JPH09330267A - Memory controller, memory control method and image generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of memory access. SOLUTION: When reading pixel data from a frame buffer 28, the same row address is generated at a timing generation circuit 271 and further, the column addresses of plural pixel data on that same row address are successively generated and applied to the frame buffer 28. At such a time, the column addresses are supplied to a column address buffer 272 as well and stored. Then, an arithmetic processing circuit 274 successively performs arithmetic by using the pixel data read from the frame buffer 28 and the pixel data supplied from the outside and when writing this arithmetic result into the frame buffer 28, the column addresses stored in the column address buffer 272 are applied to the frame buffer 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, a memory control method, and an image generation device. Particularly, for example, in a three-dimensional computer graphic system, when a three-dimensional model (three-dimensional image) is displayed by frequently performing coordinate conversion such as rotation, movement, and enlargement / reduction, when the display image is generated, etc. The present invention relates to a memory control device and a memory control method suitable for use, and an image generation device.

[0002]

2. Description of the Related Art For example, a computer graphics system is a system for creating and displaying an image (video) by a computer and a graphics peripheral device.
It is used in many fields such as CAD systems for design support in electricity, architecture, simulation of reactions and responses in chemistry, aviation, control, etc., as well as education, art, and video games.

As the computer graphics system as described above, a system provided with a three-dimensional image generating device for producing a three-dimensional image (three-dimensional image) mainly utilizing the numerical calculation ability of a computer (hereinafter, three-dimensional graphic). System).

[0004] The three-dimensional graphic system is a system for displaying a screen of a three-dimensional model in a computer by frequently performing coordinate conversion such as rotation, movement, and enlargement / reduction. It requires advanced techniques such as perspective transformation, shading, and hidden line / hidden surface elimination.

Here, in the three-dimensional graphic system, a pixel calculation process for performing calculation for each pixel is performed in order to change the three-dimensional model into various states in space, but in order to perform this pixel calculation process. Requires the combination and comparison of the pixel data obtained from the stereo model and the pixel data already obtained and stored in the frame buffer or the like. Therefore, in a three-dimensional graphic system, pixel data already stored therein is read (read) from a frame buffer, and arithmetic processing using the pixel data and newly input (generated) pixel data is performed. Is performed, and the operation result is written back to the frame buffer (hereinafter, such an operation (process) is referred to as a read-modify-write operation as appropriate).

FIG. 7 shows an example of the configuration of a three-dimensional image generating apparatus in a conventional three-dimensional graphic system. In FIG. 7, the three-dimensional image generation apparatus includes a request buffer 101 as a storage circuit that holds a pixel data write request from a block (not shown), and a memory control circuit 102 that performs memory control according to the write request.
As a memory for storing pixel data, for example, a synchronous DRAM (Dynamic Random Access Memory) (SD
A frame buffer 103 including a RAM (Syncronous DRAM) or the like is provided.

In the frame buffer 103, data writing and reading are performed in an area specified by two addresses of a row address and a column address.

The memory control circuit 102 reads a write request from the request buffer 101, and generates a physical address ADR of the frame buffer 103 and a control signal CTL.
Pixel data read from the frame buffer 103,
And an arithmetic processing circuit 102B that performs pixel arithmetic processing using the pixel data for which a write request has been made.

The timing generation circuit 102A receives, for example, an address as a write request from the request buffer 101 via the address bus 104, and the generated address ADR or control signal CTL is sent to the control bus 106 or the address bus. The data is supplied to the frame buffer 103 via the respective 107. The arithmetic processing circuit 102B receives the data (pixel data) output together with the address from the request buffer 104 via the data bus 105, and
Pixel data DATA is transmitted / received to / from the frame buffer 103 via the data bus 108.

In the three-dimensional image generating apparatus configured as described above, when the read-modify-write operation is performed on, for example, three arbitrary pixels (pixels) in the same row address of the frame buffer 103, FIG. As shown in FIG. 1, first, the timing generation circuit 102A activates the row address corresponding to the write request from the request buffer 101 at the clock clk = “0”. The control signal Ract for instructing the control bus 10
6, and the row address Row0 corresponding to the write request is supplied via the address bus 107. As a result, the frame buffer 103 latches the address Row0 from the timing generation circuit 102A as a row address, and activates the area corresponding to the row address Row0.

Next, the timing generation circuit 102A receives the frame buffer 103 at the clock clk = "2".
To the column read access operation signal Rd
c is supplied via the control bus 106,
The column address Col0 corresponding to the write request is supplied via the address bus 107.

As a result, the frame buffer 103 is
The address Col0 from the timing generation circuit 102A is latched as a column address. And frame buffer 1
03 is a row address from the timing generation circuit 102A
The pixel data Rpd0 stored in the area specified by Row0 and the column address Col0 is read out, and the data bus 108 is read.
Is supplied to the arithmetic processing circuit 102B via.

Next, the arithmetic processing circuit 102B uses the clock
When clk = “5”, the pixel data Rpd0 from the frame buffer 103 is received. Here, the request buffer 101 also outputs image data corresponding to the write request (address) when it outputs the write request, and the image data is received by the arithmetic processing circuit 102B via the data bus 105. . When the arithmetic circuit 102B receives the pixel data Rpd0 from the frame buffer 103, the arithmetic circuit 102B performs arithmetic processing using this pixel data Rpd0 and the pixel data from the request buffer 101.
Pixel data Wpd0 to be newly written in the frame buffer 103 is generated.

Then, the timing generation circuit 102A is
When the clock clk = “8”, the frame buffer 10
3, the control signal Wrc for instructing the column write access operation is supplied via the control bus 106, and the same column address Col0 as the one generated last time is supplied.
Is supplied via the address bus 107. This allows
The pixel data Wpd0 obtained as a result of the arithmetic processing in the arithmetic processing circuit 102B is supplied to the area specified by the row address Row0 and the column address Col0 of the frame buffer 103.

With respect to the remaining two pixel data in the same row address, when the clock clk = “9” to “15” or “17” to “23”, the above-mentioned clock cl
The pixel data Wpd1 is stored in the area indicated by the row address Row0 and the column address Col1 by performing the access to the frame buffer 103 and the arithmetic processing according to the same procedure as in the case of k = “2” to “8”. Pixel data in the area indicated by row address Row0 and column address Col2
Wpd2 is supplied respectively.

As described above, 3 in the same row address
The pixel data for the pixel is the frame buffer 103
Then, the timing control circuit 102A supplies the control signal Pchrg instructing the precharge operation to the frame buffer 103 via the control bus 106 at the clock clk = “25”. As a result, the pixel data Wpd0, which is supplied to the activated row address Col0,
Wpd1 and Wpd2 are written in the corresponding areas (memory cells) of the frame buffer 103.

In FIG. 8, the clock clk is "0".
Throughout the period tRCD of "1", the timing generation circuit 102A
From the generation of the row address Row0 and the control signal Ract until the frame buffer 103 latches Row0 as the row address and the data in the row address Row0 is activated.

During the period tCL in which the clock clk is "2" to "4", the timing generation circuit 102A outputs the column address C.
This is a period from when the ol0 and the control signal Rdc are generated until the pixel data Rpd0 read from the frame buffer 103 becomes valid. The same applies to the periods in which the clock clk is “9” to “11” and the periods “17” to “19”.

Further, the clock clk is "5" to "7".
The period tRMW is a period from when the read pixel data Rpd0 becomes valid until the calculation in the calculation processing circuit 102B ends. Clock clk is "12" to "14"
The same applies to the period of time and the period of “20” to “22”.

Further, the clock clk is "23" to "2".
The period “4” of tRAS is a period until the access to the data of the same row is completed and the precharge operation becomes possible.

Further, the clock clk is "25" to "2".
The period tRP of 6 ”is a period until the precharge operation is performed and a new row address can be activated.

Of the above periods, the periods tRCD, tC
L, tRAS, and tRP are defined by the standard of the DRAM (SDRAM) that constitutes the frame buffer 103, and the period tRMW varies depending on the content of the arithmetic processing in the arithmetic processing circuit 102B. FIG.
In the above, the periods tRP, tRCD, and tRAS require two clocks, and the periods tCL and tRMW require three clocks.

[0023]

By the way, in the conventional three-dimensional image generation apparatus as described above, in the case of performing the read modify write operation, the read operation is performed in units of one pixel (reading of pixel data from the frame buffer 103). , Arithmetic processing, write operation (frame buffer 10
The writing of the calculation result to 3) is repeated. Therefore, as shown in FIG. 8, an extra cycle other than data transfer, that is, the periods tCL and tRMW is required for each pixel, and it is difficult to say that the memory access efficiency is good.

Specifically, the period required for the read-modify-write operation is calculated by the formula tRCD + number of pixels × (tCL + tRMW) + tRAS + tRP + (number of pixels−
1), and as can be seen from this equation, the extra cycles of the periods tCL and tRMW are required in proportion to the number of pixels. For example, 3 in the case shown in FIG.
The period required for a pixel read-modify-write operation is 2
It is 7 clocks, and the processing efficiency of pixel calculation in this case, that is, the number of clocks spent for processing 1 pixel is 9 clocks (= 27 clocks / 3 pixels).

The present invention has been made in view of such a situation, and it is possible to improve the efficiency of memory access.

[0026]

According to another aspect of the present invention, there is provided a memory control device including: generating means for generating first and second addresses; address storing means for storing an output of the generating means; and output of the generating means. , Or a storage means for selecting one of the stored values of the address storage means and giving it to the memory.

According to another aspect of the memory control method of the present invention, the same first address is generated and given to the memory, and second addresses of a plurality of stored data are sequentially generated and given to the memory. While reading the stored data of
A plurality of calculation results using a plurality of input data and a plurality of stored data by storing the second addresses of the plurality of stored data and sequentially giving the second addresses of the stored plurality of stored data to the memory. It is characterized by writing.

An image generating apparatus according to a fifth aspect is specified by pixel data generating means for generating pixel data for pixels inside a unit figure based on vertex data, and first and second addresses. Data storage means for reading and writing data in the area;
Of the pixel data generated by the pixel data generation means and the data stored in the data storage means, the calculation means for performing a predetermined calculation, the generation means for generating the first and second addresses, and the generation means. It is characterized by comprising address storage means for storing the output, and selection means for selecting one of the output of the generation means or the storage value of the address storage means and giving it to the data storage means.

In the memory control device according to the first aspect, the generating means generates the first and second addresses,
The address storage means stores the second address generated by the generation means while the first addresses of the plurality of stored data to be operated with the plurality of consecutively input data are the same. It is done like this. The selection means selects the output of the generation means or the storage value of the address storage means when reading the storage data from the memory or writing the calculation result using the input data and the storage data to the memory, respectively. It is designed to give.

In the memory control method according to the fourth aspect, the same first address is generated and given to the memory, and second addresses of a plurality of stored data are sequentially generated and given to the memory. Reading a plurality of stored data and storing a second address of the plurality of stored data,
By sequentially applying the second addresses of the stored plurality of stored data to the memory, a plurality of calculation results using the plurality of input data and the plurality of stored data are written.

In the image generating apparatus according to the fifth aspect, the image data generating means generates the pixel data for the pixels inside the unit graphic based on the vertex data, and the data storing means includes the first and first data. Data is read and written in the area specified by the address 2. The calculation means performs a predetermined calculation using the pixel data generated by the pixel data generation means and the data stored in the data storage means, and the generation means generates the first and second addresses. Has been done. The address storing means is operated by the generating means while the first address of the data stored in the data storing means is the same, which is operated with the plurality of pixel data continuously output by the pixel data generating means. The second address generated is stored, and the selection means stores the output of the generation means or the storage value of the address storage means when reading the data from the data storage means or when writing the calculation result of the calculation means to the data storage means. Each is selected and given to the data storage means.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The three-dimensional image generating apparatus according to the present invention is applied to, for example, a three-dimensional image generating apparatus (hereinafter, simply referred to as an image generating apparatus) 2 of a three-dimensional computer graphic system 300 as shown in FIG.

First, in the three-dimensional computer graphic system 300, the input device 1 and the display device 3 are connected to the image generating device 2.

The image generating device 2 includes a transfer circuit 21 to which the output of the input device 1 is supplied and a geometry calculation circuit 22 (vertex data generating means) to which the output of the transfer circuit 21 is supplied.
And a parameter calculation circuit 23 to which the output of the geometry calculation circuit 22 is supplied, and a pixel generation circuit 24 (image data generation means) to which the output of the parameter calculation circuit 23 is supplied.
A mapping circuit 25 to which the output of the pixel generation circuit 24 is supplied, a memory control circuit 27 to which the output of the mapping circuit 25 is supplied, and a display control circuit 29 to which the output of the memory control circuit 27 is supplied. The output of the display control circuit 29 is supplied to the display device 3.

The image generating apparatus 2 also includes a texture memory 26 connected to the mapping circuit 25, and a frame buffer 28 (data storage means) connected to the memory control circuit 27.

First, the input device 1 is used to generate the image generation device 2
, Polygon data relating to polygons (unit figures) constituting an arbitrary three-dimensional model is input. That is, in the three-dimensional computer graphic system of FIG. 1, a three-dimensional model (three-dimensional image) is decomposed into a plurality of polygons,
By rendering each of these polygons, the entire three-dimensional model is displayed (thus, it can be said that the three-dimensional model is defined by a combination of polygons). Is supplied with polygon data for such polygons.

In the image generation device 2, the transfer circuit 21 transfers the polygon data from the input device 1 by direct memory access (DMA) transfer.
The data is transferred to the geometry calculation circuit 22 at a high speed.

Here, the image generating apparatus 2 represents a three-dimensional object by using the z coordinate indicating the depth in addition to the (x, y) coordinate indicating the plane, and the three coordinates x, y, and z are used. It is designed to represent any one point in the three-dimensional space.

For the polygon, each vertex is the main data. That is, by performing geometric transformation on each vertex, the surface can be transformed, and finally the polygon can be geometrically transformed. The geometric transformation includes a translation transformation, a parallel transformation, and a rotation transformation.

Therefore, in order to change the polygon input by the input device 1 to various positions in the space, the geometry operation circuit 22 causes the vertex data (x) of the polygon data from the transfer circuit 21 in the three-dimensional space. , Y, z) is subjected to the above-described geometrical conversion processing (hereinafter referred to as geometry conversion processing). Then, the geometry operation circuit 22
Supplies the polygon data subjected to the geometry conversion processing to the parameter calculation circuit 23.

The parameter calculation circuit 23 obtains a parameter necessary for generating pixel data inside the polygon in the pixel generation circuit 24 based on the polygon data from the geometry calculation circuit 22 and supplies it to the pixel generation circuit 24.

The pixel generation circuit 24 is set up by the parameters from the parameter calculation circuit 23, and corresponds to the pixel data such as the color data and the depth data inside the polygon data which has been subjected to the geometry conversion processing by the geometry calculation circuit 22 and the display. The address on the two-dimensional plane is generated and supplied to the mapping circuit 25.

The mapping circuit 25 is a pixel generation circuit 24.
Texture mapping processing is performed using the texture data stored in the tech texture memory 26 in accordance with the pixel data and address from. Then, the mapping circuit 25 supplies the pixel data and the address on which the texture mapping processing has been performed to the memory control circuit 27.

The memory control circuit 27 includes the mapping circuit 2
The pixel data corresponding to the address starting from No. 5 is read out from the frame buffer, and pixel calculation processing is performed using the pixel data and the pixel data from the mapping circuit 25. Then, the memory control circuit 27 writes the pixel data obtained as a result of the pixel operation processing into the frame buffer 28. Further, the memory control circuit 27 converts the pixel data of the display area designated by the display control circuit 29 into
It is read from the frame buffer 28 and supplied to the display control circuit 29.

A detailed description of the memory control circuit 27 and the frame buffer 28 will be given later.

The display control circuit 29 requests the memory control circuit 27 for pixel data of the display area to be displayed, and receives the pixel data supplied from the memory control circuit 27 in response to the request. Then, the display control circuit 29 converts the pixel data into an analog signal and supplies it to the display device 3.

As a result, a screen corresponding to the pixel data (image signal) from the display control circuit 29 is displayed on the display device 3.

Next, the memory control circuit 27 and the frame buffer 28 described above will be described in detail.

Memory control circuit 27 and frame buffer 2
8 is, for example, the memory control circuit 102 shown in FIG.
And the same connection as in the frame buffer 103. That is, the memory control circuit 27 and the frame buffer 28 are connected by one control bus 106, one address bus 107, and one data bus 108, as shown in FIG. Then, the memory control circuit 27 is configured to access the frame buffer 28 by outputting the control signal CTL or the address ADR via the control bus 106 or the address bus 107, respectively. In addition, the data bus 1 is provided between the memory control circuit 27 and the frame buffer 28.
Data DATA is exchanged via 08.

The memory control circuit 27 includes a timing generation circuit 271 (generation means) (instruction means), a column address buffer 272 (address storage means), and a selection circuit 273.
(Selection means), arithmetic processing circuit 274 (arithmetic means), write data buffer 275, and bidirectional buffer 276.
It is composed of

The timing generating circuit 271 generates a control signal CTL for the frame buffer 28 and supplies it to the frame buffer 28 via the control bus 106. Also, the timing generation circuit 27
1 is a row address and a column address (first and second addresses) corresponding to the address of the pixel data supplied from the mapping circuit 25 via the address bus 104.
Is generated and supplied to the column address buffer 272 and the select circuit 273 via the address bus 111. Furthermore, the timing generation circuit 271
Select circuit 2 via control bus 109
73 and the bidirectional buffer 276 are also controlled.

The column address buffer 272 is, for example, FI.
It is configured to include an FO (First In First Out) type memory, and stores a column address generated by the timing generation circuit 271 as necessary. The column address stored in the column address buffer 272 is
The data is supplied to the select circuit 273 via the address bus 112.

The select circuit 273, under the control of the timing generating circuit 271, has the timing generating circuit 27.
One of the address (row address, column address) output by 1 or the column address output by the column address buffer 272 is selected and supplied to the frame buffer 28 via the address bus 107. There is.

The arithmetic processing circuit 274 is the mapping circuit 2
5 and the pixel data supplied from the frame buffer 28.
, And performs arithmetic processing using the pixel data supplied through the bidirectional buffer 276, and supplies pixel data as the operation result to the write data buffer 275 via the data bus 114. It has been made like that. The write data buffer 275 temporarily stores the pixel data supplied from the arithmetic processing circuit 274, and supplies the pixel data to the bidirectional buffer 276 via the data bus 115. The bidirectional buffer 276 receives the pixel data read from the frame buffer 28 and supplied via the data bus 108, and receives the pixel data.
The pixel data supplied from the write data buffer 275 is supplied to the arithmetic processing circuit 274 via the data bus 108 and is supplied to the frame buffer 28 via the data bus 108.

The frame buffer 28 has the same structure as the frame buffer 103 shown in FIG.

Memory control circuit 2 configured as described above
7, the pixel data to be processed is sent from the mapping circuit 25 via the data bus 105, and the address for the pixel data is sent to the address bus 10.
4 is input.

For example, now, three pixel data Pix0, Pix1, Pix2 in the same row address of the frame buffer 28 are successively input from the mapping circuit 25, and pixel data Pix3 of different row addresses are then input. In the case where the read modifier write operation is performed for
As shown in FIG. 11, first, the timing generation circuit 271 receives the pixel data Pix0, Pix1, and Pix at the clock clk = “0”.
A control signal Ract that directs a row active operation to activate a row address according to the address for ix2
Is generated and supplied to the frame buffer 28 via the control bus 106. At the same time, the timing generation circuit 2
71 generates the same row address Row0 corresponding to the three pixel data Pix0, Pix1, and Pix2, and supplies it to the select circuit 273 via the address bus 111.

At this time, the timing generation circuit 271
The selection circuit 273 is controlled so as to select the output of the timing generation circuit 271.
Row0 is selected by the select circuit 273 and supplied to the frame buffer 28 via the address bus 107.

As a result, the frame buffer 28 latches the address Row0 from the timing generation circuit 271 as a row address, and activates the area corresponding to the row address Row0 in accordance with the control signal Ract.

Then, the timing generating circuit 271 generates a signal Rdc instructing a column read access operation at the clock clk = “2”, and the control bus 10
6 to the frame buffer 28. further,
The timing generation circuit 271 controls the select circuit 273 so as to select the output, and also the bidirectional buffer 276 so as to transfer the data in the read direction (from the frame buffer 28 to the arithmetic processing circuit 274).
Control. After that, the timing generation circuit 271 determines that the column address Co corresponding to the first image data Pix0 in the same row.
l0 is generated and output via the address bus 111.

The column address Col0 is supplied to the column address buffer 112 and the select circuit 273. The column address buffer 112 receives and stores the column address Col0 from the timing generation circuit 271. Further, the select circuit 273 selects the column address Col0 from the timing generation circuit 271 and supplies it to the frame buffer 28 via the address bus 107.

The frame buffer 28 latches the address Col0 generated by the timing generation circuit 271 as a column address. Then, the frame buffer 28 reads the pixel data Rpd0 stored in the area specified by the row address Row0 and the column address Col0, and the data bus 1
It supplies to the bidirectional buffer 276 via 08.

The bidirectional buffer 276 is controlled so as to transfer data in the read direction as described above. Therefore, in this case, the image data Rpd0 from the frame buffer 28 passes through the bidirectional buffer 276. Are supplied to the arithmetic processing circuit 274.

Next, the timing generation circuit 271 generates the signal Rdc for instructing the column read access operation at the clock clk = “3”, and outputs 2 in the same row.
A column address Col1 corresponding to the image data Pix1 is generated, and the same processing as in the case of the clock clk = "2" is performed.

As a result, the column address Col1 is stored in the column address buffer 272, and the pixel data Rpd1 is read from the area specified by the row address Row0 and the column address Col1 of the frame buffer 28, and the arithmetic processing circuit 274.

Further, the timing generation circuit 271 generates the signal Rdc for instructing the column read access operation and the column address Col2 corresponding to the third image data Pix2 in the same row at the clock clk = “4”. After that, the same process as in the case of the clock clk = “2” is performed.

As a result, the column address Col2 is also stored in the column address buffer 272, and the pixel data Rpd2 is read from the area specified by the row address Row0 and the column address Col2 of the frame buffer 28, and the operation is performed. It is supplied to the processing circuit 274.

The arithmetic processing circuit 274 has a structure capable of pipeline processing, for example, and clock clk =
At “5”, the arithmetic processing using the pixel data Pix0 and Rpd0 is performed at the clock clk = “6”.
The arithmetic processing using the pixel data Pix2 and the Rpd2 is performed at the clock clk = “7”.
Start each. Then, the arithmetic processing circuit 274 outputs pixel data Wpd0, Wpd1, Wpd2 obtained as a result of each arithmetic processing.
Are sequentially supplied to the write data buffer 275. The write data buffer 275 is formed of, for example, a FIFO type memory, and sequentially stores the pixel data Wpd0, Wpd1, and Wpd2 supplied from the arithmetic processing circuit 274.

On the other hand, when the timing generation circuit 271 receives the address corresponding to the pixel data Pix3, the row address of the pixel data Pix0 to Pix2
Of the pixel data Wpd0 to Wpd2 stored in the write data buffer 275 is started and the write control of the pixel data Wpd0 to Wpd2 is started on the data bus 108 between the pixel data Rpd2 and Wpd0. In order to avoid the collision of the above, the waiting state is set when the cloku clk = “8”.

After that, the timing generation circuit 271 sends the control signal Wrc instructing the column write access operation at the clock clk = "9" to the control bus 106.
It is supplied to the frame buffer 28 via Further, the timing generation circuit 271 controls the select circuit 273 so as to select the output of the column address buffer 272, and transfers the data in the write direction (the direction from the write data buffer 275 to the frame buffer 28). It controls the bidirectional buffer 276.

Then, from the column address buffer 272, the column address stored first, that is, the image data Wpd0
Is read out and supplied to the selector circuit 273. In this case, the selector circuit 273 selects the column address Col0 from the column address buffer 272 and supplies it to the frame buffer 28 via the address bus 107. At the same time, the pixel data Wpd0 stored first is also read from the write data buffer 275 and supplied to the bidirectional buffer 276. In this case, the bidirectional buffer 276 is controlled so as to transfer data in the write direction, and therefore the image data Wpd0 from the write data buffer 275 is supplied to the frame buffer 28 via the data bus 108. It

As a result, in the area indicated by the row address Row0 and the column address Col0 of the frame buffer 28,
The image data Wpd0 obtained by the arithmetic processing circuit 274 is supplied.

Hereinafter, the clocks clk = "10" and "1"
1 ”also, the timing generation circuit 271 performs the same processing, whereby the frame buffer 28 causes the column address buffer 2 to operate at the clock clk =“ 10 ”.
The column address Col1 stored second in 72 and the pixel data Wpd1 stored second in the write data buffer 275 are supplied, and at the clock clk = “11”,
The column address Col2 stored third in the column address buffer 272 and the pixel data Wpd2 stored third in the write data buffer 275 are supplied.

As a result, at the clock clk = "10", the image data Wpd1 is supplied to the area indicated by the row address Row0 and the column address Col1 of the frame buffer 28, and at the clock clk = "11". Row address Row0 and column address Co of frame buffer 28
The image data Wpd2 is supplied to the area indicated by l2.

Then, the timing generation circuit 271 supplies the control signal Pchr instructing the precharge operation to the frame buffer 28 via the control bus 106 at the clock clk = “12”. As a result, the pixel data Wpd0 to Wpd2 supplied to the area of the row address Row0 activated by the control signal Ract is changed to the row address Rod.
Data is written in the regions (memory cells) corresponding to w0 and column addresses Col0 to Col2, respectively.

In FIG. 3, the timing generation circuit 2 operates during the period tRCD in which the clock clk is "0" to "1".
This is a period from when the row address Row0 and the control signal Ract are generated by 71 to when the frame buffer 28 latches Row0 as the row address and the pixel data in the row address Row0 is activated.

During the period tCL0 in which the clock clk is "2" to "4", the timing generation circuit 271 outputs the column address Co.
This is the period from the generation of l0 and the control signal Rdc until the image data Rpd0 read from the frame buffer 28 becomes valid. Similarly, in the period tCL1 in which the clock clk is “3” to “5”, from the timing generation circuit 271 generating the column address Col1 and the control signal Rdc until the image data Rpd1 read from the frame buffer 28 becomes valid. In the period tCL2 in which the clock clk is "4" to "6", the image data Rpd2 read from the frame buffer 28 is valid after the timing generation circuit 271 generates the column address Col2 and the control signal Rdc. It is a period until.

Further, the clock clk is "5" to "7".
During the period tRMW0, after the pixel data Rpd0 becomes valid,
This is a period until the arithmetic processing in the arithmetic processing circuit 274 using the pixel data Rpd0 ends. Similarly, during the period tRMW1 when the clock clk is “6” to “8”, the pixel data Rp
This is a period from the time when d1 becomes effective to the time when the arithmetic processing in the arithmetic processing circuit 274 using the pixel data Rpd1 ends, and the period tRMW2 in which the clock clk is “7” to “9”.
Is a period from when the image data Rpd2 becomes valid to when the arithmetic processing in the arithmetic processing circuit 274 using the image data Rpd2 ends.

Further, the clock clk is "11" to "1".
The period "2" tRAS is a period until the access to the image data of the same row address is completed and the precharge operation becomes possible.

Further, the clock clk is "13" to "1".
The period tRP of 4 ”is a period until the precharge operation is performed and a new row address can be activated.

Note that periods tRCD and tC in FIG.
L and tRMW also represent the same period as in FIG.

Further, as described above, the periods tRCD, tCL, t
RAS and tRP are the DRA that constitutes the frame buffer
It is defined by the standard of M, and the period tRMW varies depending on the content of the arithmetic processing in the arithmetic processing circuit 274. In FIG. 3 (also in FIG. 6), as in the case of FIG. 8 described above, the periods tRP, tRC
2 clocks for D and tRAS, 3 for periods tCL and tRMW
There is a clock, respectively.

Next, the efficiency of pixel calculation processing in the read-modify-write operation performed by the memory control circuit 27 and the frame buffer 28 will be described.

In the case shown in FIG. 3, the period required for the read-modify-write operation can be obtained from the equation tRCD + tCL + tRMW + the number of pixels + tRAS + tRP. Therefore, the period required for the read-modify-write for three pixels is 15 clocks. The 15 clocks are in the conventional case (Fig. 8).
12 clocks less than 27 clocks of
This is because the periods tCL0 to tCL2 and tRMW0 to tRMW2 overlap as shown in FIG. That is, the period required for read-modify-write is shortened by reading pixel data and performing pixel calculation processing in parallel.

In this case, the processing efficiency of pixel calculation, that is, the number of clocks consumed for processing one pixel is 5, and therefore the number of processing clocks per pixel in the above-described conventional three-dimensional image generating apparatus is 9 clocks. As can be seen from comparison with the clock, the efficiency of memory access is improved.

Further, the number of processing clocks per pixel in the conventional three-dimensional image generation apparatus is the period tCL and tRMW.
However, since it is required for each pixel, it is not reduced depending on the number of pixel data of the same row address that can be continuously processed. However, in the image generation device 2, in the periods tCL and tRMW.
However, since the number of clocks is constant regardless of the number of pixel data of the same row address that can be continuously processed, the larger the number of pixel data that can be continuously processed, the more
The number of processing clocks per pixel can be reduced.

In general, the three-dimensional image generating apparatus has locality of memory access (there are many consecutive accesses to the same row address). Therefore, when this is taken into consideration, the performance is sufficiently improved. be able to.

In order to prevent the column address buffer 272 from overflowing, the column address buffer 2 is stored so that the maximum number of column addresses to which pixel data of the same row address are continuously supplied can be stored.
Although it is necessary to configure 72, it is rare that such a number of column addresses needs to be stored, and in such a rare case, the column address buffer 272 is configured by the device. It is not preferable in terms of scale and cost.

Therefore, when the column address buffer 272 is made to be able to store only a number of column addresses smaller than the maximum number of pixel data of the same row address which are continuously supplied, it is necessary to prevent the overflow. There is.

Further, when the column address buffer 272 is composed of only a FIFO type memory, a problem occurs when pixel data of the same row address and the same column address is supplied to the memory control circuit 27.

Specifically, for example, as shown in FIG.
The pixel data A has already been stored in the column address Col0 of the row address Row0 of the frame buffer 28, and the pixel data A
When the pixel data B is stored in a different column address Col1 of the same row address Row0 as the column address Row0 of the memory control circuit 27
The pixel data a of Col0 is supplied, and then the row address Row0
Of the column address Col1 of the column address Col0 of the same row address Row0 as the first row address
When the pixel data c of 1 is supplied, according to the processing of the memory control circuit 27 described above, the arithmetic processing circuit 274 cannot obtain the expected arithmetic result.

That is, now, let us say that the calculation result (image data) obtained by performing the calculation using the image data X and Y in the calculation processing circuit 274 is expressed as XY. By sequentially supplying the data a, b, and c, the arithmetic processing circuit 274 sequentially obtains the arithmetic results of the image data aA, bB, and cA.

However, regarding the image data c,
Originally, calculation with the calculation result aA using the image data a and A should be performed, so that the calculation result with respect to the image data c must be caA.

Therefore, the column address buffer 272 can be constructed, for example, as shown in FIG. In this embodiment, the column address buffer 272 is a FIF.
It is composed of an O memory 2721 (detection means), a comparator 2722 (detection means), and an OR operation circuit 2723.

The FIFO memory 2721 temporarily stores the column address supplied from the timing generation circuit 271,
It is adapted to be supplied to the select circuit 273. The FIFO memory 2721 is a FIFO type memory, and in this embodiment, it has four stages (however, F
The number of stages of the IFO memory 2721 is not limited to four). Therefore, the FIFO memory 2721 can store up to four column addresses. Further, the FIFO memory 2721, when storing the four storable column addresses, detects that the free area of itself has run out, and the OR operation circuit 2723
For example, a 1 (H level) FULL signal is also output. Note that the FIFO memory 2721 is
In other cases, for example, a FULL signal of 0 (L level) is output to the OR operation circuit 2723.

The comparator 2722 is used in the timing generation circuit 2
71 receives the same column address as that supplied to the FIFO memory 2721,
The column address already stored in the memory 2721 is compared, thereby detecting that the same column address as the column address stored in the FIFO memory 2721 is generated in the timing generation circuit 271. Has been done. The comparator 2722 is used in the FIFO memory 2
When it is detected that the same column address as the column address stored in 721 is generated in the timing generation circuit 271, normally, for example, the DT signal which is 0 is set to 1 and the logical sum operation is performed. It is adapted to output to the circuit 2723.

The logical sum operation circuit 2723 obtains the logical sum of the FULL signal from the FIFO memory 2721 and the DT signal from the comparator 2722, and outputs the logical sum as the EQ signal to the timing generation circuit 271. Has been done. Therefore, in the timing generation circuit 271,
When there is no free space in the FIFO memory 2721, when the same column address as the column address stored in the FIFO memory 2721 is generated in the timing generation circuit 271, and the EQ signal of 1 is other than that. Is provided with an EQ signal of zero.

Under the column address buffer 272 configured as described above, when the pixel data a to c described in FIG. 4 are supplied and the read modifier write operation to the frame buffer 28 is performed. As shown in FIG. 6, first, the timing generation circuit 271 sets the clock clk = “0” to the clock clk = “0”.
As in the case of "0", the control signal Rac and the row address Row0 are generated and supplied to the frame buffer 28. As a result, in the frame buffer 28, the address
Row0 is latched as a row address and its row address Ro
The area corresponding to w0 is activated.

Next, the timing generating circuit 271 supplies the signal Rdc instructing the column read access operation to the frame buffer 28 via the control bus 106 at the clock clk = “2”. Further, the timing generation circuit 271 controls the select circuit 273 so as to select the output, and controls the bidirectional buffer 276 so as to transfer the data in the read direction.
Then, the timing generation circuit 271 generates the column address Col0 of the image data a and supplies it to the frame buffer 28 via the selection circuit 273. The column address Col0 is also supplied to the column address buffer 272 and stored in its FIFO memory 2721.

When the frame buffer 28 receives the address Col0 from the timing generation circuit 271, it latches it as a column address and stores it in the area specified by the column address Col0 and the row address Row0 previously supplied. The pixel data A stored in the bidirectional buffer 27
It is supplied to the arithmetic processing circuit 274 via 6.

Next, the timing generation circuit 271 performs the control signal Rdc and the image data b at the clock clk = “3” in the same manner as at the clock clk = “2”.
Column address Col1 of is generated. As a result, the column address Col1 is stored in the FIFO memory 2 in the same manner as described above.
The pixel data B stored in the area 721 and stored in the area specified by the row address Row0 and the column address Col1 of the frame buffer 28 is read and supplied to the arithmetic processing circuit 274.

The timing generation circuit 271 is also adapted to generate a column address to be output next, and the column address is supplied to the comparator 2722 first. Therefore, in this case, the clock
When clk = “3”, the column address Col0 of the image data c
Are supplied to the comparator 2722. At this time, the FIFO
Since the memory 2721 stores the column address Col0 of the image data a that matches the column address Col0 of the image data c, the comparator 2722 is configured to perform the OR operation circuit 2723.
Then, the DT signal of 1 is output. As a result, the OR signal 2723 outputs an EQ signal of 1.
The Q signal is transmitted via the control bus 110 (FIG. 2),
It is supplied to the timing generation circuit 271.

When the timing generation circuit 271 receives the EQ signal of 1, the reading (reading) from the frame buffer 28 is interrupted and the operation result obtained so far is written (writing). Therefore, the clock clk = "4"
Through the period from "7" to "7", it is in a waiting state.

On the other hand, in the arithmetic processing circuit 274, the clock
When clk = “5” and “6”, the frame buffer 28
The calculation for obtaining the data to be written into is started. That is, the arithmetic processing circuit 274 performs the arithmetic processing using the pixel data a and A at the clock clk = “5”, and the arithmetic processing using the pixel data b and B at the clock clk = “6”. Start each. Then, the arithmetic processing circuit 274, the pixel data aA obtained as a result of each arithmetic processing,
bB is sequentially supplied to and stored in the write data buffer 275.

Then, the timing generation circuit 271 sends the control signal Wrc instructing the column write access operation at the clock clk = “8” to the control bus 106.
It is supplied to the frame buffer 28 via Further, the timing generation circuit 271 controls the select circuit 273 so as to select the output of the column address buffer 272, and also controls the bidirectional buffer 276 so as to transfer the data in the write direction.

As a result, the column address Col0 corresponding to the pixel data aA is read from the column address buffer 272 and supplied to the frame buffer 28 via the address bus 107. In addition, the write data buffer 27
From 5, the pixel data aA is read out and supplied to the frame buffer 28 via the bidirectional buffer 276 and the data bus 108. As a result, the pixel data aA is written in the area indicated by the row address Row0 and the column address Col0 of the frame buffer 28.

Similar processing is carried out also at the clock clk = “9”, whereby the image data bB is transferred to the row address Row0 and the column address Col1 of the frame buffer 28.
It is written in the area indicated by.

When the writing of all the pixel data stored in the write data buffer 275 into the frame buffer 28 is completed as described above, the timing generation circuit 271 reads from the frame buffer 28 again. At clock clk = "10",
The control signal Rdc and the column address Col0 of the pixel data c are generated, and the pixel data aA is extracted from the area specified by the row address Row0 and the column address Col0 of the frame buffer 28 as in the case of the clock clk = “2”.
Is read. This pixel data aA is stored in the bidirectional buffer 2
It is supplied to the arithmetic processing circuit 274 via 76.

In the arithmetic processing circuit 274, the clock clk =
At "13", the calculation using the pixel data c and aA is started, and thereafter, when the pixel data caA as the calculation result is obtained, the pixel data caA is supplied to and stored in the write data buffer 275. .

Then, the timing generation circuit 271 supplies the control signal Wrc and the column address Col0 of the pixel data caA to the frame memory 28 at the clock clk = “16” as in the case of the clock clk = “8”. That row address Row0 and column address Co
The pixel data caA is written in the area specified by l0.

Therefore, in this case, the frame buffer 28
In the field, caA, which should be originally obtained, is written as the calculation result of the image data c.

As described above, the column address buffer 272
If the same column address as the column address stored in is generated in the timing generation circuit 271,
Since the reading from the frame memory 28 is interrupted, the calculation results obtained up to that point are written in the frame memory 28, and then the reading is started again, the expected calculation result can be obtained.

Next, in the case where the column address buffer 272 is configured as shown in FIG. 5, the FIFO memory 2
When the free capacity of 721 is exhausted, the FULL signal of 1 is output from the FIFO memory 2721 to the OR operation circuit 2723, whereby the OR operation circuit 2723 outputs 1 to the timing generation circuit 271. EQ signal is supplied. Therefore, also in this case, the reading from the frame memory 28 is interrupted, the operation results obtained up to that point are written in the frame memory 28, and then the reading is started again.
It is possible to prevent 721 from overflowing.

[0115]

According to the memory control device of the first aspect and the memory control method of the fourth aspect, when the stored data is read from the memory, the same first address is generated and given to the memory. The second addresses of the plurality of stored data are sequentially generated and given to the memory, so that the plurality of stored data are read out and the second addresses of the plurality of stored data are stored. On the other hand, when the calculation result using the input data and the stored data is written to the memory, the second addresses of the stored plurality of stored data are sequentially given to the memory, so that the plurality of input data and the plurality of stored data are used. A plurality of calculation results are written. Therefore, it is possible to improve the efficiency of memory access.

According to the image generating apparatus of the fifth aspect,
By reading the image data from the data storage means, the same first address is generated and given to the data storage means, and the second addresses of the plurality of image data are sequentially generated and given to the data storage means. , The plurality of image data are read, and the second addresses of the plurality of image data are stored. On the other hand, when the operation result using the image data generated by the image data generating means and the image data stored in the data storing means is written in the data storing means, the second addresses of the plurality of stored data stored are the data. A plurality of calculation results are written by being sequentially given to the storage means. Therefore, it is possible to improve the efficiency of access to the data storage unit, and as a result, it is possible to improve the processing speed of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a three-dimensional computer graphic system to which the present invention has been applied.

FIG. 2 is a block diagram showing a configuration example of a memory control device 27 of FIG.

FIG. 3 is a timing chart for explaining processing of the memory control device 27 of FIG.

FIG. 4 is a diagram for explaining an inconvenience that occurs when pixel data having the same row address and the same column address is supplied to a memory control circuit 27.

5 is a block diagram showing a configuration example of a column address buffer 272 of FIG.

FIG. 6 is a timing chart for explaining processing of the memory control device 27 when the column address buffer 272 is configured as shown in FIG.

FIG. 7 is a block diagram showing a configuration of an example of a conventional three-dimensional image creating apparatus.

8 is a timing chart for explaining the processing of the memory control circuit 102 of FIG.

[Explanation of symbols]

22 geometry calculation circuit (vertex data generation means),
23 parameter calculation circuit, 24 pixel generation circuit (pixel data generation means), 25 mapping circuit, 26
Texture memory, 27 memory control circuit, 28
Frame buffer (data storage means), 29 display control circuit, 271 timing generation circuit (generation means) (instruction means), 272 column address buffer (column address storage means), 273 select circuit (selection means), 274 arithmetic processing circuit ( Computing means), 2
75 write data buffer, 276 bidirectional buffer, 2721 FIFO memory (detection means), 27
22 comparator (detection means), 2723 OR operation circuit

Claims (5)

[Claims] 1. A memory in which data is read and written in an area specified by a first address and a second address, and stored data which is subjected to a predetermined operation with input input data. A memory control device for controlling the memory for storing the first address and the second address, address generating means for storing the output of the generating means, output of the generating means, or Selecting means for selecting any one of the stored values of the address storing means and giving it to the memory, wherein the address storing means is a plurality of units that are operated with a plurality of input data that are continuously input. Storing the second address generated by the generating means while the first address of the stored data is the same, and the selecting means stores the stored data in the memory. When reading from, or when writing the operation result using the input data and the stored data to the memory, the output of the generating means or the stored value of the address storing means is selected and given to the memory. Characteristic memory control device. 2. An instruction unit for instructing the memory whether to read or write data in an area specified by the first and second addresses, and an empty area of the address storage unit. Further comprising a detection unit for detecting that the address storage unit has a vacant area when the storage unit instructs the memory to read the stored data. 2. The memory control device according to claim 1, wherein when it is detected that the input data and the storage data are exhausted, an instruction to write an operation result is issued. 3. The instructing means for instructing the memory whether to read or write data to the area specified by the first and second addresses, and the generating means, And a detection unit configured to detect that the same address as the second address stored in the storage unit is generated, wherein the instruction unit instructs the memory to read the stored data. When the detecting means detects that the generating means has generated the same second address stored in the address storage means, the input data and the stored data are used. 2. The memory control device according to claim 1, wherein the memory control device is instructed to write the calculation result of. 4. A memory for reading and writing data to and from an area specified by first and second addresses, the memory data being subjected to a predetermined operation with input input data. A memory control method for controlling what stores the data, wherein when the first addresses of a plurality of stored data to be operated with a plurality of input data that are successively input are the same, A first address is generated and given to the memory, and a second address of the plurality of storage data is sequentially generated and given to the memory to read out the plurality of storage data and at the same time to store the plurality of storage data. Second
Of the plurality of input data and the plurality of stored data by writing the second addresses of the plurality of stored data stored therein to the memory in sequence to write a plurality of calculation results using the plurality of input data and the plurality of stored data. A characteristic memory control method. 5. An image generating apparatus for generating a three-dimensional image defined by a combination of unit figures, comprising: vertex data generating means for generating vertex data on vertices of the unit figure; and based on the vertex data, Pixel data generation means for generating pixel data for pixels inside the unit figure; data storage means for reading and writing data in an area specified by the first and second addresses; Calculating means for performing a predetermined calculation using the pixel data generated by the pixel data generating means and the data stored in the data storing means; generating means for generating the first and second addresses; Any of the address storage means for storing the output of the generation means, the output of the generation means, or the storage value of the address storage means Select one, and a selection means for supplying to said data storage means, said address storage means, operation of a plurality of pixel data the pixel data generating means for successively output is performed,
The second address generated by the generation means is stored while the first address of the data stored in the data storage means is the same, and the selection means reads the data from the data storage means. At the time, or when the calculation result of the calculation means is written in the data storage means, the output of the generation means or the storage value of the address storage means is selected and given to the data storage means. Generator.