JP4482996B2 - Data storage apparatus and method and image processing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data storage device and a data storage method in a first-in first-out format (hereinafter referred to as FIFO (First In First Out) format) for data of a plurality of systems, and generation of a display image using the data storage device. The present invention relates to an image processing apparatus that can be efficiently performed.
[0002]
[Prior art]
A so-called FIFO memory that reads input data in the input order is widely used in various electronic circuits. In particular, in recent years, the processing speed has been improved in all electronic devices. As a result, there is a difference in the data processing speed between the processing units, and it is difficult to transfer the data in proper synchronization. In order to solve this problem, a FIFO memory is often provided as a buffer means between the processing units.
For example, an image processing device that generates a three-dimensional image used for a CAD device, a game machine, or the like is capable of processing many pixels such as coordinate conversion, texture mapping, special effect processing for each pixel, and high-speed display of the generated image. Various processing units that perform high-speed processing are sequentially connected. A large number of FIFO memories are used in order to transfer data between these processing units at high speed and appropriately.
[0003]
[Problems to be solved by the invention]
By the way, for example, a plurality of types of data are often transferred as necessary between the components of such an image processing apparatus. In particular, when not only image data but also control data is included, it is rare that only one specific type of data is transferred. In such a case, as shown in FIG. 7, for example, a plurality of FIFO memories are provided in parallel according to the type of data (sometimes referred to as a data system).
However, when a plurality of FIFO memories are provided in parallel as described above, a margin must be secured for each system, or a control unit is provided independently despite a lot of common signal processing. There is a problem that the circuit cannot be used efficiently, that is, the circuit scale becomes larger than necessary.
In particular, since such a circuit is often realized as a semiconductor integrated circuit, there is a demand for reducing the circuit scale, in other words, the gate scale of the circuit as much as possible.
[0004]
Accordingly, it is an object of the present invention to provide a data storage device and method thereof that can appropriately provide a FIFO function for data of a plurality of systems with a smaller circuit scale.
Another object of the present invention is to provide an image processing apparatus capable of appropriately transferring data in each processing means with a smaller circuit scale, thereby efficiently performing desired image processing.
[0005]
  In order to solve the above problems, a data storage device according to the present invention manages data storage means for sequentially storing input data of a plurality of systems, and the storage order of data stored in the data storage means for each system. In response to a data output request for each system, the storage order management means that performs the storage of the requested system based on the data storage order for each system managed by the storage order management means. Output means for reading out and outputting data in the order of input, and the storage order management means is an arbitrary free area other than the area in which the data that has not yet been read is stored in the data storage means. Storage address generation means for generating the address of the input as a storage address for storing the input data, and for each of the systems, the last input and stored data Address storage means for storing the storage address, and an address space corresponding to the address space of the data storage means, and the same as the data stored at the corresponding address of the data storage means as the data of each address The address of the data storage means in which the data inputted and stored next to the data of the address is stored in the input data of the system ofTeTable and the input data of any system stored in the generated storage address of the data storage means, the generated storage at the address stored in the address storage means of the table Table updating means for storing addresses, and the storage address generating means includes a flag indicating whether or not unread data is stored in the address for each address of the data storage means. Based on the flag storage means for storing and the stored flag, the free area of the data storage means is detected, and a storage address selection for selecting the address of any one of the free areas as the storage address And the storage of newly input data and the reading of the stored data by the output means, And a flag updating means for updating the lug, said data storage means, the address generated by the memory address generating means, for storing data of any line that is the input.
[0006]
  According to a second aspect of the present invention, there is provided a data storage method for a data storage device having a data storage means, a storage order management means, and an output means, wherein a plurality of input data are stored in a memory. 1 step, a second step of managing the storage order of the stored data for each system, and storage of the data for each managed system in response to an output request for data for each system A third step of reading out and outputting the stored data of the requested system in the input order based on the order, and the second step is performed at the end for each of the systems. A fourth step of storing the storage address for the data input and stored in the memory, and a region in which data not yet read out of the memory is stored when data of an arbitrary system is input A fifth step of generating an arbitrary address of a free area other than as a storage address for storing the input data,It has an address space corresponding to the address space of the data storage means, and the input data of the same system as the data stored in the corresponding address of the data storage means as the data of each address, the address The address of the data storage means in which the data input and stored next to the data is stored is stored.In the storage address of the table, the data input and stored at the end of the stored system,When the input data is stored at the generated storage address of the memory,A sixth step of storing the generated storage address, wherein the fourth step includes a flag indicating whether or not unread data is stored in each address of the memory. A seventh step to be set, an eighth step of detecting the free area of the memory based on the stored flag, and an address of any one of the free areas as the storage address A ninth step of selectingThe
[0007]
  According to a third aspect of the present invention, there is provided an image processing device for generating arbitrary display image data, an image memory for storing the generated display image data, and a desired one from the stored display image data. Output data for reading out area data as display screen data, and the image memory sequentially stores data of a plurality of input systems, and stores the data stored in the data storage means. Based on the storage order of the data for each system managed by the storage order management means in response to the output request of the data for each system, the storage order management means for managing the storage order for each system Output means for reading out and outputting the stored data of the requested system in the order of the input, and the storage order management means is not stored in the data storage means. Storage address generation means for generating an arbitrary address in an empty area other than an area where unread data is stored as a storage address for storing input data, and the last input for each system. Address storage means for storing the storage address for stored data, and an address space corresponding to the address space of the data storage means, each address data being stored at a corresponding address of the data storage means A table for storing the address of the data storage means in which the data inputted and stored next to the data of the address is stored in the same system as the existing data, and an arbitrary system to be input When the data is stored at the generated storage address of the data storage means. Table updating means for storing the generated storage address at the address stored in the address storage means, and the storage address generation means is still in the address for each address of the data storage means Flag storage means for storing a flag indicating whether or not unread data is stored, and detecting the free area of the data storage means based on the stored flag, A storage address selection unit that selects an address of any one area as the storage address, and a flag update that updates the flag based on storage of newly input data and reading of the stored data by the output unit And the data storage means adds the input to the address generated by the storage address generation means. Stores any system data that is input.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
  An embodiment of the present invention will be described with reference to FIGS.
  In the present embodiment, a three-dimensional computer graphics system that is applied to a home game machine or the like and displays a desired three-dimensional image of an arbitrary three-dimensional object model on a display at high speed is exemplified. explain.
[0014]
  First, the overall configuration and operation of the three-dimensional computer graphics system will be described with reference to FIG.
  This three-dimensional computer graphics system expresses a three-dimensional model as a united figure of triangles (polygons), draws this polygon, determines the color of each pixel on the display screen, and displays the polygon on the display This is a system that performs rendering processing.
  In the three-dimensional computer graphics system 1, in addition to (x, y) coordinates representing a plane, a three-dimensional object is represented using a z coordinate representing depth, and the three coordinates x, y, z To specify an arbitrary point in the three-dimensional space.
[0015]
  FIG. 1 is a block diagram showing the configuration of the three-dimensional computer graphics system 1.
  The three-dimensional computer graphics system 1 includes an input unit 2, a three-dimensional image generation device 3, and a display device 4.
  The three-dimensional image generation apparatus 3 includes a geometry calculation unit 32, a parameter calculation unit 33, a pixel generation unit 34, a texture mapping unit 35, a texture memory 36, a memory interface (I / F) 37, an image memory 38, and a programmable display. A control unit 39 is included.
[0016]
  First, the configuration and function of each unit will be described.
  The input unit 2 inputs data of a stereoscopic model to be displayed to the three-dimensional image generation device 3. In the present embodiment, since the three-dimensional computer graphics system 1 is applied to a consumer game machine, the input unit 2 is connected to a main controller or the like that controls the game itself of the consumer game machine. . In the main control device, a screen to be displayed is determined based on the progress of the game, etc., a three-dimensional model necessary for the screen display is selected, and information on the display method is generated. Accordingly, the input unit 2 receives these pieces of information from the main control device of the consumer game machine and converts them into a form suitable for input to the three-dimensional image generation device 3. To do.
  Specifically, the input unit 2 inputs the polygon data of the stereoscopic model to be displayed as described above to the geometry calculation unit 32 of the three-dimensional image generation device 3. The input polygon data is x, y, z coordinate data of each vertex and accompanying data such as color, transparency, texture, and the like.
[0017]
  The geometry calculation unit 32 arranges the polygon input from the input unit 2 at a desired position in the three-dimensional space and generates polygon data at that position. Specifically, for each vertex (x, y, z) of the polygon, geometric conversion processing (also referred to as geometry conversion processing) such as translation conversion, parallel conversion, and rotation conversion is performed. The polygon data subjected to the geometry conversion process is output to the parameter calculation unit 33.
[0018]
  The parameter calculation unit 33 obtains parameters necessary for generating pixel data inside the polygon in the pixel generation unit 34 based on the polygon data input from the geometry calculation unit 32, that is, the data of each vertex of the polygon. , Output to the pixel generator 34. Specifically, for example, information on color, depth, and texture inclination is obtained.
[0019]
The pixel generation unit 34 linearly interpolates between the vertices of the polygon based on the polygon data subjected to the geometry conversion processing by the geometry calculation unit 32 and the parameters obtained by the parameter calculation unit 33, and the inside of the polygon and the edge Partial pixel data is generated. The pixel generation circuit 34 generates an address on a predetermined two-dimensional plane corresponding to the display of the pixel data. The generated pixel data and address are sequentially output to the texture mapping unit 35.
[0020]
The texture mapping unit 35 performs texture mapping processing on the pixel data generated by the pixel generation unit 34 using the texture data stored in the texture memory 36. The pixel data and address subjected to the texture mapping process are output to the memory interface 37.
[0021]
The texture memory 36 is a memory for storing a texture pattern used when texture mapping is performed by the texture mapping unit 35.
[0022]
The memory interface 37 generates new pixel data based on the pixel data and address input from the texture mapping unit 35 and the corresponding pixel data already stored in the image memory 38 and stores the new pixel data in the image memory 38. To do. That is, the memory interface 37 reads out pixel data corresponding to the address input from the texture mapping unit 35 from the image memory 38, and uses the pixel data and the pixel data input from the texture mapping unit 35 to perform a desired process. Pixel calculation processing is performed, and the obtained pixel data is written into the image memory 38.
In addition, when a display area is designated from the programmable display control unit 39, the memory interface 37 reads out pixel data of the display area from the image memory 38 and outputs it to the programmable display control unit 39.
[0023]
The image memory 38 is a memory for recording image data for display, and has two memory buffers, a frame buffer and a Z buffer, which can be accessed simultaneously. The frame buffer stores frame data that is color information of each pixel. The Z buffer stores Z data that is depth information (Z value) of each pixel.
The image memory 38 will be described in detail later.
[0024]
The programmable display control unit 39 converts pixel data in the display area read from the image memory 38 via the memory interface 37 into, for example, a predetermined analog signal that can be displayed by the display device 4 and outputs the analog signal to the display device 4. The format of the output signal at this time and the conversion condition based on the format can be arbitrarily set by programming based on the signal characteristics of the display device 4 to be connected.
The programmable display controller 39 requests the memory interface 37 for pixel data in the display area to be displayed, and thereby reads out pixel data in the desired display area from the image memory 38.
[0025]
In the present embodiment, display device 4 is a television receiver having a video input terminal or the like normally used at home. An analog video signal is input from the programmable display control unit 39 of the three-dimensional image generation device 3 through a video signal input terminal, and a three-dimensional image is displayed on the screen based on the signal.
[0026]
Next, the operation of the three-dimensional computer graphics system 1 will be described.
First, when a three-dimensional image to be displayed is determined in a main control device that controls the game itself of the consumer game machine, information on a three-dimensional model necessary for screen display is input to the input unit 2. Based on this information, the input unit 2 inputs polygon data of a three-dimensional model for displaying the image to the three-dimensional image generation device 3.
Each polygon data input to the 3D image generation device 3 is first translated, converted and rotated by the geometry calculation unit 32 so that it is arranged at a desired position in the 3D space for screen display. Geometry conversion processing such as conversion is performed.
[0027]
Next, the parameter calculation unit 33 obtains parameters necessary for generating pixel data inside the polygon with respect to the polygon data subjected to the coordinate conversion, and the pixel generation unit 34 actually determines between the vertices of the polygon. Is linearly interpolated to generate pixel data inside and at the edge of the polygon.
The generated pixel data is sequentially input to the texture mapping unit 35. The texture mapping unit 35 performs texture mapping processing with reference to the texture pattern data recorded in the texture memory 36, and the generated pixel data is It is stored in the image memory 38 via the memory interface 37.
[0028]
The pixel data stored in the image memory 38 is appropriately subjected to desired processing based on other pixel data input through a similar path or arbitrary control data.
As a result, the latest image data is always stored in the image memory 38 and used for screen display. That is, a request for outputting data in a predetermined area to be displayed on the display device 4 is made from the programmable display control unit 39 to the memory interface 37, and pixel data in that area is read from the image memory 38 as appropriate. The programmable display control unit 39 converts the signal into a predetermined signal for screen display and outputs the signal to the display device 4.
Thereby, a desired image is displayed on the screen on the display device 4.
[0029]
Next, the peripheral circuit of the image memory 38 according to the present invention of the three-dimensional computer graphics system 1 will be described in detail.
In the three-dimensional computer graphics system 1, the texture mapping unit 35, the memory interface 37, and the programmable display control unit 39 are components that substantially access the image memory 38. In the following description, these processing units are regarded as one signal processing unit for the image memory 38 so that the features related to the present invention become clear.
The actual circuit may have a configuration in which each component is independent as shown in FIG. 1, or may be integrally configured using, for example, a general-purpose signal processor, as will be described later. .
[0030]
FIG. 2 is a diagram logically showing peripheral circuits of the image memory 38 (hereinafter referred to as the memory device 50). The configuration of the texture mapping unit 35 to the programmable display control unit 39 shown in FIG. It is the figure shown from another viewpoint.
As described above, the memory device 50 has a function of sequentially buffering two systems of data, for example, frame data that is color information of each pixel and Z data that is depth information (Z value) of each pixel. Shall have.
[0031]
The MTXPC 51 is a signal processing unit in which a memory interface 37, a mapping mapping unit 35, and a programmable display control unit 39 are integrated in the three-dimensional computer graphics system 1. Image data generated by the MTXPC 51 is input to the FIFO memory 100.
The FIFO memory 100 sequentially stores the image data input from the MTXPC 51 regardless of the system (type), buffers it, and outputs it to the signal processing unit 53.
[0032]
The signal processing unit 53 performs arbitrary processing on the image data read from the FIFO memory 100 and stores it in the image memory 38 again. As described above, the signal processing unit 53 performs a desired pixel calculation process using, for example, corresponding pixel data already stored in the image memory 38 and texture-mapped pixel data. The obtained pixel data is written into the image memory 38 again.
The first RAM 54 and the second RAM 55 are 2-bank FIFO memories each storing data of a specific system, and sequentially store data input from the signal processing unit 53. Although not shown, for example, in response to a read request from the MTXPC 51, the stored data is output in the stored order.
The first RAM 54 (bank A) and the second RAM 55 (bank B) are each 275 bits wide and have a total storage capacity of 16 words.
[0033]
The memory device 50 (peripheral circuit of the image memory 38) can logically show the configuration as described above. Hereinafter, the FIFO memory 100 according to the present invention will be described with reference to FIGS. To do.
As described above, the FIFO memory 100 is a memory for buffering drawing data as the image memory 38 in FIG. 1, and has a capacity of 275 bits × 16 words. Further, the FIFO memory has a latency 3 from reading to reading and a reading latency 2 corresponding to two systems of data by the shared data buffer.
[0034]
First, an outline of the configuration of the FIFO memory 100 will be described with reference to FIG.
FIG. 3 is a block diagram schematically showing the main configuration of the FIFO memory 100 suitable for showing the data flow in the FIFO memory 100.
As shown in FIG. 3, the FIFO memory 100 includes a dual port RAM (DportRAM) 120, an output register (REG) 140, a write pointer unit (Wpointer) 160, a read pointer unit (Rpointer) 180, and a full signal generation unit (FullGen). 200 and an empty signal generator (EMPTY
Gen) 220.
[0035]
The dual port RAM 120 is a memory capable of simultaneous writing and reading of 275 bits × 16 words.
The dual port RAM 120 has input data DATAin applied to the data input terminal, and stores the data sequentially based on the write control signal from the write pointer unit 160. The data stored in the dual port RAM 120 is read out in the order stored based on the read control signal from the read pointer unit 180 and is output to the output register 140.
[0036]
The output register 140 stores the data RAMout read from the dual port RAM 120 based on the read control signal output from the read pointer unit 180 and outputs the data RAMout from the FIFO memory 100.
[0037]
The write pointer unit 160 generates a storage control signal for the dual port RAM 120 based on the write enable signals WE_A and WE_B of the banks A and B input to the FIFO memory 100, and applies them to the dual port RAM 120. Controls storage of data in the dual port RAM 120.
[0038]
The read pointer unit 180 generates a read control signal for the dual port RAM 120 based on the read enable signals RE_A and RE_B of the banks A and B input to the FIFO memory 100 and applies them to the dual port RAM 120. Controls reading of data from the dual port RAM 120.
[0039]
The full signal generation unit 200 indicates that the total of data stored in the dual port RAM 120 is 16, 15, 14 or more based on various control signals and status signals in the FIFO memory 100 (not shown). The signal FULL, the pre-full signal PFULL, and the pre-pre-full signal PFULL, in other words, the pre-signal FULL indicating that the storage area of the dual port RAM 120 is full, and the pre-state indicating that one more word is full. A full signal PFULL and a pre-pre-full signal PFULL indicating a pre-full state in one word are generated, and the control unit (not shown) corresponding to the memory interface 37 of the three-dimensional computer graphics system 1 Output.
[0040]
The empty signal generation unit 220 generates a signal EMPTY indicating that there is no data stored in the dual port RAM 120, that is, an empty state, based on various control signals and status signals in the FIFO memory 100 (not shown). The data is output to a control unit (not shown) corresponding to the memory interface 37 of the three-dimensional computer graphics system 1.
A control unit (not shown) controls writing and reading of data to and from the image memory 38 (FIFO memory 100) based on these signals FULL, PFULL, PFULL, and EMPTY.
[0041]
Next, a more detailed configuration of the FIFO memory 100 will be described with reference to FIG. 4 and FIG.
FIG. 4 is a circuit diagram showing a detailed configuration of the FIFO memory 100.
The FIFO memory 100 includes a dual port RAM 120, an output register 140, and a control unit 150.
The control unit 150 includes a write enable decoder 151, a read enable decoder 152, a selector 153, a register 154, a full signal generation unit 200, an empty signal generation unit 220, and an address control unit 240.
[0042]
As described above, the dual port RAM 120 is a memory capable of simultaneous writing and reading of 275 bits × 16 words. The dual port RAM 120 stores the applied data in based on the write address wp_m input from the address control unit 240 of the control unit 150 and the write enable signal ram_we input from the write enable decoder 151. Further, based on the read address rp_m input from the selector 153 of the control unit 150 and the read enable signal ram_re input from the read enable decoder 152, data is read and output to the output register 140.
[0043]
The output register 140 temporarily stores the data read from the dual port RAM 120 based on the enable signal oreg_en input from the register 154 of the control unit 150 and outputs the data from the FIFO memory 100 as the output signal out.
[0044]
The write enable decoder 151 of the control unit 150 is such that the dual port RAM 120 input from the address control unit 240 and the write enable signals we_a and we_b for the two banks A and B input from the outside to the FIFO memory 100 are full. The write enable signal ram_we for the dual port RAM 120 and the signals ram_we_a and ram_we_b indicating the writing of data in each bank are generated based on the signal ram_full indicating
[0045]
Specifically, when the dual port RAM 120 is not full, the write enable decoder 151 activates the write enable signal ram_we for the dual port RAM 120 when one of the write enable signals we_a and we_b is input. In response to the write enable signals we_a and we_b, one of the signals ram_we_a and ram_we_b indicating data writing is activated. When the signal ram_full indicating that the dual port RAM 120 is full is active, the write enable decoder 151 does not activate any signal.
[0046]
The read enable decoder 152 is a signal indicating that the read data re_a and re_b for each of the two banks A and B inputted to the FIFO memory 100 from the outside and the storage data of each bank inputted from the address control unit 240 are empty. Based on ram_empty_a and ram_empty_b, a read enable signal ram_re for the dual port RAM 120 and signals ram_re_a and ram_re_b indicating data reading of each bank are generated and output to the dual port RAM 120 and the address control unit 240, respectively.
[0047]
Specifically, the read enable decoder 152 receives the read signals re_a and re_b for either the bank A or the bank B, and when the bank is not empty, The read enable signal ram_re is activated, and signals ram_re_a and ram_re_b indicating the reading of data in the bank are activated. When the signal ram_empty_a or ram_empty_b indicating that the bank is empty is active, the read enable decoder 151 does not activate any signal.
[0048]
The selector 153 selects one of the addresses rp_a and rp_b of the first data of each bank stored in the dual port RAM 120 and input from the address control unit 240 and applies the selected address to the dual port RAM 120. In this embodiment, when the read signal re_b of the bank B input to the FIFO memory 100 is active, the start address rp_b of the storage data of the bank B is selected, and when not, the start address rp_a of the storage data of the bank A is selected. select.
[0049]
The register 154 latches the read enable signal ram_re output from the read enable decoder 152 to the dual port RAM 120 by one clock, and uses the output register 140 as an enable signal oreg_en for storing the data output from the dual port RAM 120 as an output register. Output to 140.
[0050]
Based on a full signal full generated by an address control unit 240 described later, the full signal generation unit 200 further includes a signal PFULL indicating a state in which one more word is full, and a state in which another one word is PFULL. Each signal PFULL indicated is generated and output.
[0051]
The empty signal generation unit 220 is in a state where there is no data stored in the dual port RAM 120 based on signals empty_a and empty_b indicating that the data of each bank generated by the address control unit 240 described later is empty, that is, empty. A signal EMPTY indicating an abnormal state is generated and output.
[0052]
The address control unit 240 generates various control signals for the dual port RAM 120 and the outside as described above, and manages the order of data stored in the dual port RAM 120.
The configuration of the address control unit 240 will be described in detail with reference to FIG.
FIG. 5 is a circuit diagram showing a configuration of the address control unit 240.
The address control unit 240 includes a RAM use area flag 241, a flag update unit 242, a write address decoder 243, a bank A write address storage unit 244, a bank B write address storage unit 245, a selector 246, a next pointer 247, and a bank A read address selection. 248, bank A read address register 249, bank B read address selection unit 250, bank B read address register 251, bank A empty detection counter 252, and bank B empty detection counter 253.
[0053]
The RAM use area flag 241 stores a flag indicating whether or not data that has not yet been read is stored in each address of the dual port RAM 120, and manages the use state of the dual port RAM 120. This is a 16-bit register with 1 bit corresponding to each address.
The RAM use area flag 241 is input when a signal ram_we_a (we_a in the address control unit 240, the same applies below) or ram_we_b (we_b) indicating the writing of any bank is input from the write enable decoder 151, or the read enable decoder When signals ram_re_a (re_a) and ram_re_b (re_b) indicating reading of any bank are input from 152, the data is updated with new flag data applied from the flag update unit 242.
[0054]
When data is written to and read from the dual-port RAM 120, the flag update unit 242 reads signals ram_we_a (we_a), ram_we_b (we_b) indicating the writing of any bank and any bank. When any one of the signals ram_re_a (re_a) and ram_re_b (re_b) indicating the above is input, update data of the RAM use area flag 241 is generated and applied to the RAM use area flag 241.
[0055]
The write address decoder 243 generates an address for storing data next based on the use flag of the storage area of the dual port RAM 120 stored in the RAM use area flag 241, and generates the bank A write address storage unit 244, the bank B In addition to being output to the write address storage unit 245 and the next pointer 247, it is output from the address control unit 240 and applied to the dual port RAM 120.
When data is stored in the dual port RAM 120 with the bank A or bank B being empty, the address wp is directly selected by the bank A read address selection unit 248 or the bank B read address without using the next pointer 247. The data is input to the unit 250 and used for reading data.
[0056]
At this time, the write address decoder 243 selects a storage area in order from the larger address among the empty areas of the dual port RAM 120 and outputs the addresses.
Further, the write address decoder 243 determines whether data that has not been read yet is stored in all the storage areas of the dual port RAM 120 based on the use flag of the dual port RAM 120 stored in the RAM use area flag 241. That is, whether or not the dual port RAM 120 is full is detected, and if it is full, a full signal full is output.
[0057]
The bank A write address storage unit 244 is a register that stores the address of the dual port RAM 120 into which data is written at the end of the bank A. The bank A write address storage unit 244 stores the output address of the write address decoder 243 when the signal ram_we_a (we_a) indicating writing to the bank A becomes active.
[0058]
The bank B write address storage unit 245 is a register that stores the address of the dual port RAM 120 into which data is written at the end of the bank B. The bank B write address storage unit 245 stores an output address of the write address decoder 243 when the signal ram_we_b (we_b) indicating writing to the bank B becomes active.
[0059]
The selector 246 selects an address stored in the bank A write address storage unit 244 or the bank B write address storage unit 245 according to the bank to which data is written, and applies the selected address to the next pointer 247.
[0060]
The next pointer 247 is a register that stores the order of data for each bank. The next pointer 247 has the same 16-word address space as the dual port RAM 120, and is a register file of 4 bits for each word.
The next pointer 247 stores the address output from the write address decoder 243 as the address selected and applied by the selector 246 each time new data is written into the dual port RAM 120.
As a result, each time new data is written to the dual port RAM 120, the next pointer 247 stores the data at the address where the previous data written to the same bank as the data is stored. The stored address is stored. In other words, each address of the next pointer 247 stores data of the same bank as the data stored at the address and the address at which the next data following the data is stored.
[0061]
The bank A read address selection unit 248 sequentially selects bank A data from the 16-word data of the next pointer 247 and outputs the selected data to the bank A read address register 249. Each time bank A data is read, the bank A read address selection unit 248 is data of the address selected by itself, and the data of the next pointer 247 of the address stored in the bank A read address register 249 in the subsequent stage is read. Select in order.
[0062]
The bank A read address register 249 stores data of the next pointer 247 selected by the bank A read address selection unit 248, that is, an address ram_re_a (re_a) of data to be read next stored as data of the bank A. The stored address is output from the address control unit 240 to the read enable decoder 152.
[0063]
The bank B read address selection unit 250 sequentially selects bank B data from the 16-word data of the next pointer 247 and outputs the selected data to the bank B read address register 251. Each time bank B data is read, the bank B read address selection unit 250 is the data of the address selected by itself, and the data of the next pointer 247 of the address stored in the bank B read address register 251 at the subsequent stage is read. Select in order.
[0064]
The bank B read address register 251 is a register that stores data of the next pointer 247 selected by the bank B read address selection unit 250, that is, an address ram_re_b (re_b) of data to be read next stored as bank B data. The stored address is output from the address control unit 240 to the read enable decoder 152.
[0065]
The bank A empty detection counter 252 is a counter that counts the number of valid data in the bank A. The bank A empty detection counter 252 is incremented every time a signal ram_we_a (we_a) indicating writing to the bank A is input, and a signal indicating reading from the bank A Each time ram_re_a (re_a) is input, it is decremented. When the counter value is 0, it is assumed that no data is stored in the bank A, and the empty signal ram_empty_a (empty_a) is activated.
[0066]
The bank B empty detection counter 253 is a counter that counts the number of valid data in the bank B. The bank B empty detection counter 253 is incremented each time a signal ram_we_b (we_b) indicating writing to the bank B is input, and indicates a reading from the bank B. Each time ram_re_b (re_b) is input, it is decremented. When the counter value is 0, the empty signal ram_empty_b (empty_b) is activated assuming that no data is stored in the bank B.
[0067]
Next, the operation of the FIFO memory 100 having such a configuration will be described with reference to FIGS.
First, with reference to FIG. 4 and FIG. 5, the operation will be described in detail with a focus on the address control method in the FIFO memory 100.
[0068]
First, for example, when data of the bank A (first system) is stored, the input data DATAin is applied to the dual port RAM 120, and the write enable signal we_a of the bank A is activated.
The write enable decoder 151 of the control unit 150 of the FIFO memory 100 detects the write enable signal we_a, activates the write enable signal ram_we for the dual port RAM 120, and writes data to the bank A to the address control unit 240. The signal ram_we_a (we_a) is input.
Since the address controller 240 has already detected the address of the empty area in the write address decoder 243 and applied it to the dual port RAM 120, the dual port RAM 120 uses the write enable signal ram_we from the write enable decoder 151. Data is recorded at the address wp designated by the write address decoder 243.
[0069]
In the address control unit 240, the write address wp is stored in the bank A write address storage unit 244 based on the signal ram_we_a (we_a) for writing data to the bank A input from the write enable decoder 151.
Further, the flag update unit 242 generates new flag data in which the flag of the address wp is used for the flag stored in the RAM use area flag 241, and thereby the RAM use area flag The contents of 241 are updated.
The bank A read address selection unit 248 selects this address wp and sets it in the bank A read address register 249 as the address of the first data of the bank A.
Further, based on the updated flag data of the RAM use area flag 241, the write address decoder 243 generates an address to which data is next written and outputs it as a new address wp.
[0070]
Next, for example, assuming that data in bank B (second system) is stored, input data DATAin is applied to dual port RAM 120, and write enable signal we_b in bank B is activated. This write enable signal we_b is detected by the write enable decoder 151 of the control unit 150 and activates the write enable signal ram_we for the dual port RAM 120. As a result, the input data is written to the address ram_wp (wp) already output from the address control unit 240 and applied to the dual port RAM 120.
[0071]
Further, a signal ram_we_b (we_b) for writing data to the bank B is input from the write enable decoder 151 to the address control unit 240, whereby the write address wp is stored in the bank B write address storage unit 245.
Further, the flag update unit 242 generates new flag data in which the flag of the address wp is used for the flag stored in the RAM use area flag 241, and thereby the RAM use area flag The contents of 241 are updated.
The bank B read address selection unit 250 selects this address wp and sets it in the bank B read address register 251 as the address of the first data in the bank B.
Further, based on the updated flag data of the RAM use area flag 241, the write address decoder 243 generates an address to which data is next written and outputs it as a new address wp.
[0072]
Next, assuming that the data of the bank A is stored again, the input data DATAin is applied to the dual port RAM 120, and the write enable signal we_a of the bank A is activated. The write enable decoder 151 detects the write enable signal we_a and activates the write enable signal ram_we for the dual port RAM 120, thereby inputting the address ram_wp (wp) applied to the dual port RAM 120 from the address control unit 240. Written data is written.
[0073]
At this time, the address controller 240 uses the selector 246 to output the first bank, which is the output of the bank A write address storage unit 244, based on the signal ram_we_a (we_a) for writing data to the input bank A. The address at which the A data is recorded is selected and applied to the next pointer 247, and the current data recording address, that is, the address at which the second bank A data is recorded is stored in the first data recording address. The
Thereafter, as in the first time or when writing to the bank B, this recording address is recorded in the bank A write address storage unit 244, and the flag update unit 242 stores the contents of the flag stored in the RAM usage area flag 241. Is updated, and the write address decoder 243 generates a new write address based on the updated flag data of the RAM use area flag 241.
Note that when storing additional data from the state in which data has already been stored, the address is not written from the write address decoder 243 to the bank A read address register 249.
[0074]
Now, in the state where data is written in this way, when the reading of the data of the bank A is requested, the read enable signal re_a of the bank A is activated.
The read enable decoder 152 of the control unit 150 of the FIFO memory 100 detects the read enable signal we_a, activates the read enable signal ram_re for the dual port RAM 120, and reads the bank A data to the address control unit 240. Signal ram_re_a (re_a).
[0075]
From the address control unit 240, the stored data start address of each bank has already been output to the selector 153 via the bank A read address register 249 and the bank B read address register 251.
In the selector 153, since the read enable signal re_b of the bank B is negative, the leading address of the bank A that is the output of the bank A read address register 249 is selected and applied to the dual port RAM 120.
As a result, the first data stored in bank A is read from the dual port RAM 120 and output from the FIFO memory 100 via the output register 140.
[0076]
Further, in the address control unit 240, the bank A read address selection unit 248 receives the bank A from the next pointer 247 based on the signal ram_re_a (re_a) for reading the data of the bank A input from the read enable decoder 152. The address data read from the current data stored in the read address register 249 is selected and set in the bank A read address register 249 as the address of the next data in the bank A. As a result, the address control unit 240 outputs the storage data head address of the new bank A to the selector 153.
Further, in the address control unit 240, new flag data in which the flag of the address wp is not used is generated by the flag update unit 242 with respect to the flag stored in the RAM use area flag 241. As a result, the contents of the RAM use area flag 241 are updated.
[0077]
In this way, data reading and writing of each bank are sequentially performed thereafter.
[0078]
Finally, the overall operation of the FIFO memory 100 will be described with reference to FIG. 3 and FIG.
6A and 6B are time charts showing the overall operation of the FIFO memory 100. FIG. 6A is a diagram showing an operation clock CLK of the FIFO memory 100, and FIG. 6B is a diagram showing input data DATAin to the FIFO memory 100. ) Is a diagram showing data FIFOin applied to the dual port RAM 120, (D) is a write enable signal WE_A for the bank A, (E) is a write enable signal WE_B for the bank B, (F) is the entire empty signal EMPTY, (G) is full signal FULL, (H) is pre-full signal PFULL, (I) is pre-pre-full signal PFULL, (J) is a read enable signal for bank B, and (K) is from dual port RAM 120. Output data FIFOout.
[0079]
First, as shown in FIG. 6B, when data is sequentially input to the FIFO memory 100, the data D0 to D3 are stored in the bank A, and the data D4 to D7 are stored in the bank B, FIG. D) and write enable signals for banks A and B are activated as shown in FIG. 6E, signal processing is performed in the FIFO memory 100 as described above, and data is stored in a desired form. Is done.
Then, the empty signal becomes negative when the data D0 is stored as shown in FIG. 6 (F), and pre-pre-play is performed when the six data up to the data D5 are stored as shown in FIG. 6 (I). The full signal PFULL becomes active, and the pre-full signal PFULL becomes active at the stage where seven data up to the data D6 are stored as shown in FIG. 6 (H), and further, as shown in FIG. 6 (G). In this way, the full signal FULL becomes active at the stage where eight data up to the data D7 are stored.
[0080]
In this state, as shown in FIG. 6 (J), by activating the read enable signal for bank B, as shown in FIG. 6 (K), data in bank B below data D4 is transferred. Read sequentially. F
As the data is read out, the full signal FULL shown in FIG. 6G, the pre-full signal PFUL shown in FIG. 6H, and the pre-pre-full signal PFULL shown in FIG. 6I become negative. To go.
The FIFO memory 100 operates in this way.
[0081]
As described above, in the FIFO memory 100 of the present embodiment, two systems of FIFOs can be realized by using one dual port RAM 120. As a result, the FIFO margin can be reduced as a whole, and a part of the control circuit can be shared as compared with the case where two completely independent FIFOs are provided. As a result, the circuit scale is greatly increased. Can be reduced.
Further, the storage capacity allocation in the two systems may be determined dynamically based on the input data, and is not fixed in advance. Therefore, as a whole, a more flexible buffer can be configured.
[0082]
Then, by applying the FIFO memory 100 having such a configuration to, for example, the three-dimensional image generating apparatus 3 of the three-dimensional computer graphics system 1 as described above, each component unit that performs complex and high-speed processing is used. The data can be transferred efficiently with a small scale circuit, and as a result, a desired image can be generated efficiently.
[0083]
The present invention is not limited to the embodiment described above, and various modifications can be made.
For example, in the present embodiment, a FIFO that processes two types (two systems) of data is illustrated, but this is not limited to two systems, and any number of systems may be processed.
[0084]
The memory for actually storing data is not limited to the dual port RAM, and a single port RAM may be used. In that case, for example, two single-port RAMs are provided, and storage and reading of data cannot be performed simultaneously by controlling storage and reading of data so that storage and reading of one single-port RAM are not performed simultaneously. A FIFO memory that operates in the same manner as the present invention can be configured using a single-port RAM and without increasing the operating clock.
Of course, any memory other than the single port RAM may be used as the type of memory.
[0085]
In the present embodiment, the three-dimensional image generation apparatus is illustrated as an application example of the FIFO memory 100 memory 100. However, this FIFO memory apparatus can be applied to any suitable apparatus as a normal FIFO memory.
[0086]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a data storage apparatus and method that can appropriately provide a FIFO function for data of a plurality of systems with a smaller circuit scale.
In addition, it is possible to provide an image processing apparatus capable of appropriately transferring data in each processing means with a smaller circuit scale, and thereby performing desired image processing efficiently.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a three-dimensional computer graphics system to which a memory device of the present invention is applied according to an embodiment of the present invention.
2 is a diagram logically showing a configuration of a memory device including an image memory and its peripheral circuits of the three-dimensional computer graphics system shown in FIG. 1. FIG.
FIG. 3 is a block diagram schematically showing a configuration of a FIFO memory of a memory device suitable for showing a data flow in the memory device shown in FIG. 2;
FIG. 4 is a circuit diagram showing a detailed configuration of the FIFO memory shown in FIG. 3;
FIG. 5 is a circuit diagram showing a configuration of an address control unit of the FIFO memory shown in FIG. 4;
FIG. 6 is a time chart showing the overall operation of the FIFO memory shown in FIG. 3;
FIG. 7 is a diagram logically showing a configuration of a memory device including an image memory and its peripheral circuit in a conventional three-dimensional computer graphics system.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Three-dimensional computer graphics system, 2 ... Input part, 3 ... Three-dimensional image generation apparatus, 4 ... Display apparatus, 32 ... Geometry calculation part, 33 ... Parameter calculation part, 34 ... Pixel generation part, 35 ... Texture mapping part 36 ... Texture memory, 37 ... Memory interface, 38 ... Image memory, 39 ... Programmable display control unit, 50 ... Memory device, 51 ... MTXPC, 53 ... Signal processing unit, 54 ... First RAM, 55 ... Second RAM, 100 ... FIFO memory, 120 ... Dual port RAM, 140 ... Output register, 150 ... Control unit, 151 ... Write enable decoder, 152 ... Read enable decoder, 153 ... Selector, 154 ... Register, 160 ... Write pointer unit, 180 ... Read pointer part, 200 ... Full signal generation , 220 ... Empty signal generation unit, 240 ... Address control unit, 241 ... RAM use area flag, 242 ... Flag update unit, 243 ... Write address decoder, 244 ... Bank A write address storage unit, 245 ... Bank B write address storage , 246 ... selector, 247 ... next pointer, 248 ... bank A read address selection section, 249 ... bank A read address register, 250 ... bank B read address selection section, 251 ... bank B read address register, 252 ... bank A Empty detection counter, 253 ... Bank B empty detection counter

Claims (8)

Data storage means for sequentially storing input data of a plurality of systems;
Storage order management means for managing the storage order of the data stored in the data storage means for each of the systems;
In response to a data output request for each system, the stored data of the requested system is input based on the storage order of the data for each system managed by the storage order management means. Output means for reading out and outputting in the order of
The storage order management means includes
A storage address generating means for generating an arbitrary address of an empty area other than an area where data that has not yet been read from the data storage means is stored as a storage address for storing input data;
For each of the systems, address storage means for storing the storage address for the last input and stored data;
It has an address space corresponding to the address space of the data storage means, and the input data of the same system as the data stored in the corresponding address of the data storage means as the data of each address, the address and lutein Buru to store an address of the data memory means the data stored is input to the next is stored data,
When the data of an arbitrary system to be inputted is stored in the generated storage address of the data storage means, the generated storage address is stored in the address stored in the address storage means of the table. Table updating means to
Have
The storage address generating means
Flag storage means for storing a flag indicating whether or not data that has not yet been read is stored in the address for each address of the data storage means;
Storage address selection means for detecting the free area of the data storage means based on the stored flag and selecting the address of any one of the free areas as the storage address;
Flag update means for updating the flag based on storage of newly input data and reading of stored data by the output means;
The data storage means stores data of an arbitrary system to be inputted at an address generated by the storage address generation means. The output means includes
Read address storage means for storing, as a read address, the storage address stored in the table of the address at which data was last read from the data storage means for each of the systems,
Data read means for reading out and outputting the data of the read address of the system stored in the read address storage means of the data storage means when there is an output request of data of the arbitrary system,
The data storage device according to claim 1, comprising: The data storage device according to claim 1, wherein the data storage unit, the storage order management unit, and the output unit are configured as a semiconductor integrated circuit. The data storage device according to claim 3, wherein the data storage unit includes a dual port memory capable of storing and reading data during the same cycle. A data storage method of a data storage device having data storage means, storage order management means, and output means,
A first step of storing input data of a plurality of systems in a memory;
A second step of managing the storage order of the stored data for each of the systems;
In response to a data output request for each system, the stored data of the requested system is read and output in the input order based on the managed data storage order for each system. A third step;
Have
The second step includes
For each of the systems, a fourth step of storing the storage address for the last input and stored data;
When data of an arbitrary system is input, an arbitrary address in an empty area other than an area in which data that has not yet been read is stored is generated as a storage address for storing input data. A fifth step;
It has an address space corresponding to the address space of the data storage means, and the input data of the same system as the data stored in the corresponding address of the data storage means as the data of each address, the address data stored is input to the following table for storing an address of said data storage means having stored therein the data, the last entered stored address for the stored data of the lines being the storage, the A sixth step of storing the generated storage address when input data is stored in the generated storage address of the memory;
Have
The fourth step includes
A seventh step of setting a flag indicating whether data not yet read is stored in each address of the memory;
An eighth step of detecting the free area of the memory based on the stored flag;
A ninth step of selecting an address of any one of the empty areas as the storage address;
A data storage method comprising: Image generating means for generating arbitrary display image data;
An image memory for storing the generated display image data;
Output means for reading out data of a desired area from the stored display image data and outputting it as display screen data;
The image memory is
Data storage means for sequentially storing input data of a plurality of systems;
Storage order management means for managing the storage order of the data stored in the data storage means for each of the systems;
In response to a data output request for each system, the stored data of the requested system is input based on the storage order of the data for each system managed by the storage order management means. Output means for reading out and outputting in the order of
The storage order management means includes
A storage address generating means for generating an arbitrary address of an empty area other than an area where data that has not yet been read from the data storage means is stored as a storage address for storing input data;
For each of the systems, address storage means for storing the storage address for the last input and stored data;
It has an address space corresponding to the address space of the data storage means, and the input data of the same system as the data stored in the corresponding address of the data storage means as the data of each address, the address and lutein Buru to store an address of the data memory means the data stored is input to the next is stored data,
When the data of an arbitrary system to be inputted is stored in the generated storage address of the data storage means, the generated storage address is stored in the address stored in the address storage means of the table. Table updating means to
Have
The storage address generating means
Flag storage means for storing a flag indicating whether or not data that has not yet been read is stored in the address for each address of the data storage means;
Storage address selection means for detecting the free area of the data storage means based on the stored flag and selecting the address of any one of the free areas as the storage address;
Flag update means for updating the flag based on storage of newly input data and reading of stored data by the output means;
The image processing apparatus, wherein the data storage unit stores the input data of an arbitrary system at the address generated by the storage address generation unit. The image generating means includes
Arbitrary three-dimensional solid model performs predetermined coordinate transformation on the vertexes of the basic polygons of the three-dimensional image data shown as a set of basic polygons indicated by the vertices having at least three-dimensional position information. Coordinate transformation means to perform,
Pixel data generating means for generating pixel data of the basic polygon based on the data of the vertices of the basic polygon;
The image processing according to claim 6, further comprising: a texture mapping unit that texture-maps the generated pixel data using a desired texture pattern and generates display three-dimensional image data as the display image data. apparatus. The output means includes
Read address storage means for storing, as a read address, the storage address stored in the table of the address at which data was last read from the data storage means for each of the systems,
Data read means for reading out and outputting the data of the read address of the system stored in the read address storage means of the data storage means when there is an output request of data of the arbitrary system,
The image processing apparatus according to claim 7.

Images