JP2001209811A - Device and method for storing data and image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for storing data, with which a FIFO function can be suitably provided for the data of plural systems in small circuit scale. SOLUTION: When data are written in a bank A, for example, in an address control part 240, an address at the time of recording the data of the last bank A outputted from a bank A write address storage part 244 is selected by a selector 246, this address is impressed to a next pointer 247, and the data recording address of this time is stored in the data recording address of the last time as data. Since the link of data streams of plural systems is managed by the next pointer 247, even when the inputted data of any arbitrary system are written in any address, each of systems is distinguished and data can be read in the order of input for each of systems.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out (FIFO) format for a plurality of data streams.
First Out) format. A) a data storage device and a data storage method, and an image processing device capable of efficiently generating a display image using the data storage device.

[0002]

2. Description of the Related Art A so-called FIFO memory for reading input data in the order of input is widely used in various electronic circuits. In particular, in recent years, the processing speed has been improved in all electronic devices, and as a result, the processing speed of data between the processing units may differ, or it may be difficult to transfer data in an appropriate synchronization. In order to solve this problem, a FIFO memory is frequently provided as a buffer between the processing units. For example, an image processing device that generates a three-dimensional image used for a CAD device, a game device, or the like, performs coordinate conversion, texture mapping, special effect processing for each pixel, and high-speed display of a generated image. Various processing units that perform high-speed processing are sequentially connected. A large number of FIFO memories are used to perform high-speed and appropriate data transfer between these processing units.

[0003]

By the way, for example, a plurality of types of data are often transferred between components of such an image processing apparatus as needed. In particular, if not only image data but also control data is included, it is rare that only one specific type of data is transferred. In such a case, up to now, as shown in FIG. 7, for example, as shown in FIG.
Memory was provided in parallel. However, when a plurality of FIFO memories are provided in parallel in such a manner, a margin must be secured for each system, and a control unit is provided independently despite a large amount of common signal processing. For example, there is a problem that the circuit cannot be used efficiently, that is, the circuit scale becomes larger than necessary. In particular, since such a circuit is often realized as a semiconductor integrated circuit, there is a demand that the circuit scale, in other words, the gate scale of the circuit be reduced as much as possible.

Accordingly, it is an object of the present invention to provide a data storage device and a method thereof capable of appropriately providing a FIFO function to data of a plurality of systems with a smaller circuit scale. It is another object of the present invention to provide an image processing apparatus capable of appropriately performing data transfer in each processing means with a smaller circuit scale and thereby efficiently performing desired image processing.

[0005]

In order to solve the above-mentioned problems, a data storage device according to the present invention comprises a data storage means for sequentially storing a plurality of input data, and a data storage means for storing the data stored in the storage means. A storage order management unit that manages a storage order for each system, and a storage order of the data for each system managed by the storage order management unit in response to a data output request for each system. Output means for reading and outputting the stored data of the requested system in the order of input.

Preferably, the storage order management means has an address space corresponding to an address space of the data storage means, and stores, as data of each address, data stored at a corresponding address of the data storage means. In the input data of the same system as the above, the storage order of the data stored in the storage means is determined by a table storing an address in which the data input and stored next to the data of the address is stored. Manage for each system.

More specifically, the storage order management means stores an arbitrary address of a free area other than an area of the data storage means in which data that has not been read yet is stored.
Storage address generation means for generating a storage address for storing input data; address storage means for storing the storage address for the last input and stored data for each system; and address of the data storage means. Data having the same address space as the data stored at the corresponding address in the data storage means, and having the address space corresponding to the address. The table that stores the address of the data storage unit where the stored data is stored, and when the input arbitrary data of the system is stored in the generated storage address of the data storage unit, The generated storage address is replaced with the address stored in the address storage means of the table. And a table updating means for 憶,
The data storage unit stores the input arbitrary data at the address generated by the storage address generation unit.

[0008] More specifically, the storage address generating means stores a flag indicating whether or not data which has not been read yet is stored at each address of the data storage means. Means for detecting the free area of the data storage means based on the stored flag, and selecting an address of any one of the free areas as the storage address; And a flag updating unit for updating the flag based on the storage of the data input to the CPU and the reading of the stored data by the output unit.

Specifically, the output means stores, for each of the systems, the storage address stored in the table of the address from which the data was last read from the data storage means, as a read address. Read address storage means, and data reading for reading and outputting the data of the read address of the system stored in the read address storage means of the data storage means when there is an output request of data of any of the systems. Means.

More specifically, the data storage means, the storage order management means and the output means are configured as a semiconductor integrated circuit. More specifically, the data storage means has a dual port memory capable of storing and reading data during the same cycle.

Further, in the data storage method of the present invention, data of a plurality of input systems is stored in a memory, a storage order of the stored data is managed for each of the systems, and a data output request for each system is controlled. And reads and outputs the stored data of the requested system in the input order based on the storage order of the managed data for each system. Preferably, the input data has an address space corresponding to the address space of the memory for storing the data, and as the data of each address, the input data of the same system as the data stored at the address of the memory. Then, the storage order of the stored data is managed for each system by a table that stores the address on the memory of the data input next to the data of the address and stored in the memory.

Further, the image processing apparatus according to the present invention comprises: an image generating means for generating arbitrary display image data; an image memory for storing the generated display image data; and the stored display image data. Output means for reading out data of a more desired area and outputting the data as screen data for display, wherein the image memory is a data storage means for sequentially storing a plurality of input systems of data; A storage order management unit that manages a storage order of data for each of the systems, and a storage order of data for each of the systems managed by the storage order management unit in response to a data output request for each of the systems. And output means for reading and outputting the stored data of the requested system in the order of input.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. In the present embodiment, a three-dimensional computer graphics system which is applied to a home game machine or the like and displays a desired three-dimensional image of an arbitrary three-dimensional object model on a display at a high speed is exemplified. explain.

First, the overall configuration and operation of the three-dimensional computer graphics system will be described with reference to FIG. In this three-dimensional computer graphics system, a three-dimensional model is expressed as a combination of triangles (polygons), which are unit figures, and the polygons are drawn to determine the color of each pixel on a display screen and display the polygons on a display. This is a system that performs rendering processing. In addition, in the three-dimensional computer graphics system 1, a three-dimensional object is represented using z coordinates representing depth in addition to (x, y) coordinates representing a plane, and three coordinates of x, y, and z are used. Specifies an arbitrary point in the three-dimensional space.

FIG. 1 is a block diagram showing the configuration of the three-dimensional computer graphics system 1. The three-dimensional computer graphics system 1 includes an input unit 2, a three-dimensional image generation device 3, and a display device 4.
Further, the three-dimensional image generation device 3 includes a geometry calculation unit 3
2, a parameter calculation unit 33, a pixel generation unit 34, a texture mapping unit 35, a texture memory 36, a memory interface (I / F) 37, an image memory 38, and a programmable display control unit 39.

First, the configuration and function of each unit will be described. The input unit 2 inputs data of a three-dimensional model to be displayed to the three-dimensional image generation device 3. In this embodiment, since the three-dimensional computer graphics system 1 is applied to a home game machine, the input unit 2
Is connected to a main controller for controlling the game itself of the home game machine. The main controller determines the screen to be displayed based on the progress of the game, etc.
A three-dimensional model required for the screen display is selected, and information on the display method is generated. Therefore, the input unit 2 receives the information from the main control device of the consumer game machine,
The image is converted into a form suitable for input to the three-dimensional image generation device 3 and input to the three-dimensional image generation device 3. Specifically, the input unit 2 inputs the polygon data of the three-dimensional model to be displayed as described above to the geometry calculation unit 32 of the three-dimensional image generation device 3. The input polygon data is x, y, z coordinate data of each vertex and accompanying data such as color, transparency, and texture.

The geometry calculation unit 32 arranges the polygon input from the input unit 2 at a desired position in the three-dimensional space and generates polygon data at that position. Specifically, for each vertex (x, y, z) of the polygon, a geometric transformation process (also referred to as a geometry transformation process) such as a translation transformation, a parallel transformation, and a rotation transformation is performed. The polygon data subjected to the geometry conversion processing is output to the parameter calculation unit 33.

The parameter calculation unit 33 is required for the pixel generation unit 34 to generate pixel data inside the polygon based on the data of the polygon input from the geometry calculation unit 32, that is, the data of each vertex of the polygon. The parameters are obtained and output to the pixel generator 34. Specifically, for example, information on color, depth, and texture inclination is obtained.

The pixel generating section 34 includes a geometry calculating section 32
Based on the polygon data subjected to the geometry conversion processing in step (1) and the parameters calculated by the parameter calculation unit 33, linear interpolation is performed between the vertices of the polygon to generate pixel data of the inside and the edge of the polygon. In addition, the pixel generation circuit 34 has a predetermined 2 corresponding to the display of pixel data.
Generate addresses on a dimensional plane. The generated pixel data and address are sequentially transferred to the texture mapping unit 3.
5 is output.

The texture mapping unit 35 uses the texture data stored in the texture memory 36 for the pixel data generated by the pixel generation unit 34,
Perform texture mapping processing. The pixel data and the address subjected to the texture mapping process are output to the memory interface 37.

The texture memory 36 is a memory for storing texture patterns used when texture mapping is performed by the texture mapping unit 35.

The memory interface 37 generates new pixel data based on the pixel data and address input from the texture mapping unit 35 and the corresponding pixel data already stored in the image memory 38, 38. That is, the memory interface 37 reads pixel data corresponding to the address input from the texture mapping unit 35 from the image memory 38, and uses the pixel data and the pixel data input from the texture mapping unit 35,
A desired pixel calculation process is performed, and the obtained pixel data is written to the image memory 38. Also memory interface 3
When the display area is designated by the programmable display control section 39, the pixel data of the display area is read out from the image memory 38,
Output to the display controller 39.

The image memory 38 is a memory for recording image data for display, and has two memory buffers, a frame buffer and a Z buffer, which can be accessed simultaneously. Frame data, which is color information of each pixel, is stored in the frame buffer. The Z buffer stores Z data as depth information (Z value) of each pixel. The image memory 38 will be described later in detail.

Programmable display control unit 39
Is the image memory 3 via the memory interface 37.
The pixel data of the display area read from
For example, the signal is converted into a predetermined analog signal that can be displayed, and output to the display device 4. At this time, the format of the output signal and the conversion condition based on the format can be arbitrarily set by programming based on the signal characteristics of the display device 4 to be connected. The programmable display control unit 39 requests the memory interface 37 for pixel data of a display area to be displayed, and
Thereby, pixel data of a desired display area is read from the image memory 38.

In the present embodiment, the display device 4 is
This is a television receiver having a video input terminal and the like generally used in homes and the like. 3D image generation device 3
An analog video signal is input from the programmable display control unit 39 via a video signal input terminal, and a three-dimensional image is displayed on a screen based on the signal.

Next, the operation of the three-dimensional computer graphics system 1 will be described. First, when a three-dimensional image to be displayed is determined in a main control device or the like that controls the game itself of the home-use game machine, information on a three-dimensional model required for screen display is input to the input unit 2. Based on this information, the input unit 2 converts the polygon data of the three-dimensional model for displaying the image into a three-dimensional image generating device 3.
To enter. Each polygon data input to the three-dimensional image generation device 3 is first processed by the geometry calculation unit 32.
Geometry transformation processing such as translation, parallel transformation, and rotation transformation is performed so as to be arranged at a desired position in a three-dimensional space for screen display.

Next, for the polygon data subjected to the coordinate conversion, parameters necessary for generating pixel data inside the polygon are obtained in the parameter calculation unit 33, and the pixel generation unit 34 actually calculates the polygon data. Pixel data of the inside of the polygon and the edge portion is generated by linearly interpolating between the vertices. The generated pixel data is sequentially input to the texture mapping unit 35, and the texture mapping unit 35 performs texture mapping with reference to the texture pattern data recorded in the texture memory 36, and generates the pixel data. It is stored in the image memory 38 via the memory interface 37.

The pixel data stored in the image memory 38 is subjected to a desired process as needed based on other pixel data input through a similar route or arbitrary control data. As a result, the latest image data is always stored in the image memory 38 and used for screen display. That is, a request to output data in a predetermined area for display on the display device 4 is made from the programmable display control unit 39 to the memory interface 37, and pixel data in that area is read out from the image memory 38 as appropriate. Is converted into a predetermined signal for screen display by the programmable display control unit 39 and output to the display device 4. Thereby, a desired image is displayed on the screen of the display device 4.

Next, the image memory 3 of the three-dimensional computer graphics system 1 according to the present invention will be described.
8 will be described in detail. In the three-dimensional computer graphics system 1, the texture mapping unit 35, the memory interface 37, and the programmable display control unit 39 are components that substantially access the image memory 38. In the following description, these processing units will be described as one signal processing unit for the image memory 38 so as to clarify the features of the present invention. In addition,
The actual circuit may have a configuration in which each component is independent as shown in FIG. 1, or may be an integrated configuration using a general-purpose signal processor, for example, as described later.

FIG. 2 is a diagram logically showing a peripheral circuit of the image memory 38 (hereinafter, this is referred to as a memory device 50). The texture mapping unit 3 shown in FIG.
5 is a diagram illustrating a configuration of a programmable display control unit 39 from another viewpoint. FIG. As described above, the memory device 50 includes, for example, frame data that is color information of each pixel and depth information (Z
It has a function of sequentially buffering data of two systems of the Z data of (value).

The MTXPC 51 is a memory interface (Memory Interface) 37, a mapping (Temple Mapping) unit 35 and a programmable display control unit (Program) in the three-dimensional computer graphics system 1.
The CRT controller 39 is an integrated signal processing unit. The image data generated by the MTXPC 51 is input to the FIFO memory 100. The FIFO memory 100 sequentially stores the image data input from the MTXPC 51 irrespective of the system (type), buffers the image data, and outputs the buffered data to the signal processing unit 53.

The signal processing unit 53 includes a FIFO memory 100
An arbitrary process is performed on the read image data, and the image data is stored in the image memory 38 again. As described above, the signal processing unit 53 performs a desired pixel calculation process using, for example, corresponding pixel data already stored in the image memory 38 and texture-mapped pixel data. Then, the obtained pixel data is written into the image memory 38 again. First RAM 54 and second RAM 55
Are two banks of FIs each storing data of a specific system.
The FO memory sequentially stores data input from the signal processing unit 53. Although not shown, for example, in response to a read request from the MTXPC 51, the stored data is output in the order of storage. The first RAM 5
4 (bank A) and second RAM 55 (bank B)
Have a storage capacity of 16 words in total, each having a width of 275 bits.

The memory device 50 (peripheral circuit of the image memory 38) can logically show the configuration as described above. Hereinafter, the FIFO memory 100 according to the present invention will be described with reference to FIGS. I will explain. As described above, the FIFO memory 100 is a memory for buffering drawing data as the image memory 38 in FIG. 1, and has a capacity of 275 bits × 16 words. In addition, the FIFO memory has a latency of 3 from write to read and a read latency of 2 corresponding to two systems of data by the shared data buffer.

First, an outline of the configuration of the FIFO memory 100 will be described with reference to FIG. FIG. 3 shows a FIFO memory 100 suitable for showing a data flow in the FIFO memory 100.
FIG. 2 is a block diagram schematically showing a main configuration of FIG. As shown in FIG. 3, the FIFO memory 100 includes a dual port RAM (DportRAM) 120 and an output register (R
EG) 140, write pointer unit (Wpointer)
160, read pointer section (Rpointer) 18
0, a full signal generator (FullGen) 200 and an empty signal generator (EMPTYGen) 220.

The dual-port RAM 120 is a 275-bit × 16-word memory capable of simultaneously writing and reading. Dual port RAM 120
The input data DATAin is applied to the data input terminal, and is sequentially stored based on a write control signal from the write pointer unit 160. The data stored in the dual port RAM 120 is read out in the order in which the data is stored based on the read control signal from the read pointer unit 180, and is output to the output register 140.

The output register 140 stores the data RAMo read from the dual port RAM 120 based on the read control signal output from the read pointer section 180.
ut is stored and output from the FIFO memory 100.

The write pointer section 160 is based on the write enable signals WE_A and WE_B of the banks A and B input to the FIFO memory 100, respectively.
By generating a storage control signal for the dual port RAM 120 and applying it to the dual port RAM 120, the storage of data in the dual port RAM 120 is controlled.

The read pointer section 180 is based on the read enable signals RE_A and RE_B of the banks A and B input to the FIFO memory 100, respectively.
By generating a read control signal for the dual port RAM 120 and applying the signal to the dual port RAM 120, data read from the dual port RAM 120 is controlled.

The full signal generation unit 200 is provided with an unshown FIF
Based on various control and status signals in the O-memory 100, a full signal FULL, a pre-full signal PFULL, and a full signal FULL indicating that the total of the data stored in the dual port RAM 120 is 16, 15, 14 or more, respectively. , A pre-full signal PFULL, in other words, a pre-signal FULL indicating that the storage area of the dual port RAM 120 is full, a pre-full signal PFULL indicating that one more word is full, and one more.
It generates a pre-full signal PFULL indicating a word-full state and outputs it to a control unit (not shown) corresponding to the memory interface 37 of the three-dimensional computer graphics system 1.

The empty signal generator 220 generates a signal EMPTY indicating no data stored in the dual port RAM 120, that is, an empty state, based on various control signals and status signals in the FIFO memory 100 (not shown). It is generated and output to a control unit (not shown) corresponding to the memory interface 37 of the three-dimensional computer graphics system 1. The control unit (not shown) controls these signals FULL, PFULL, PPFULL and E
Based on the MPTY, writing and reading of data to and from the image memory 38 (FIFO memory 100) are controlled.

Next, a more detailed configuration of the FIFO memory 100 will be described with reference to FIGS. FIG. 4 is a circuit diagram showing a detailed configuration of the FIFO memory 100. The FIFO memory 100 has a dual port RA
M120, output register 140 and control unit 150. The control unit 150 includes a write enable decoder 151, a read enable decoder 152, a selector 153, a register 154, a full signal generation unit 200, an empty signal generation unit 220, and an address control unit 240.

The dual port RAM 120 is a 275-bit × 16-word memory that can be written and read simultaneously, as described above. The dual port RAM 120 has an address control unit 240 of the control unit 150.
Data i based on a write address wp_m input from the write enable signal ram_we input from the write enable decoder 151.
n is stored. Further, based on the read address rp_m input from the selector 153 of the control unit 150 and the read enable signal ram_re input from the read enable decoder 152, data is output to the read output register 140.

The output register 140 receives the enable signal oreg_ input from the register 154 of the control unit 150.
en, the data read from the dual port RAM 120 is temporarily stored, and as an output signal out, F
Output from the IFO memory 100.

The write enable decoder 151 of the control unit 150 has a full write enable signal we_a, we_b for each of the two banks A and B externally input to the FIFO memory 100 and a dual port RAM 120 input from the address control unit 240. Based on the signal ram_full indicating that the write enable signal ram_
we and signals ram_we_a and ram_we_b indicating the writing of data in each bank, respectively.
Dual-port RAM 120 address control unit 240
Output to

Specifically, the write enable decoder 1
Reference numeral 51 denotes a state where the dual port RAM 120 is not full, and if any of the write enable signals we_a and we_b is input, the dual port RAM 120
Is activated. Also, the write enable signals we_a, we
Ram_w indicating a data write in accordance with _b
Either e_a or ram_we_b is activated. When the signal ram_full indicating that the dual port RAM 120 is full is active, the write enable decoder 151 does not activate any signal.

The read enable decoder 152 requires that the read signals re_a and re_b for the two banks A and B externally input to the FIFO memory 100 and the storage data of each bank input from the address control unit 240 be empty. Signal ram_em indicating
Based on pty_a and ram_empty_b, a read enable signal ram_re for the dual port RAM 120 and signals ram_re_a and ram_re_b indicating data read of each bank are generated and output to the dual port RAM 120 and the address control unit 240, respectively.

More specifically, the read enable decoder 1
Reference numeral 52 denotes a case where one of the read signals re_a and re_b for either the bank A or the bank B is input, and when the bank is not empty,
A read enable signal ram_re for the dual port RAM 120 is activated, and signals ram_re_a and ram_r indicating that data is read from the bank.
Activate e_b. A signal ram_empty_a or ra indicating that the bank is empty
When m_empty_b is active, the read enable decoder 151 does not activate any signal.

The selector 153 includes an address control unit 240
Rp_a, r of the first data of each bank stored in the dual port RAM 120
p_b, and select the dual port RAM1
20. In the present embodiment, the read signal re_b of the bank B input to the FIFO memory 100
Is active, selects the start address rp_b of the storage data of the bank B, and otherwise selects the start address rp_a of the storage data of the bank A.

The register 154 latches the read enable signal ram_re output from the read enable decoder 152 to the dual port RAM 120 for one clock, and stores the data output from the dual port RAM 120 as an enable signal oreg_en for the output register 140 to store. , To the output register 140.

Based on a full signal full generated by an address control unit 240, which will be described later, the full signal generation unit 200 further generates a signal PFULL indicating that the state becomes full in one more word, and a PFULL in another word.
Respectively, and generates and outputs a signal PPFULL indicating the state.

The empty signal generating section 220 generates a signal empty__ indicating that the data of each bank generated by the address control section 240 described later is empty.
a, dual port RAM based on empty_b
A signal EMPTY indicating a state where there is no data stored in 120, that is, an empty state is generated and output.

The address control section 240 generates various control signals for the dual port RAM 120 and the outside as described above,
20 manages the order of the data stored in the memory 20. The configuration of the address control unit 240 will be described in detail with reference to FIG. FIG. 5 is a circuit diagram showing a configuration of the address control unit 240. The address control unit 240 includes a RAM use area flag 241, a flag update unit 242, a write address decoder 243, and a bank A write address storage unit 24.
4, bank B write address storage unit 245, selector 246, next pointer 247, bank A read address selection unit 248, bank A read address register 2
49, bank B read address selector 250, bank B
It has a read address register 251, a bank A empty detection counter 252, and a bank B empty detection counter 253.

The RAM use area flag 241 stores a flag indicating whether or not unread data is stored in each address of the dual port RAM 120.
This is a 16-bit register in which one bit corresponds to each address of the dual port RAM 120 for managing the use state of the dual port RAM 120. The RAM use area flag 241 indicates that the write enable decoder 151
Signal ram_w indicating write of any bank
e_a (we_a inside the address control unit 240; the same applies hereinafter), ram_we_b (we_b), or a signal ram_re_a indicating reading of any bank from the read enable decoder 152.
When (re_a) and ram_re_b (re_b) are input, they are updated with new flag data applied from the flag update unit 242.

The flag update unit 242 has a dual port R
When data is written to and read from AM 120, that is, signals ram_we_a (we_a), ram_
Wem_b (we_b) and signals ram_re_a (re_a), ram_
When any of re_b (re_b) is input,
Update data of the RAM use area flag 241 is generated, and R
This is applied to the AM use area flag 241.

The write address decoder 243 has the RA
Based on the use flag of the storage area of the dual port RAM 120 stored in the M use area flag 241, an address for storing the next data is generated, and the bank A write address storage 244, the bank B write address storage 245, Output to the next pointer 247 and output from the address control unit 240 to apply to the dual port RAM 120. Note that when the bank A or the bank B is empty, the dual port RAM 12
When data is stored in 0, this address wp is
The next pointer 247 is directly input to the bank A read address selection unit 248 or the bank B read address selection unit 250 without any intervention, and is used for data reading.

The write address decoder 243
At this time, among the empty areas of the dual port RAM 120, the storage areas are selected in order from the one with the largest address,
Output the address. Further, the write address decoder 243 determines whether or not unread data has been stored in all storage areas of the dual port RAM 120 based on the use flag of the dual port RAM 120 stored in the RAM use area flag 241. That is, whether the dual port RAM 120 is full or not is detected.
Output l.

Bank A write address storage section 244
Is a register for storing the address of the dual-port RAM 120 to which data was written at the end of the bank A.
The bank A write address storage unit 244 stores the bank A
Signal ram_we_a (we_a) indicating writing to
Is activated, the output address of the write address decoder 243 is stored.

Bank B write address storage section 245
Is a register for storing the address of the dual port RAM 120 to which data was written at the end of the bank B.
The bank B write address storage unit 245 stores the bank B
Signal ram_we_b (we_b) indicating writing to
Is activated, the output address of the write address decoder 243 is stored.

The selector 246 operates in accordance with the bank to which data is to be written.
4 or the address stored in the bank B write address storage section 245 is selected, and the next pointer 247 is selected.
Is applied.

The next pointer 247 is a register for storing the order of data for each bank. The next pointer 247 is the same 1 as the dual port RAM 120.
It has an address space of 6 words and is a register file of 4 bits for each word. Then, the next pointer 24
7 stores the address output from the write address decoder 243 in the address selected and applied by the selector 246 every time new data is written to the dual port RAM 120. Thus, every time new data is written to the dual port RAM 120, the data is stored in the next pointer 247 at the address where the data before the data written to the same bank as the data is stored. The stored address is stored. In other words, each address of the next pointer 247 stores an address in the same bank as the data stored in the address and in which the next data following the data is stored.

The bank A read address selection section 248
The data of the bank A is sequentially selected from the 16-word data of the next pointer 247 and output to the bank A read address register 249. The bank A read address selection unit 248 outputs the data every time the data of the bank A is read.
It selects the data of the next pointer 247 of the address which is the data of the address selected by itself and is stored in the subsequent bank A read address register 249.

Bank A read address register 249
Is a register that stores the data of the next pointer 247 selected by the bank A read address selection unit 248, that is, the address ram_re_a (re_a) of the next read data stored as the data of the bank A. The stored address is The address is output from the address control unit 240 to the read enable decoder 152.

The bank B read address selection section 250
The bank B data is sequentially selected from the 16-word data of the next pointer 247 and output to the bank B read address register 251. The bank B read address selector 250 reads the bank B data every time
It selects the data of the next pointer 247 of the address which is the data of the address selected by itself and is stored in the subsequent bank B read address register 251 in order.

Bank B read address register 251
Is a register that stores the data of the next pointer 247 selected by the bank B read address selection unit 250, that is, the address ram_re_b (re_b) of the next read data stored as the data of the bank B. The stored address is The address is output from the address control unit 240 to the read enable decoder 152.

Bank A empty detection counter 252
Is a counter for counting the number of valid data in bank A, and a signal ram_we_ indicating writing to bank A
a (we_a) is incremented each time the signal is input, and a signal ram_re_
It is decremented each time a (re_a) is input. When the counter value is 0, it is determined that no data is stored in the bank A, and the empty signal r
am_empty_a (empty_a) is activated.

Bank B empty detection counter 253
Is a counter for counting the number of valid data in bank B, and a signal ram_we_ indicating writing to bank B is provided.
b (we_b) is incremented each time it is input, and a signal ram_re_
It is decremented each time b (re_b) is input. When the counter value is 0, it is determined that no data is stored in the bank B and the empty signal r
am_empty_b (empty_b) is activated.

Next, the FIFO memory 1 having such a configuration is described.
The operation of 00 will be described with reference to FIGS.
First, referring to FIG. 4 and FIG.
The operation will be described in detail focusing on the method of controlling the address at 0.

First, for example, when data of bank A (first system) is stored, dual port RAM 12
Input data DATAin is applied to 0, and the write enable signal we_a of the bank A is activated. The write enable decoder 151 of the control unit 150 of the FIFO memory 100 outputs the write enable signal we.
_A is detected, a write enable signal ram_we for the dual port RAM 120 is activated, and a signal ram_we_a (we_a) for writing data to the bank A is input to the address control unit 240. From the address control unit 240, the address of the empty area has already been detected by the write address decoder 243 and applied to the dual port RAM 120. Therefore, in the dual port RAM 120, the write enable signal ram_we from the write enable decoder 151 Data is recorded at the address wp specified by the write address decoder 243.

In the address control section 240, a signal ram_we_a for writing data to the bank A input from the write enable decoder 151 is output.
The write address wp is stored in the bank A write address storage unit 244 based on (we_a). Further, the flag updating unit 242 adds the address wp to the flag stored in the RAM use area flag 241.
New flag data in which the flag is used is generated.
1 is updated. This address wp is selected in the bank A read address selection section 248, and the bank A read address register
Is set as the address of the first data of further,
Based on the updated flag data of the RAM use area flag 241, the write address decoder 243 generates an address at which data is to be written next, and outputs it as a new address wp.

Next, assuming that data of bank B (second system) is stored, for example, dual port RAM 1
20, the input data DATAin is applied, and the write enable signal we_b of the bank B is activated. The write enable signal we_b is transmitted to the control unit 1
The 50 write enable decoders 151 detect and activate the write enable signal ram_we for the dual port RAM 120. As a result, the dual port RAM already output from the address control unit 240
Address ram_wp (wp) applied to 120
The input data is written in.

A signal ram_we_b (we_b) for writing data to the bank B is input from the write enable decoder 151 to the address control unit 240, whereby the write address wp is stored in the bank B write address storage unit 245. Is done. In addition, the flag updating unit 242 generates new flag data in which the flag at the address wp is used for the flag stored in the RAM use area flag 241. 241 is updated. This address wp is selected in the bank B read address selection section 250, and the bank B
The address is set in the read address register 251 as the address of the head data of the bank B. In addition, the updated R
Based on the flag data of the AM use area flag 241,
The write address decoder 243 generates an address at which data is to be written next, and outputs it as a new address wp.

Next, assuming that data of bank A is stored again, input data DATAin is applied to dual port RAM 120, and write enable signal we_a of bank A is activated. This write enable signal we_a is transmitted to the write enable decoder 15.
1 is detected and the write enable signal ram_we for the dual-port RAM 120 is activated, so that the address control unit 240
The address ram_wp (w
In p), the input data is written.

At this time, in the address control section 240, the selector 246 sets the address of the bank A write address storage section 24 in the selector 246 based on the signal ram_we_a (we_a) for writing data to the input bank A.
The address at which the data of bank A was recorded for the first time, which is the output of 4, is selected and applied to the next pointer 247, and the current data recording address, that is, the address at which the data of bank A is recorded for the second time, is selected. It is stored at the first data recording address. Then, as in the first time or when writing to bank B, this recording address is stored in the bank A write address storage unit 24.
4 and the flag updating unit 242 updates the content of the flag stored in the RAM use area flag 241, and the write address decoder 243 updates the content of the flag based on the updated flag data of the RAM use area flag 241. A write address is generated. Note that when additional data is stored from a state where data has already been stored, writing of an address from the write address decoder 243 to the bank A read address register 249 is not performed.

When reading data from bank A is requested in such a state in which data is written, the read enable signal re_a of bank A is activated. The read enable decoder 152 of the control unit 150 of the FIFO memory 100 detects the read enable signal we_a, and
The signal ram_re_a (r
e_a).

The address control unit 240 has already output the head address of the stored data of each bank to the selector 153 via the bank A read address register 249 and the bank B read address register 251. Then, in the selector 153, since the read enable signal re_b of the bank B is negative, the head address of the bank A, which is the output of the bank A read address register 249, is selected, and the dual port RA
M120. As a result, dual port RA
The head data of the bank A previously stored is read from M120 and output from the FIFO memory 100 via the output register 140.

In the address control section 240,
A signal ram_re_a (re) indicating that data of bank A input from read enable decoder 152 is read.
_A), the bank A read address selection unit 24
8 selects, from the next pointer 247, the data at the address from which the current data stored in the bank A read address register 249 has been read, and sets the selected data at the bank A read address register 249 as the address of the data next to the bank A. As a result, the address control unit 240
Thereafter, the new storage data head address of bank A is output to selector 153. Further, the address control unit 2
In 40, the flag stored in the RAM use area flag 241 by the flag update unit 242 is
New flag data in which the flag at the address wp is in an unused state is generated, and the content of the RAM use area flag 241 is updated accordingly.

In this manner, the reading and writing of data in each bank are performed sequentially.

Finally, the overall operation of the FIFO memory 100 will be described with reference to FIGS. FIG.
5A is a time chart showing the entire operation of the FIFO memory 100, FIG. 5A is a diagram showing an operation clock CLK of the FIFO memory 100, FIG. 5B is a diagram showing input data DATAin to the FIFO memory 100, and FIG. Data FIFOi applied to dual port RAM 120
(D) is a write enable signal WE_A for bank A, (E) is a write enable signal WE_B for bank B, and (F) is an entire empty signal E.
MPTY, (G) is full signal FULL, (H) is pre-
Full signal PFULL, (I) is pre-pre-full signal P
PFULL, (J) is a read enable signal for bank B, and (K) is output data FIFOout from dual port RAM 120.

First, as shown in FIG. 6B, data is sequentially input to the FIFO memory 100, data D0 to D3 are stored in bank A, and data D4 to D7 are stored in bank B. As shown in FIG. 6 (D) and FIG. 6 (E), when each write enable signal for bank A and bank B is activated, F
Signal processing is performed in the IFO memory 100, and data is stored in a desired form. When the data D0 is stored as shown in FIG. 6 (F), the empty signal becomes negative, and as shown in FIG. The full signal PPFULL becomes active, and the pre-full signal PFULL becomes active at the stage when seven data up to the data D6 are stored as shown in FIG.
As shown in FIG. 6 (G), the full signal FULL becomes active when eight data up to the data D7 are stored.

In this state, as shown in FIG. 6 (J), by activating the read enable signal of bank B, as shown in FIG. Are sequentially read.
F, together with the data reading, the full signal FULL shown in FIG. 6G, the pre-full signal PFULL shown in FIG. 6H and the pre-pre-full signal PPFULL shown in FIG. It is becoming. FI
The FO memory 100 operates in this manner.

As described above, in the FIFO memory 100 of the present embodiment, one dual port RAM 12
By using 0, two systems of FIFO can be realized. As a result, compared to a case where two completely independent FIFOs are provided, the FIFO margin can be reduced as a whole, and a part of the control circuit can be shared, resulting in a large circuit scale. Can be reduced. Further, the allocation of storage capacity in the two systems may be determined dynamically based on input data, and is not fixed in advance. Therefore, a more flexible buffer can be configured as a whole.

By applying the FIFO memory 100 having such a configuration to, for example, the three-dimensional image generating device 3 of the three-dimensional computer graphics system 1 as described above, each of them performs complicated and high-speed processing. Data transfer between the constituent parts can be efficiently performed with a small-scale circuit, and as a result, a desired image can be efficiently generated.

The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the present embodiment, a FIFO for processing two types (two systems) of data has been exemplified, but this is not limited to two systems, and an arbitrary number of systems may be processed.

The memory for actually storing data is
The invention is not limited to the dual port RAM, and a single port RAM may be used. In that case, for example, two single-port RAMs are provided, and data storage and reading are controlled so that storage and reading are not performed simultaneously on one single-port RAM, so that storage or reading cannot be performed simultaneously. A FIFO memory that performs the same operation as the present invention can be configured using a single-port RAM and without advancing the operation clock. Of course, any type of memory other than the single-port RAM may be used.

In the present embodiment, the FIFO
Memory 100 A three-dimensional image generation device has been illustrated as an application example of the memory 100, but the FIFO memory device can be applied to any suitable device as a normal FIFO memory.

[0086]

As described above, according to the present invention,
It is possible to provide a data storage device and a method thereof that can appropriately provide a FIFO function for data of a plurality of systems with a smaller circuit scale. In addition, it is possible to provide an image processing apparatus capable of appropriately performing data transfer in each processing unit with a smaller circuit scale and thereby efficiently performing desired image processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a three-dimensional computer graphics system to which an embodiment of the present invention is applied, to which a memory device of the present invention is applied;

FIG. 2 is a diagram logically showing a configuration of a memory device including an image memory and its peripheral circuits of the three-dimensional computer graphics system shown in FIG. 1;

FIG. 3 is a block diagram schematically showing a configuration of a FIFO memory of the memory device, which is suitable for showing a flow of data in the memory device shown in FIG. 2;

FIG. 4 is a circuit diagram showing a detailed configuration of the FIFO memory shown in FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of an address control unit of the FIFO memory shown in FIG. 4;

FIG. 6 is a time chart illustrating an overall operation of the FIFO memory illustrated in FIG. 3;

FIG. 7 is a diagram logically showing a configuration of a memory device including an image memory and its peripheral circuits of a conventional three-dimensional computer graphics system.

[Explanation of symbols]

1. 3D computer graphics system 2.
Input unit, 3 ... three-dimensional image generation device, 4 ... display device, 32
... Geometry calculation unit, 33 ... Parameter calculation unit, 34 ...
Pixel generation unit, 35 texture mapping unit, 36 texture memory, 37 memory interface, 38
... image memory, 39 ... programmable display control unit, 50 ... memory device, 51 ... MTXPC, 53 ... signal processing unit, 54 ... 1st RAM, 55 ... 2nd RAM,
100: FIFO memory, 120: Dual port RA
M, 140 ... output register, 150 ... control unit, 151 ...
Write enable decoder, 152 ... read enable decoder, 153 ... selector, 154 ... register, 16
0: write pointer section, 180: read pointer section, 2
00: full signal generation unit, 220: empty signal generation unit, 240: address control unit, 241: RAM use area flag, 242: flag update unit, 243: write address decoder, 244: bank A write address storage unit, 245 ... Bank B write address storage unit, 246
... Selector, 247 ... Next pointer, 248 ... Bank A read address register, 249 ... Bank A read address register, 250 ... Bank B read address selector, 251 ... Bank B read address register, 25
2 ... Bank A empty detection counter, 253 ... Bank B empty detection counter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B047 EA01 EA06 EA07 EB02 EB12 5B080 AA13 BA08 CA08 GA22 5C082 AA06 BA12 BA46 BB13 BB25 BB26 BB29 CB01 DA22 DA53 DA87 DA89 EA18 MM04

Claims (20)

[Claims] 1. Data storage means for sequentially storing data of a plurality of input systems, storage order management means for managing the storage order of data stored in the storage means for each of the systems, and data for each of the systems. In response to the output request, the stored data of the requested system is read out and output in the input order based on the storage order of the data for each system managed by the storage order management means. A data storage device having output means. 2. The storage order management means has an address space corresponding to the address space of the data storage means, and as the data of each address, the same as the data stored at the corresponding address of the data storage means. In the input data of the system, the storage order of the data stored in the storage unit is determined for each of the systems by a table that stores an address at which the stored data is stored next to the data of the address. The data storage device according to claim 1, wherein the data storage device manages the data. 3. The storage order management means according to claim 1, wherein an arbitrary address in a free area of said data storage means other than an area in which unread data is stored is used as a storage address for storing input data. Storage address generation means for generating, an address storage means for storing the storage address for the last input and stored data for each of the systems, and an address space corresponding to an address space of the data storage means, As the data of each address, the input data of the same system as the data stored in the corresponding address of the data storage means is stored next to the data of the address. The table for storing the address of the data storage means; Means for storing the generated storage address at an address stored in the address storage means of the table when stored at the generated storage address of the means; and 3. The data storage device according to claim 2, wherein the means stores the input arbitrary system data at the address generated by the storage address generation means. 4. The storage address generation means, comprising: a flag storage means for storing, for each address of the data storage means, a flag indicating whether or not unread data is stored at the address; A storage address selecting unit for detecting the empty region of the data storage unit based on the stored flag and selecting an address of any one of the empty regions as the storage address; 4. The data storage device according to claim 3, further comprising: a flag updating unit that updates the flag based on data storage and reading of the stored data by the output unit. 5. A read address storage for storing, as a read address, the storage address of the last address from which data was read from the data storage means for each of the systems as a read address. Means, when there is a request to output data of any of the systems, data reading means for reading and outputting data of the read address of the system stored in the read address storage means of the data storage means, The data storage device according to claim 4, comprising: 6. The data storage device according to claim 1, wherein said data storage means, said storage order management means and said output means are configured as a semiconductor integrated circuit. 7. The data storage device according to claim 6, wherein said data storage means has a dual port memory capable of storing and reading data in the same cycle. 8. A memory for storing input data of a plurality of systems in a memory, managing the storage order of the stored data for each of the systems, and controlling the storage order in response to a data output request for each system. A data storage method for reading and outputting the stored data of the requested system in the input order based on the storage order of the data for each system. 9. An address space corresponding to an address space of the memory for storing the data, wherein the data of each address is inputted in the same system as the data stored at the address of the memory. 9. The data according to claim 8, wherein the storage order of the stored data is managed for each system by a table that stores an address on the memory of data that is input next to the data of the address and stored in the memory. Data storage method as described. 10. The storage address for the last input and stored data is stored for each of the systems, and when data of an arbitrary system is input, the data has not yet been read from the memory. When an arbitrary address in a free area other than an area where data is stored is generated as a storage address for storing input data, and when the input data is stored in the generated storage address of the memory, 10. The data storage method according to claim 9, wherein the generated storage address is stored in a storage address for the last input and stored data of the stored system in the table. 11. The method according to claim 11, wherein the generation of the storage address sets a flag indicating whether or not unread data is stored in each address of the memory, and based on the stored flag. 11. The data storage method according to claim 10, wherein the data storage method is performed by detecting the free area of the memory and selecting an address of any one of the free areas as the storage address. 12. The method of reading data, wherein, for each of the systems, the storage address of the address from which the data was last read from the memory and stored in the table is stored as a read address. 12. The data storage method according to claim 11, wherein when there is a data output request of said system, said stored data of said read address of said system is read and output. 13. An image generating means for generating arbitrary display image data, an image memory for storing the generated display image data, and reading data of a desired area from the stored display image data. Output means for outputting as display screen data, the image memory comprising: a data storage means for sequentially storing data of a plurality of input systems; and a storage order of the data stored in the storage means for each of the systems. A storage order management unit that manages the data for each system, and in response to a data output request for each system, based on the storage order of the data for each system managed by the storage order management unit, Output means for reading out and outputting stored data in the order of input. 14. The basic polygon of three-dimensional image data in which an arbitrary three-dimensional solid model is represented as a set of basic polygons indicated by vertices having at least three-dimensional position information. Coordinate conversion means for performing predetermined coordinate conversion on the vertices, pixel data generation means for generating pixel data of the basic polygon based on data of vertices of the basic polygon, and the generated pixel The image processing apparatus according to claim 13, further comprising a texture mapping unit configured to perform texture mapping on the data using a desired texture pattern and generate display three-dimensional image data as the display image data. 15. The storage order management means has an address space corresponding to an address space of the data storage means,
As the data of each address, the input data of the same system as the data stored in the corresponding address of the data storage means is stored next to the data of the address. 14. The image processing apparatus according to claim 13, wherein a storage order of the data stored in the storage unit is managed for each system by a table storing addresses. 16. The storage order management means may use an arbitrary address of a free area other than an area of the data storage means in which unread data is stored as a storage address for storing input data. Storage address generation means for generating, an address storage means for storing the storage address for the last input and stored data for each of the systems, and an address space corresponding to an address space of the data storage means, As the data of each address, the input data of the same system as the data stored in the corresponding address of the data storage means is stored next to the data of the address. The table for storing the address of the data storage means; Table updating means for storing the generated storage address at an address stored in the address storage means of the table when stored at the generated storage address of the storage means; The image processing apparatus according to claim 15, wherein the storage unit stores the input arbitrary system data at the address generated by the storage address generation unit. 17. The storage address generation means, comprising: a flag storage means for storing, for each address of the data storage means, a flag indicating whether or not unread data is stored at the address; A storage address selecting unit for detecting the empty region of the data storage unit based on the stored flag and selecting an address of any one of the empty regions as the storage address; 17. The image processing apparatus according to claim 16, further comprising: a flag updating unit that updates the flag based on storage of data and reading of the stored data by the output unit. 18. A read address storage for storing, as a read address, the storage address stored in the table, of the address from which the data was last read from the data storage means, for each of the systems. Means, when there is a request to output data of any of the systems, data reading means for reading and outputting data of the read address of the system stored in the read address storage means of the data storage means, The image processing device according to claim 17, further comprising: 19. The image processing apparatus according to claim 13, wherein said data storage means, said storage order management means and said output means are configured as a semiconductor integrated circuit. 20. The image processing apparatus according to claim 19, wherein said data storage means has a dual port memory capable of storing and reading data in the same cycle.