JPH02145817U

JPH02145817U -

Info

Publication number: JPH02145817U
Application number: JP5629989U
Authority: JP
Priority date: 1989-05-15
Filing date: 1989-05-15
Publication date: 1990-12-11

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図及び第３図はこの考案の動作を説明する
ための波形図、第４図は従来の技術を説明するた
めのブロツク図、第５図及び第６図は従来の技術
の動作を説明するための波形図である。１……アドレスカウンタ、２Ａ，２Ｂ……メモ
リ、３……アンドゲート、４……固定遅延素子。 FIG. 1 is a block diagram showing an embodiment of this invention, FIGS. 2 and 3 are waveform diagrams for explaining the operation of this invention, and FIG. 4 is a block diagram for explaining the conventional technology. FIGS. 5 and 6 are waveform diagrams for explaining the operation of the conventional technology. 1... Address counter, 2A, 2B... Memory, 3... AND gate, 4... Fixed delay element.

Claims

[Claims for Utility Model Registration] A. An address counter that counts clock pulses of a fixed period and outputs the counted output as an address signal, and a desired address that is sequentially accessed from the first address by the address signal output from this address counter. In a delay generation circuit constituted by a memory in which a delay pulse generation command is written at an address that is accessed when the delay time has elapsed, B. A plurality of the above memories are provided, and the plurality of memories are connected from the above address counter. A delay generation circuit that is accessed by the upper and lower bit address signals of the output address signal and is configured to generate a delay pulse when read outputs are obtained from a plurality of memories.