JPS61133830U

JPS61133830U -

Info

Publication number: JPS61133830U
Application number: JP1503185U
Authority: JP
Priority date: 1985-02-05
Filing date: 1985-02-05
Publication date: 1986-08-21

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示すブロツク図、
第２図は上記実施例に於ける第１のメモリに記憶
された情報例を示す図、第３図は同第２のメモリ
に記憶された情報例を示す図、第４図は上記実施
例に於ける各部の信号タイミングを示すタイムチ
ヤート、第５図ａ，ｂは本考案の一実施例で対象
とするデイスクコントローラに於けるデイスクト
ラツクフオーマツトと、その各制御信号タイミン
グを示す図、第６図は従来の構成を示すブロツク
図である。１１……第１のメモリ（ＲＯＭ）、１２……第
２のメモリ（ＲＡＭ）、１３……クロツクカウン
タ、１４……コンパレータ、１５……アドレスカ
ウンタ、１６……アドレス選択回路（ＭＰＸ）、
１７……オアゲート、１８……ラツチ回路、Ｓ・
ＣＬＫ……システムクロツク、ＳＰ……セクタパ
ルス。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing an example of information stored in the first memory in the above embodiment, FIG. 3 is a diagram showing an example of information stored in the second memory, and FIG. 4 is a diagram showing an example of information stored in the second memory in the above embodiment. Figures 5a and 5b are time charts showing the signal timings of various parts in the disk controller according to an embodiment of the present invention, and diagrams showing the timings of each control signal. FIG. 6 is a block diagram showing a conventional configuration. 11...First memory (ROM), 12...Second memory (RAM), 13...Clock counter, 14...Comparator, 15...Address counter, 16...Address selection circuit (MPX),
17...OR gate, 18...Latch circuit, S.
CLK...System clock, SP...Sector pulse.

Claims

[Claims for Utility Model Registration] (1) A first storage means for storing pattern information that defines the generation order of each of the plurality of control signals, and time information that defines the generation timing of each of the control signals. a second storage means; a timekeeping means for performing time counting in response to a clock of a constant period;
a coincidence detection means for comparing the time information output from the memory means; and a coincidence detection means for receiving a coincidence detection signal from the coincidence detection means to switch the pattern information output from the first memory means, and the second memory means for switching the pattern information output from the first memory means. and an output control means for switching the time information output from the first storage means to the time information corresponding to the switched pattern information, and outputting the control signal from a predetermined plurality of bit positions of the pattern information output from the first storage means. 2. A control signal generating device according to claim 1, wherein the storage means is a rewritable memory. (2) The control signal generating device according to claim 1, wherein the first storage means is a rewritable memory. (3) The control signal generating device according to claim 1, wherein the second storage means is a rewritable memory. (4) The control signal generating device according to claim 1, wherein the first storage means and the second storage means are read and controlled by common address data, respectively.