JPH0618400Y2 - Voice processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a voice processing device for recording and / or reproducing voice.

[Prior Art] In recent years, integrated circuits (for example, MSM 6258 manufactured by Oki Electric Co., Ltd.) for recording and reproducing voice have been commercially available. It has both voice analysis and voice synthesis functions.
A recording device is configured by writing and reading audio information to and from an AM (random access memory).

The recording time is variable by switching the switch, and for example, 4 seconds and 8 seconds can be switched depending on the interval at which the start / stop terminal is triggered. That is, in order to record for 4 seconds, after the start / stop terminal is triggered, this terminal is triggered again 4 seconds later and the recording is finished at this point.

[Problems to be Solved by the Invention] In the above, in order to make the recording time accurate, it is necessary to accurately set the interval at which the start / stop terminals are triggered. The circuit requires an accurate 4 seconds or 8 seconds timing circuit.

Further, in order to make the recording time variable, a circuit configuration for that purpose must be added.

The present invention eliminates the need for a timing circuit for determining the recording / playback time, and enables time control with a simple circuit configuration.

[Problems to be Solved by the Invention] The present invention records and / or records a desired address signal of a control circuit for designating an address of a storage circuit for storing voice information.
Alternatively, a selection circuit for selecting in accordance with the reproduction time is provided, and writing and / or reading of audio information is stopped by this selected address signal.

[Embodiment] In the drawings, 1 is, for example, a 256 K-bit RAM,
It constitutes a memory circuit for storing voice information. Two
Is a voice analysis / synthesis circuit, for example, MSM 62 manufactured by Oki Electric.
58 is used. This has a function of converting a voice signal into digital voice information and a function of converting voice information into an analog voice signal, and accesses the voice information to the RAM 1 in order to execute both functions. And constitutes a control circuit. Reference numeral 3 is a switching circuit which constitutes a selection circuit, and 4 is a switching circuit for designating a storage area of the RAM 1. Reference numeral 5 is a one-shot pulse generator, and 6 is a gate circuit.

Next, the operation will be described. The voice analysis / synthesis circuit 2 is configured so that the recording and reproducing functions are switched according to the level of the terminal a, the above function is started by the first trigger of the terminal b, and the above function is stopped by the second trigger. ing.

Further, in this example, recording / reproducing for 8 seconds is performed by using half the storage area of RAM 1, and recording / reproducing for 4 seconds is performed by switching to the storage area of 1/4.

First, when recording / reproducing for 8 seconds, the switching circuits 3 and 4 are brought into the illustrated state by setting the terminal c to a predetermined level by an external switch (not shown).
That is, the address line A ₁₄ is connected to the one-shot pulse generator 5.

Therefore, the terminal a is set to a predetermined level to set recording or reproduction, and then a start pulse is supplied to the terminal f. As a result, the voice analysis / synthesis circuit 2 starts operating, and the address line A
Address signals are generated from _{0 to} A ₁₂ , and data lines D ₀ to
Audio information from D ₇ is access to RAM 1. Designation of writing / reading to / from the RAM 1 is performed by an output from the terminal RD / WR of the voice analysis / synthesis circuit 2. When the address advances and a signal is generated from the address line A ₁₄ , the one-shot pulse generator 5 is triggered via the switching circuit 3 to generate one pulse. This pulse triggers the voice analysis / synthesis circuit 2 to stop the recording / playback operation.

In this way, write / write in half the memory area of RAM1.
The reading is performed and the recording / playback for 8 seconds is performed.

Note that which half of the storage area of the RAM 1 is used is specified by the output from the terminal e.

Next, when recording / reproducing for 4 seconds, the level of the terminal c is inverted to switch the states of the switching circuits 3 and 4. As a result, the address line A ₁₃ is connected to the one-shot pulse generator 5.

Therefore, when an address signal is generated from the address line A _{13, a} pulse is generated from the one-shot pulse generator 5 and the operation of the voice analysis / synthesis circuit 2 is stopped. Ie R
It stops when writing / reading is performed on the 1/4 storage area of AM1. The storage area of the RAM 1 used in this case is determined by the outputs from the terminals d and e.

[Advantage of the Invention] According to the present invention, since the writing / reading of the voice information is stopped by the predetermined address signal to the voice information storage circuit, the timing circuit for determining the recording / playback time becomes unnecessary. , It is possible to switch the recording / playback time accurately with a simple structure.

[Brief description of drawings]

 The drawing is a logic circuit diagram showing an embodiment of the present invention. 1 ... RAM 2 ... Voice analysis / synthesis circuit 3 ... Selection circuit

Claims (1)

[Scope of utility model registration request] 1. A storage circuit for storing voice information, a control circuit for controlling writing and / or reading of voice information by designating an address of the storage circuit, and a switching of recording and / or reproducing time of voice information. A voice processing device comprising: a selection circuit for selecting a desired address signal of the control circuit, wherein writing and / or reading of the voice signal is stopped by the address signal selected by the selection circuit.