JPH0239040B2 - - Google Patents

Abstract

PURPOSE:To obtain a reproduced voice signal which is free from click noise, by controlling reading of a memory with the output that detected the level of the reproduced voice signal and connecting the read signal with the consecutive signal. CONSTITUTION:A double-speed voice monitor device or the like consists of such as a register 1, 1st and 2nd RAMs 2 and 3, a subtractor 4, a level detector 5, gates 6, 7, 9 and 10, address memories 11 and 12, gates 8, 13 and 14, address memories 15 and 16, address counters 17 and 18, a flip-flop 20, a D/A converter 21, and a 4-bit counter 22. The voice signal reproduced with the nonstandard speed is written intermittently into memories 2 and 3 and then read out with a change of the time axis to be turned into a consecutive signal reproduced approximately reduced to the standard speed. In this case, these signals are connected together at the equal level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audio monitoring device used when reproducing audio signals recorded on a magnetic tape, magnetic disk, record, etc. at a non-standard speed.

Dubbing (copying) such audio recording signals,
In a search or the like, the data is reproduced at a higher speed (for example, double speed) than the standard speed at which it was recorded, and the recorded content is monitored to check. Since the reproduced signal has a higher frequency than the standard, this is converted to the standard speed frequency.

FIG. 1 is a waveform diagram of a reproduced audio signal showing a conventional frequency conversion method. Although FIG. 1A is a waveform diagram of a double-speed audio reproduction signal, recording and reproduction is not limited to analog signals, and PCM signals may also be used. For example, every 0.2 sec interval of the reproduced signal, a half 0.1 sec section of the signal is sampled and code-modulated, and this is
Write to RAM (random access memory), etc.
The time axis is expanded and read out from the RAM to a time width of 0.2 seconds, and the audio signal shown in FIG. 1B is obtained. For example, since the same sound of human speech continues for 0.2 seconds or more, the reproduced signal can be monitored even with the signal shown in FIG. 1B, in which the signal for the latter half of 0.1 seconds of FIG. 1A is missing.

However, in this method, the signal connections shown in FIG. 1B become discontinuous and change abruptly from a low level to a high level or from a high level to a low level, resulting in click noise and extremely difficult to hear sound.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to obtain a reproduced audio signal free of click noise.

The non-standard speed audio monitoring device of the present invention writes a reproduced audio signal during non-standard speed playback, for example, double speed, to the memory (RAM2, 3), reads it by changing the time axis, and writes the reproduced audio signal to the memory (RAM2, 3) and reads it out by changing the time axis. It is based on the principle of thinning out written or read data at predetermined time intervals during reading to obtain a continuous audio signal that corresponds to standard speed playback.

The register 1, subtracter 4, level detector 5, and gate 6 shown in FIG. 2 constitute a detection circuit that detects one of the negative-to-positive or positive-to-negative zero crossing points of the reproduced signal.

The memory write address corresponding to the zero cross point at the start of the non-thinning section of the memory write data is
A first address memory 11, 15 that stores the write address based on the output of the detection circuit, and a second address that stores the write address of the memory corresponding to the zero cross point at the end of the non-thinning section based on the output of the detection circuit. Memories 12 and 16 are provided, respectively.

Based on the outputs of the first and second address memories, address generating means (address counter 1
7, 18), and an audio signal combining the zero-crossing point at the end of the non-thinning section and the zero-crossing point at the starting end of the next non-thinning section is obtained based on the output of the memory. do.

According to this configuration, both the leading edge and the trailing edge of one non-thinning section of the reproduced audio signal read out from the memories 2 and 3 while changing the time axis are from negative to positive (or from positive to negative) of the input reproduced audio signal. ) corresponds to the zero cross point to Therefore, if the non-thinned sections are made to be temporally continuous by writing to the memory and reading with a changed time axis, the trailing edge of the adjacent front section and the leading edge of the rear section will be at approximately zero level of the audio waveform. and are joined at a point in the same inclination direction. Therefore, since no discontinuities occur in the spliced audio waveforms, high-quality monitor sound can be reproduced at a non-standard speed without generating unpleasant clicking sounds.

Note that it is also possible to connect the waveforms at points other than the zero level, but in this case, in order to match the level and slope direction of the waveform before and after the joining point, registers and registers that store the values of multiple consecutive sample points of the waveform are required. A data comparator is required to discriminate the size and increase/decrease direction of each data in this register before and after the junction point, resulting in an extremely complicated configuration. On the other hand, according to the configuration of the present invention, it is only necessary to detect the zero crossing of the waveform from negative to positive (or from positive to negative), so the circuit configuration is very simple. Furthermore, since the audio signal always has a zero-crossing point no matter what the sound source and the reproduction state, extremely stable joining operation can be obtained.

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, it is assumed that the audio signal is recorded in PCM.

FIG. 2 is a block diagram of the signal converter of the double-speed audio monitoring device according to the present invention, and FIG. 3 is a time chart for explaining the operation of FIG. In Figure 2, the double-speed playback audio signal PB (12-bit PCM
signal) is sent to the first RAM2 and the
2Supplied to RAM3. These RAMs 2 and 3 are supplied with an address signal W-ADD from a write address generator (not shown), and the address signal W-ADD in FIG.
Input data is stored one after another according to address numbers (1 to 32) indicated by ADD. In addition, RAM2 and 3
The enable input of the control signal e shown in FIG.
1 and an inverted signal e2 are supplied, and the RAMs 2 and 3 perform storage operations alternately at a period of, for example, 0.2 seconds.

The register 1 has a delay record (one clock delay) of one data of the input reproduced PCM signal, and its input and output are supplied to the subtracter 4. The subtracter 4 subtracts the PCM data of the current sample value from the PCM data of the previous sample value. When the subtraction result is negative, that is, when the data is increasing, the output of the subtracter 4 is at a low level. play on the other hand
The PCM signal is supplied to the level detector 5, and the 0 level value of the PCM data is detected. When the level data of the reproduced PCM signal is around 0, the output of the level detector 5 is at a low level. Note that the level detector 5 operates with a clock pulse CP for each PCM data cycle.

Since the outputs of the subtracter 4 and the level detectors 4 and 5 are supplied to the gate 6, the timing signal in the part marked with ◯ of the reproduced waveform in FIG. 3A is obtained from the gate 6. That is, the zero crossing point of the increasing portion of the reproduced PCM signal is detected. The zero cross detection signal a is
Address memory 1 through gates 7, 9, 10
1 and 12 enable inputs. A control signal e1 shown in FIG. 3C is supplied to the gate 7,
Also, in gate 9, the first half P which is divided into two parts of e1
A control signal c (FIG. 3B) which becomes high level at (0.1 sec) is supplied, and a control signal which becomes high level at the latter half S of e1 is supplied to the gate 10.

Further, the address memory 11 is supplied with the write address signal W-ADD which is supplied to the RAMs 2 and 3. Therefore, in the address memory 11,
The address ("4" in FIG. 3) of the first zero cross point in the first half P of the write period of the first RAM 2 is stored. The address memory 12 also stores the address of the first zero cross point in the second half S ("20" in FIG. 3). Note that the enable signal supplied to the address memories 11 and 12 is output from the gates 9 and 10 only once at the first zero cross point.

Similarly, the zero cross detection signal a output from gate 6 is supplied to enable inputs of address memories 15 and 16 through gates 8, 13 and 14.
Therefore, the address of the first zero cross point in the first half P of the write period e2 of the second RAM 3 ("3" in FIG. 3) is stored in the address memory 15.
The address memory 16 also stores the address ("17" in FIG. 3) of the first zero cross point in the second half S of the write period of the RAM 3.

The data written in the first RAM 2 and the second RAM 3 are read out as follows. Note that RAM2 and 3 are set to 1 so that writing and reading are performed in parallel.
It has twice the storage capacity of cycles.
Read address signals R-ADD for RAMs 2 and 3 are supplied from address counters 17 and 18. These counters 17 and 18 count 1/2 CP of the clock having a period twice the data period of the reproduced PCM signal to form an address signal. counter 17,1
The counter 8 consists of a start/stop counter, and the counter 17 starts counting with the contents of the address memory 11 at "4" and starts counting with the contents of the address memory 12 at "20".
Stop counting. Therefore, addresses of 4 to 20 double cycles as shown by R-ADD in FIG. 3 are formed.

When the counter 17 stops, a stop signal j is sent to the address counter 18, and the counter 1
8 starts counting when the address memory 15 contains "3" and stops counting when the address memory 16 contains "17". Therefore, addresses of 3 to 17 double cycles as shown by R-ADD in FIG. 3 are formed. Note that when the counter 18 stops, the stop signal k
is sent to the counter 17, and the counter 17 starts operating.

The data stored in the first and second RAMs 2 and 3 in this manner is read out at twice the cycle as shown in FIG. 3D. The read data is substantially equivalent to the standard playback frequency. RAM2,3
The output of the flip-flop 20 is supplied to the selector 19 and is set and reset by the stop signals j and k of the address counters 17 and 18.
The output is switched according to the output of RAM1/RAM2, and is further derived as an audio signal via the D/A converter 21.

As shown in Figure 3D, the outputs of RAM2 and 3 are:
Since the signals are always combined at the increasing portion of the reproduced signal and at the zero cross point, there is no large level fluctuation at the signal junction, and therefore a good monitor signal without click noise can be obtained.

Note that when the input reproduction signal PB becomes non-signal, negative pulses are continuously obtained from the output of the level detector 5. This negative pulse is supplied to a 4-bit counter 22, and when four or more negative pulses continue, a positive pulse is generated from the counter 22. Therefore, this positive pulse is applied to gates 7, 8, 9, 10, 1
Address memory 11, 12, 1 through 3, 14
5 and 16 as an enable signal, the address of the positive pulse position is stored.

Although they are connected at the zero-crossing points of the increasing portion, they may be connected at the zero-crossing points of the decreasing portion. Furthermore, although the above-mentioned embodiment describes a monitor device for double-speed playback, the present invention can also be applied to cases of other higher playback speeds.

In addition, if the reproduced signal has an extremely low frequency and there is no zero cross point, the output of the RAM is combined at the rear end of the section P (first half) of the first RAM and the front end of the section P of the second RAM in Figure 3B. It can be configured to:

As described above, according to the present invention, the level does not suddenly change at the splicing portion of the thinned out audio signals, and a standard speed monitor audio signal that does not produce clicking sounds even during non-standard speed playback can be produced using a relatively simple circuit.
can be obtained stably. Furthermore, since the thinned out audio signals are joined at the zero cross point, a stable joining operation can be obtained regardless of the sound source and reproduction state.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing the conventional standard conversion method for double-speed playback frequency, FIG. 2 is a block diagram of the signal conversion section of the double-speed audio monitoring device according to the present invention, and FIG. 3 is for explaining the operation of FIG. 2. This is a time chart. In addition, in the symbols used in the drawings, 1...Register, 2, 3...RAM, 4...Subtractor, 5...Level detector, 11, 12...Address memory, 15, 16...Address memory ,1
7, 18...address counter.

Claims (1)

[Claims] 1. Writing a reproduced audio signal during non-standard speed reproduction into a memory and reading it out while changing the time axis,
In an audio monitoring device that thins out the written or read data at predetermined time intervals during memory writing or reading to obtain a continuous audio signal that corresponds to standard speed playback, A detection circuit that detects one of the negative zero-crossing points, and a memory write address corresponding to the zero-crossing point at the start of the non-thinning section of the memory write data.
a first address memory that stores data based on the output of the detection circuit; and a second address memory that stores a memory write address corresponding to the zero-crossing point at the end of the non-thinning section based on the output of the detection circuit. , address generating means for generating a memory read address for the non-thinning section based on the outputs of the first and second address memories, and a zero cross point at the end of the non-thinning section and the next non-thinning section. An audio monitoring device for non-standard speed playback, characterized in that an audio signal combined with a zero crossing point at a starting end is obtained based on the output of the memory.