JPS6028983Y2 - Recording and playback device - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a storage means (
The present invention relates to a recording/playback device using a RAM (hereinafter referred to as RAM).

When practicing pronunciation of a foreign language using a conventional magnetic recording/playback device, one first records one's own pronunciation and then plays it back for confirmation.

However, in order to perform the above operations using a conventional magnetic recording and reproducing device, (a) one must record one's own voice;

It is necessary to repeat operations such as (b) rewinding the magnetic tape by a predetermined length and (C) reproducing the magnetic tape, and there are disadvantages associated with these operations.

On the other hand, when controlling the start and end of recording using an audio signal detection circuit that detects the presence or absence of an audio signal and inverts the output, so-called VOx circuit, the beginning of the audio may be delayed due to the detection time delay of the audio signal detection circuit. There was a drawback that some parts of the recording were missing.

The present invention has been developed in consideration of the above, and enables recording and playback without the need for rewinding the magnetic tape as in conventional magnetic recording and playback devices, and uses an audio signal detection circuit to detect the beginning of the voice. An object of the present invention is to provide a recording/playback device capable of performing recording without missing parts.

The configuration of the present invention will be explained based on FIG. 1.

In the present invention, an A/D conversion means 2 converts an input analog audio signal (hereinafter referred to as an audio signal) supplied from a microphone 1 into a digital signal (hereinafter referred to as audio signal data). It is provided with D/A conversion means 4 for converting the audio signal data read from the RAM 3 which stores the converted audio signal data into an analog signal.

The RAM 3 is divided into a first area 3a, a second area 3b having the same storage capacity as the first area 3a, and a third area 3c.

Also, a recording instruction means 5 for instructing recording, an audio signal detection circuit 6 to which an audio signal is supplied, and a first write control means 7 based on the output of the recording instruction means 5 and the output of the audio signal detection circuit 6.
, a selection means 10 for selecting the second write control means 8.

Furthermore, the audio outputted from the A/D conversion means 2 by cyclically instructing the addresses of the first area 3a and selected from the time when the recording instruction means 5 inputs the start of recording to the time when the audio signal detection circuit 6 detects the audio signal. The first write control means 7 instructs to write signal data, and following the selection of the first write control means 7, the address of the third area 3c that is selected during the audio signal detection period is sequentially designated and the A/D is A second write control means 8 instructs to write the audio signal data outputted from the conversion means 2, and a second
After completion of writing by the write control means 8, the memory contents at the address next to the last address selected by the first write control means 7 are sequentially read.
Transfer instruction means 9 for instructing transfer of all storage contents of the first area 3a to the second area 3b, and after completion of this transfer, the second area 3b
It is provided with a control means 11 for sequentially reading out the storage contents of the third area 3c following the storage contents of the third area 3c.

Therefore, from the time when a recording instruction is given by the recording instruction means 5 until the time when an audio signal is detected by the audio signal detection circuit 6, the audio signal data output from the A/D conversion means 2 is transferred to the first writing control means 7. The information is circulated and sequentially stored in the first area 3a.

Here, the first area 3a is set to have a storage capacity larger than that capable of storing the output audio signal data from the A/D conversion means 2 during the audio signal detection delay period of the audio signal detection circuit 6.

During audio signal detection by the audio signal detection circuit 6 following completion of writing into the first area 3a by the first write control unit 7, the audio signal data output from the A/D conversion unit 2 is transferred to the third area. 3c, the second write control means 8
be memorized by

After the second write control means 8 finishes writing to the third area 3c, the entire storage contents of the first area 3a are sequentially transferred and stored in the second area 3b by the transfer instruction means 9. It will be done.

Here, since the storage capacity of the first area 3a and the storage capacity of the second area 3b are selected to be equal, this transfer transfers all the storage contents in the first area 3a to the second area 3b without excess or deficiency. will be transferred and stored.

Further, since the storage contents of the first area 3a are transferred to the second area 3b sequentially from the storage contents at the address next to the last address specified by the first write control means 7, An audio signal detection circuit 6 is provided in the area 3b.
The audio signal data corresponding to the beginning of the audio signal that was missing due to the detection delay will be stored, and the audio signal data stored in the second area 3b and the audio signal data stored in the second area 3c will be stored. This means that continuity is maintained with the stored audio signal data.

Next, after the transfer by the transfer instruction means 9 is completed, the storage contents of the second area 3b and the third area 3c are sequentially read by the readout control means 11, and the read audio signal data is sent to the D/A conversion means. 4 into an analog signal.

Therefore, the audio signal is reproduced from the D/A conversion means 4, and the beginning of the audio signal is not lost due to the detection delay of the audio signal detection circuit 6.

Hereinafter, a specific example of the present invention will be described by way of an example.

The second is a block diagram showing the configuration of an embodiment of the present invention.

The audio signal supplied from the microphone 1 is supplied to the A/D converter 12 via a low-pass filter 20 for removing aliasing noise caused by sampling, and is converted into audio signal data.

On the other hand, the analog signal output from the D/A converter 14 is sent to the output terminal OUT via the low-pass filter 21.

On the other hand, 24 is a microcomputer, which basically includes CPU25, RAM26, and RAM2.
7. An audio signal detection circuit, a so-called VOX circuit, which is composed of an input port 28 and an output port 29, and detects the presence or absence of the audio signal by receiving the audio signal supplied from the microphone 1 and detecting the presence or absence of the audio signal. 6, the output of the recording instruction switch 15, the output of the playback instruction switch 22, the output of the pause switch 23 that instructs pause, and
The audio signal data output from the /D converter 12 is supplied to the input port 28.

A program for controlling the CPU 25 is written in the RAM 26, and the CPU 25 connects the audio signal detection circuit 6 via the input port 28 according to the program in the RAM 26.
output, output of recording instruction switch 15, output of playback instruction switch 22, output of body switch 23, A/D converter 1
Read the audio signal data from 2 when you need it,
The data is stored in the RAM 27 or a register, and processing such as transfer, judgment, calculation, and comparison of stored data is performed, and according to this processing, a conversion instruction signal is sent to the A/D converter 12 via the output port 29 as necessary. A conversion instruction signal and stored audio signal data are respectively sent to the D/A converter 14.

FIG. 3a is a circuit diagram showing an example of the audio signal detection circuit 6. FIG.

The audio signal circuit 6 includes an operational amplifier circuit 30, a capacitor 31.
35 and resistors 32, 33, and 34, and a rectifier circuit 6B that comprises diodes 37, 38, capacitors 36, 39, and resistor 40 and doubles and rectifies the output voltage of the amplifier 6A.

The audio signal detection circuit 6 amplifies the audio signal output from the microphone 1 with an amplifier 6A, and the audio signal amplified with the amplifier 6A is voltage doubled and rectified with a rectifier circuit 6B and output.

Therefore, when the audio signal detection circuit 6 is supplied with an audio signal having a waveform as shown in FIG. 3, it detects this and generates an output as shown in FIG. 3C.

Therefore, there is a detection delay due to the time constants of the amplifier 6A and the rectifier circuit 6B, and as shown in FIG. The output disappears, and the audio signal detection is interrupted within a predetermined period, and the output continues to be generated without being inverted.

Also, a recording instruction switch 15, a playback instruction switch 22,
Each of the pause instruction switches 23 has one contact connected to the power supply voltage Vcc via a pull-up resistor, and the other contact directly grounded. Output is performed when a recording instruction, playback instruction, or pause instruction is issued.

Further, the RAM 27 has an audio signal data storage area corresponding to the RAM 3, and in the audio signal data storage area, the first area has a starting address value of Mis, a final address value of Ml, a final address value of Mis, and a first area of the audio signal data storage area. The start address value of area 2 is M2. , (=M1゜+1),
The final address value is M2E1, and the first address value of the third area is M3. (=M2e, +1), the final address value is M
3E, and Ml between the first region and the second region.

−M□,=M2E M2f3 is set to hold.

The operation of one embodiment of the present invention constructed as described above will be explained with reference to the flowchart shown in FIG.

When the program written in the ROM 26 is operated, a key manual subroutine is executed to read the output states of the recording switch 15 and the pause instruction switch 23 (step a).

As shown in FIG. 5, the key manual subroutine clears the contents of the recording instruction storage area of the RAM 27 when the output 23 is at a high potential (step a-2).

When the pause instruction is not given in step a-t or following step a-2, the recording instruction switch 1
The output state of step 5 is continued (step a-3), and when a recording instruction is issued in step a-3, data corresponding to the recording instruction is stored in the recording instruction storage area (step a-1).

When no recording instruction is given in step a-, or following execution of step a-4, the process returns to the main routine shown in FIG. 4 and determines whether the contents of the recording instruction storage area are recording instructions (step b). .

When it is detected in step b that a recording instruction has been given, the first address value M19 of the first area of the RAM 27 is set in the register R1 (step C), and the A/D converter 12 is subsequently instructed to convert. Output a signal (step d).

Upon receiving this conversion instruction signal, the A/D conversion means 12 samples the audio signal input through the low-pass filter 20 and converts it into audio signal data.

The audio signal data read in step d and output from the A/D converter 12 is input into the register R8.Step e
), R where the contents of the register pull are indicated by the contents of register R□
Write to the address of AM27 (step f).

Following step f, the output state of the audio signal detection circuit 6 is read to detect whether the output of the audio signal detection circuit 6 is at a high potential (step g), and in step g, the output state of the audio signal detection circuit 6 is at a low potential. Then, following step g, "'+1" is added to the contents of register R□ (step h).

Following step h, it is determined whether the contents of the register Ro are larger than the address value M1° (step 1), and steps 1 to i are repeated until the contents of the register R1 become larger than the address value M1° in step i. The contents of register R1 are the address value MI
! When the voltage is larger than that, the step mill step i is repeated, and when it is detected that the output of the audio signal detection circuit 6 is at a high potential, the loop of steps a-i and d-i is removed.

Therefore, until it is detected in step g that the output of the audio signal detection circuit 6 is at a high potential, the audio signal data output from the A/D conversion means 12 is sequentially stored in the RAM 27.
will be circulated within the first region.

When the audio signal data is stored in the entire first area in the storage of the first area, the old storage content is updated,
From the time when it is detected that the output of the audio signal detection circuit 6 has become a high potential (indicated by tl in FIG. 6), the audio signal data corresponding to the storage capacity of the first area is stored in reverse order in time. , are stored in the first area.

In step j, when it is detected that the output of the audio signal detection circuit 6 has become a high potential, the contents of the register R1 are saved to the register R2 (following step j, the contents of the third area of the RAM 27 are stored in the register R0). A first address value M3E is set (step k).

Step k is followed by step d. A like ef
Step l) Output a conversion instruction signal to the /D converter 12.
Steps m and n) of storing the audio signal data output from the A/D converter 12 in the address of the RAM 27 specified by the contents of the register R1.

It goes without saying that the storage location of the audio signal data in steps m and n is within the third area.

Following step a-, the contents of register R1 are changed to '+
1”L (step O), followed by the audio signal detection circuit 6
Step p) to detect whether the output of the audio signal detection circuit 6 is at a low potential or not, and when the output of the audio signal detection circuit 6 is at a high potential in step p, it is determined whether the contents of the register R1 are slightly larger than the address following step p. Step q) Steps 1 to q are repeated until the contents of register R1 are no longer greater than the address value kE in step q.

When it is detected in step p that the output of the audio signal detection circuit 6 is at a low potential, step 1
~Extract from the loop in step q.

Therefore, in steps 1 to q, the audio signal data output from the A/D converter 12 is sequentially stored in the third area of the RAM 27 following time t1 shown in FIG. until the output of the audio signal detection circuit 6 becomes a low potential or the third
This continues until the audio signal data is stored in the entire area.

When it is detected in step p that the output of the audio signal detection circuit 6 is at a low potential, and when it is detected in step q that the contents of the register R1 are larger than the address value M section, the contents of the register R1 are Register R
3 and step r), then set the contents of register R2 + 1° in register R1 in step S), and then set the first address value M2s of the second area of RAM 27 in register R4. (step t),
Following step t, the stored audio signal data is transferred from the address of RAM 27 specified by the contents of register R1 to register R8 (step U), and following step U, the contents of the register are transferred to the RAM 27 of register R4 specified by the contents. The data is transferred to and written to the address (Step V).

Following step V, the contents of register R1 are changed to “+1°”.
Step W), then write “ to the contents of register R1.
+1” (step X).

Following step X, the contents of register R1 are changed to register R.
2 is equal to “content +1” (step y
).

At step y, the contents of register R□ are changed to register R2.
If it is not equal to '6 content + 1''°, it is determined whether the content of register R1 is greater than address value M1E (step 2).

In step 2, the contents of register R1 are set to address value M.
If it is not larger than 1B, repeat steps U to 2 until the contents of register R1 are thicker than address value MIE, and if it is determined in step 2 that the contents of register R1 are larger than address value MIE, Following step 2, the address value M1. is placed in register R1 (step ab), followed by step U~
The loop in step 2 is extracted when the contents of register R1 become equal to the contents V' of register R2 in step y.

Therefore, by steps U to ab, the RAM 27
All the audio signal data stored in the first area will be sequentially transferred to the rate 2 area.

As schematically shown in FIG. 6, if the contents of the register R2 at step j are α, the address after FIG. 6 is α (Ml, ≦α≦MIE).

In step UXV, the audio signal data stored at the address (α+1) in the first area of the RAM 27 is transferred to the first address M2s in the second area of the RAM 27 via the register tag, and the same is sequentially transferred in the same manner. RAM
The audio signal data stored at address α in the first area of RAM 27 is transferred to the final address M2E of the second area of RAM 27, and step aC is executed.

Therefore, when step aC is executed, it is already R
All the audio signal data of the first area is transferred and stored in the second area of AM27, and the audio signal data stored in the second area and the audio signal data stored in the third area are The audio signal data that is present maintains temporal continuity,
It is detected that the output of the audio signal detection circuit 6 has a high potential, and the audio signal data is sequentially stored in the third area of the RAM 27. However, due to the detection delay of the audio signal detection circuit 6, the missing audio signal data The audio signal data of the head part is stored in RAM27.
is stored in the second area from the final address side of the second area.

In step y, when the contents of register R□ are equal to the "contents + 1" of register 2, step y continues, register R1 is set to address M2!3, and step aC
), followed by the RA specified by the contents of register R1.
The audio signal data stored in the RAM 27 is transferred from the address of M27 to the register R8 (step ad), and the contents of the register R8 are then output to the D/A converter 14 (step ae).

Following step ae, a conversion instruction signal is output (step af), and the contents of register R□ are set to “+1”L.
, (step ag), the contents of register R□ are register R
3, and repeat step ad until the contents of register R□ become larger than the contents of register R3.
~Repeat step ah.

Therefore, by steps aC to ah, R
The stored contents from the first address of the second area of AM27 to the address where the audio signal data of the third area is stored are sequentially read out and converted into analog signals by the D/A converter 14. The analog signal is smoothed by a low-pass filter 21 and output.

As a result, one reproduction is performed.

In step ah, the contents of register R□ are changed to register R.
When it is detected that the content has become larger than the content of 3, the output state of the playback instruction switch 22 is read (step ai).
, when the output of the reproduction instruction switch 22 is at a high potential in step ai, steps aC to step ai are repeatedly executed.

As a result of this execution, regeneration is repeatedly performed while the output of the regeneration instruction switch 22 is at a high potential.

Further, if it is detected in step ai that the output of the regeneration instruction switch 22 is at a low potential, that is, that no regeneration instruction has been issued, the key manual subroutine is executed in step a.
), if no recording instruction is given in step b, step ai is executed.

Therefore, from step aC to step ai, RAM2 is
7, the audio signal data stored in the third area up to the address where the audio signal data is stored is sequentially read, and is converted into an analog signal by the D/A converter 14. will be played.

Moreover, regardless of the detection delay of the audio signal detection circuit 6, the RA
The second area of M27 stores the audio signal data of the part that is missing due to the detection delay, and during playback, it is played back before the audio signal data stored in the third area, so that the missing part of the beginning part is not included in the reproduced signal. do not have.

As explained above, according to the present invention, recording and playback can be performed without requiring operations such as rewinding and playback instructions, which were required in conventional magnetic recording and playback devices.

Furthermore, recording can be started with the speaker's voice, and the beginning of the recording will not be lost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the functions of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 3a is a circuit diagram showing an example of an audio signal detection circuit, and FIG. and C are waveform diagrams for explaining the operation of the audio signal detection circuit shown in FIG. FIG. 3 is a schematic diagram for explaining the operation of an embodiment of the invention. 1...Microphone, 2...A/D conversion means, 3...RAM, 4...D/
A conversion means, 6... Song audio signal detection circuit, 7 and 8.
...first and second write control means, 9...
...Transfer instruction means, 1゜...Selection means, 1
1... Readout control means.

Claims (1)

[Scope of utility model registration request] A/D conversion means for converting an analog audio signal into a digital signal; a readable/writable storage means that is divided into first to third areas and stores the output of the A/D conversion means; and a storage means for reading from the storage means. a D/A conversion means for converting the digital signal into an analog signal, a recording instruction means for instructing recording, an analog audio signal detection circuit for detecting the presence of an analog audio signal, and an output of the recording instruction means and audio signal detection. a selection means for selecting the first write control means and the second write control means based on the output of the circuit; and a selection means for selecting the first write control means and the second write control means based on the output of the circuit; A/ in the first area
The output of the D conversion means is selected by the cyclic writing control means and the audio signal detection circuit is selected by the audio signal detection circuit after the writing by the first write control means is completed, and the output of the A/D conversion means is stored in the third area of the storage means. The second step is to instruct sequential writing.
and a write control means of the storage means at an address next to the last address selected after completion of writing by the write control means to the third area of the storage means and specified by the first write control means of the storage means. 1. A recording and reproducing apparatus comprising: a transfer control means for instructing transfer to a second area; and a control means for sequentially reading from an area of a storage means to a third area after being transferred by the transfer control means.