JP2007183586A - Display device, control circuit thereof, and electronic appliance incorporating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve downsizing and cost reduction of a display device by efficiently using a physical region of a memory in the control circuit of the display device. <P>SOLUTION: In video data storage of the control circuit, its structure is provided with a video data storage for storing video data of an n-th frame (n is a natural number), a video data storage for storing video data of an (n+1)-th frame, and a video data storage for sharing video data of the n-th frame and the (n+1)-th frame among received video data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device and a display device driving method, and more particularly to a display panel control circuit using a light emitting element for a pixel. The memory control circuit controls writing and reading in a memory such as an SRAM (Static Random Access Memory).

  Note that the display panel control circuit here refers to a video that is converted from video data received so that gradation expression in the pixels of the display panel can be expressed, written in the storage means, and read from the storage means for display. Data is output to the display panel.

  The display device includes a display and a peripheral circuit that inputs a signal to the display.

  2. Description of the Related Art In recent years, a display device that replaces a liquid crystal display (LCD) is composed of a display panel in which light emitting elements are arranged for each pixel and a peripheral circuit that inputs a signal to the panel, and controls light emission of the light emitting elements. There is a light-emitting device that displays an image.

  Development of light-emitting devices using modules in which light-emitting elements are arranged in a matrix has been widely promoted, and EL elements have attracted attention.

  In such a light emitting device, typically two or three TFTs (thin film transistors) are arranged for each pixel. By controlling the on / off of these TFTs, the brightness and light emission / non-light emission of the light emitting elements of each pixel are controlled. Further, a drive circuit for controlling on / off of the TFT of each pixel is provided in the peripheral portion of the pixel portion of the display panel.

  Here, various light-emitting elements in this specification can be used. Examples include OLED elements, inorganic light emitting diode elements, other light emitting diode elements, inorganic EL (Electro Luminescence) elements, other solid light emitting elements, FED elements, and other vacuum light emitting elements. The OLED element has an anode, a cathode, and an organic light emitting layer sandwiched between the anode and cathode.

  In the pixel having the above-described configuration, there are roughly two methods for expressing the gradation of the pixel: an analog method and a digital method. The digital method is more resistant to variations in TFT characteristics than the analog method. It is advantageous. As a digital gradation expression method, there are a time gradation method and an area gradation method.

  The time gray scale method is a method of expressing gray scales by controlling a period during which each pixel of a display device emits light. Assuming that a period for displaying one image is one frame period, one frame period is divided into a plurality of subframe periods. Each pixel is turned on or off for each subframe period, and the display period for each subframe period is changed, and the total period of light emission is controlled by selecting a combination of subframe periods for lighting the pixels. Are expressed.

  The area gradation method is a technique for expressing gradation by controlling the area of the light emitting portion in each pixel of the display device. Specifically, this is a method of expressing the gradation of each pixel by dividing each pixel into sub-pixels and changing the number of sub-pixels that emit light.

  By the way, in a display device that expresses gradation by the time gradation method or the area gradation method as described above, the format of the received video data is converted into video data for time gradation display or video data for area gradation display. And a control circuit for outputting to the display panel is required.

  As a control circuit for such a display device, for example, there is a circuit for a time gray scale display device described in Patent Document 1, which is shown in FIG. The control circuit in FIG. 11 stores a format conversion circuit including a video data format conversion unit 1401 that converts first video data into second video data for time gradation, and stores the second video data that has undergone format conversion. A display control circuit including a first video memory 1402 and a second video memory 1403 for display, a display control unit 1404 for reading data from the first video memory 1402 or the second video memory 1403 and transmitting the data to the display panel; It comprises a memory for writing data and a selection circuit 1405 for selecting a memory for reading.

  FIG. 12 shows a timing chart of a conventional control circuit. The video data input to the video data format conversion unit 1401 is converted into data that conforms to the time gradation method, and data is written and read alternately every frame period using the selection circuit 1405. That is, using the first video memory 1402 and the second video memory 1403, at one point in time, one memory is used for reading video data and the other is used for writing.

The first video data stored in the first video memory 1402 is read out to the display control unit, and at the same time, the second video data corresponding to the next frame period is written into the second video memory 1403 via the selection circuit. Is done.

As described above, the control circuit of the display device in FIG. 11 includes the first video memory 1402 and the second video memory 1403 each capable of storing digital video data for one frame period. The second video data is sampled by alternately using 1402 and the second video memory 1403.
JP 2004-163919 A

  In the conventional method described in Patent Document 1, writing and reading of the second video data are performed for all pixels in the first video memory 1402 and the second video memory 1403 every frame period. If the video data input to the video data format conversion unit 1401 is converted into 6-bit digital time grayscale data, as shown in FIG. 11, 6-bit video data is stored in the first video memory 1402 with n ( n is a natural number) 1st bit video data 1100 of the frame, n (n is a natural number) frame 2nd bit video data 1101, n (n is a natural number) frame 3rd bit video data 1102, n (N is a natural number) 4th bit video data 1103 of the frame, n (n is a natural number) frame 5th bit video data 1104, n (n is a natural number) frame 6th bit video data 1105 The second video memory 1403 stores the video data 1106 of the first bit of the (n + 1) th frame, (n + ) 2nd bit video data 1107 of the frame, 3rd bit video data 1108 of the (n + 1) th frame, 4th bit video data 1109 of the (n + 1) th frame, 5th bit of the (n + 1) th frame The video data 1110 was stored as the 6th bit video data 1111 in the (n + 1) th frame. Therefore, in order to store the data stored in the first video memory 1402 and the second video memory 1403, a memory for at least twice the number of gradation bits of all pixels is required. Therefore, in order to store the data stored in the first video memory 1402 and the second video memory 1403 when the number of pixels in the display panel is doubled and the total number of pixels is increased to a square value. The physical area of the memory required for this has increased by a square value.

  In the configuration described in Patent Document 1, the first video memory 1402 and the first video memory 1402 and the first video memory 1402 in the blanking period until the next frame of video data is written when one frame of video data is written to all pixels of the display panel. 2 Since there is no writing to or reading from the video memory 1403, there is a surplus in the utilization efficiency of the physical area of the memory. However, writing and reading in one memory has a problem that accurate video data accompanying data overwriting cannot be written to pixels.

  Also, simply increasing the physical area of the video data to cope with the increase in the video data written to the display panel is determined in advance by the ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), etc. Among the specifications, there was no choice but to cope by adding a new memory. For this reason, the increase in the number of selection circuits such as selectors and buffers for newly installed memories increases the area occupied by circuit elements on the board and the number of mounting pins, which has been an obstacle to product miniaturization and lower production costs. .

  The present invention has been devised in view of the above-described problems, and it is an object of the present invention to provide a display device control circuit that solves the above-described problems, and a display device / electronic apparatus incorporating the same.

In order to achieve the above object, the present invention has devised the following configuration. That is, in the present invention, among video data to be received, a memory that stores video data of the nth (n is a natural number) frame, a memory that stores video data of the (n + 1) th frame, and an nth frame of (n + 1) ) Prepare a memory to share the video data of the frame.

One of the control circuits of the display device of the present invention includes first to third video data storage means, writing means for writing video data to the first to third video data storage means, and the first From the first video data storage means, the selection means for alternately switching the writing of video data to the video data storage means and the writing of video data to the second video data storage means every frame period Display control means for alternately switching the reading of the video data and the reading of the video data from the second video data storage means for each frame period, the first video data storage means, In the second video data storage means, the writing of the video data and the reading of the video data are performed alternately, and the third video data is stored. The chromatography data storage means, one frame period, in a period other than the receiving video data of one image, a configuration in which video data to be read in the display control unit is written from the writing means.

According to another aspect of the present invention, there is provided a control circuit for a display device, wherein the first to third video data storage means and the first to third video data storage means convert video data into a plurality of bits of video data. Writing means for converting and writing, writing video data to the first video data storage means, and writing video data to the second video data storage means alternately for each frame period Selection means for switching, and display control means for alternately switching reading of video data from the first video data storage means and reading of video data from the second video data storage means for each frame period; In the first video data storage means and the second video data storage means, the video data writing and the video Data is read alternately, and the third video data storage means stores video data read by the display control means during a period other than receiving video data of one image in one frame period. The writing is performed by the writing means.

Another control circuit of a display device of the present invention includes first to sixth video data storage means, writing means for writing video data to the first to sixth video data storage means, Selection means for alternately switching writing of video data to the first video data storage means and writing of video data to the second video data storage means for each frame period; and the first video data Display control means for alternately switching readout of video data from the storage means and readout of video data from the second video data storage means for each frame period, and the first video data The video data is written in the storage means and the second video data storage means, and the third video data storage means and the fourth video data are stored. The video data is written in the data storage means sequentially in one frame period, and the first video data storage means, the second video data storage means, the third video data storage means, and the first video data storage means. 4 video data storage means, the video data writing and the video data reading are alternately carried out, and the fifth video data storage means and the sixth video data storage means have one frame period. Of these, the video data read by the display control means is written by the writing means during a period other than when video data of one image is received.

According to another aspect of the present invention, there is provided a display circuit control circuit comprising: first to sixth video data storage means; and video data comprising a plurality of bits in the first to sixth video data storage means. Writing means for converting and writing, writing video data to the first video data storage means, and writing video data to the second video data storage means alternately for each frame period Selection means for switching, and display control means for alternately switching reading of video data from the first video data storage means and reading of video data from the second video data storage means for each frame period; And writing the video data in the first video data storage means and the second video data storage means, and The video data is written in the three video data storage means and the fourth video data storage means sequentially in one frame period, and the first video data storage means and the second video data storage means In the third video data storage means and the fourth video data storage means, the writing of the video data and the reading of the video data are alternately performed, and the fifth video data storage means and the sixth video data storage means In this video data storage means, video data read by the display control means is written by the writing means during a period other than receiving video data of one image in one frame period.

  Further, the present invention may have a configuration including the control circuit of the display device of the present invention and a display panel provided with a light emitting element for each pixel.

  In the present invention, the light emitting element may be an EL element.

  According to the present invention, in the control circuit of the display device, video data of an arbitrary bit of the nth frame and the (n + 1) th frame can be stored in a common memory, and read from and written to the memory. Therefore, it becomes possible to efficiently use the physical area of the memory as compared with a case where a necessary memory is simply added. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

Further, according to the present invention, it is not necessary to select video data of arbitrary bits of the nth frame and the (n + 1) th frame by a selection circuit such as a selector in the control circuit of the display device. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
FIG. 1 shows an outline of a configuration example of a control circuit of a display device according to the present invention. This control circuit includes a video data format conversion unit 101, a first video data storage unit 102, a second video data storage unit 103, a third video data storage unit 104, a display control unit 105, a display And a panel 106. When the video data format conversion unit 101 receives the video data, the video data that enables gradation expression in the pixels of the display panel, for example, video data for time gradation display in a time gradation display device. Convert format to. The video data format conversion unit 101 writes video data for time gradation display to the first video data storage unit 102 or the second video data storage unit 103 as writing means via the selectors 107 and 108 as selection means. Write data. Further, the video data format conversion unit 101 writes video data for time gradation display to the third video data storage unit 104 as writing means.

Instead of the selector 107 and the selector 108, other connection control means such as an analog switch or a tristate buffer may be used.

A display control unit 105 serving as a display control unit reads video data from either the first video data storage unit 102 or the second video data storage unit 103 via the selector 107 and the selector 108 and outputs the video data to the display control unit. To do. The display control unit 105 transmits the video data selected by the selector 108 to the display panel 106 in synchronization with the display timing.

  In the present embodiment, an example in which video data input to the video data format conversion unit 101 is converted into 6-bit digital time grayscale data will be described, which also serves as a comparison with the conventional example of FIG. Of course, if the video data input to the format conversion unit is format-converted to the time gradation method or the area gradation method, it is not limited to 6 bits.

  A difference from the prior art is that a third video data storage unit 104 is provided. In the address area of the third video data storage unit 104, the i-th bit in the nth frame (n is a natural number) and the (n + 1) th frame (i is 1 <i <6; provided that the video data is converted into 6 bits) Video data) is stored. That is, the third video data storage unit 104 stores the video data storage units of the nth frame and the (n + 1) th frame in common.

  Next, the circuit configuration will be described with reference to FIG. First, video data is input to the video data format conversion unit 101. The video data format conversion unit 101 performs format conversion to video data that can express gradation, for example, video data for time gradation display in the case of a time gradation display device, and converts the data of each gradation bit. The data is written in the first video data storage unit 102, the second video data storage unit 103, or the third video data storage unit 104. At the same time, the display control unit 105 reads the video data written in the first video data storage unit 102, the second video data storage unit 103, or the third video data storage unit 103 and supplies the video data to the display panel 106. Is output.

  Here, the area of the memory in which the format-converted video data is written will be described. The first video data storage unit 102 includes a memory region 111, a memory region 112, a memory region 113, and a memory region 114. Similarly, the second video data storage unit 103 includes a memory region 115, a memory region 116, and a memory region. An area 117 and a memory area 118 are included. The third video data storage unit 104 includes a memory area 119 and a memory area 120. The first video data storage unit 102 stores the nth frame of video data, and the second video data storage unit 103 stores the (n + 1) th frame of video data. The third video data storage unit 104 is a video of the nth frame in a period other than receiving video data of one image in one frame period, that is, a period in which video data is output to the display panel and no image is received. Data and video data of the (n + 1) th frame are stored.

  Next, a timing chart of video data will be described with reference to FIG.

In FIG. 2, the first bit data 200, the second bit data 201, the third bit data 202, the fourth bit data 203, the fifth bit data 204 of the format-converted first frame video data. , 6th bit data 205 is output from the video data format conversion unit 101 during a period other than the blanking period of the first frame and stored in the video data storage unit. Similarly, the first bit data 206, the second bit data 207, the third bit data 208, the fourth bit data 209, the fifth bit data 210, 6 of the video data of the second frame whose format has been converted. The bit data 211 is output from the video data format conversion unit 101 during a period other than the period 219 of the second frame and stored in the video data storage unit. Similarly, the first bit data 212, the second bit data 213, the third bit data 214, the fourth bit data 215, the fifth bit data 216 of the third frame of video data that have been format-converted, The 6-bit data 217 is output from the video data format conversion unit 101 during a period other than the blanking period of the third frame and stored in the video data storage unit.

At this time, when attention is paid to the third bit data and the fourth bit data of the video data among the signals output from the video data storage unit to the display panel via the display control unit, the third bit data of the first frame 202, the data 203 of the fourth bit is being written into the video data storage unit in a period 218, and a data reading end period to the display control unit is in a period 219.

Similarly, the third bit data 208 and the fourth bit data 209 in the second frame are being written into the video data storage unit in the period 220, and the data read end period to the display control unit in the period 221 Become. In addition, the third bit data 214 and the fourth bit data 215 in the third frame are being written to the video data storage unit in the period 222.

The third bit data 202 and the fourth bit data 203 in the first frame are supplied to the display panel via the display control unit in the period 219 and are not supplied to the display panel in the period 220. Similarly, the third bit data 208 and the fourth bit data 209 in the second frame are supplied to the display panel via the display control unit in the period 221 and are not supplied to the display panel in the period 222. The third bit data 202 and the fourth bit data 203 do not need to store the n frame gradation data and the (n + 1) frame gradation data in separate memories in the periods 220 and 222, respectively. The third bit data and the fourth bit data can be assigned to the third bit and fourth bit write areas using the memory areas 119 and 120 of the third video data storage unit 104.

In this embodiment, for explanation, the third bit data 202 and the fourth bit data 203 are included in one frame period (a period of one cycle of SYNC (vertical synchronization signal) in FIG. 2). The example in which the video data supplied to the display panel via the display control unit in the blanking period other than the display period is stored in the third video data storage unit 104 has been described. However, the present invention is not limited to this, and any video data that is supplied to the display panel via the display control unit in a period other than the display period may be the nth frame (n is a natural number) and the (n + 1) th frame. Even the video data can be stored in the third video data storage unit 104 as the i-th video data (i is 1 <i <m; provided that the video data is converted into m bits).

FIG. 3 illustrates a flow of data written to the first video data storage unit 102, the second video data storage unit 103, and the third video data storage unit 104. In FIG. 3, the video data format conversion unit 101 and the display control unit 105 in FIG. 1 are collectively abbreviated as a controller.

3A represents a period 218 and a period 219 in the timing chart. The third bit data storage unit 104 stores the third bit data 202 and the fourth bit data 203 supplied to the display panel during a period in which the second frame of video data is not transmitted, that is, a blanking period. Further, the first bit data 200, the second bit data 201, the fifth bit data 204, and the sixth bit data 205, which are the remaining video data, are stored in the first video data storage unit 102.

The state of FIG. 3B represents a period 220 and a period 221 in the timing chart. The format-converted video data is read from the first video data storage unit 102 and the third video data storage unit 104 and output to the display panel via the display control unit. Thereafter, the third video data storage unit 104 that receives the video data of the second frame receives the third bit to be supplied to the display panel during a period in which the video data of the third frame is not transmitted, that is, a blanking period. Data 208 and the fourth bit data 209 are stored in the third video data storage unit. The remaining gradation data is stored in the first bit data 206, the second bit data 207, the fifth bit data 210, and the sixth bit data 211 of the second video data storage unit.

The state in FIG. 3C represents a period 222 in the timing chart. The format-converted video data is read from the second video data storage unit 103 and the third video data storage unit 104 and output to the display panel via the display control unit. After that, the third frame of video data is received, and the third video data storage unit 104 receives the third frame of data to be supplied to the display panel during the period when the video data of the next frame is not transmitted, that is, during the blanking period. 214, the fourth bit data 215 is stored in the third video data storage unit 104. The remaining gradation data is stored in the first bit data 212, the second bit data 213, the fifth bit data 216, and the sixth bit data 217 in the first video data storage unit 102.

As described with reference to FIGS. 1 to 3, in the third video data storage unit 104, the present invention can arbitrarily set the third video data storage unit 104 via a display control unit during a blanking period other than the display period in one frame period. Can be stored, and data of an arbitrary gradation bit in the next frame can be stored. That is, the third video data storage unit 104 can hold data of arbitrary gradation bits in the nth frame (n is a natural number) and the (n + 1) th frame. Therefore, the third video data storage unit 104 can input / output data without using a selection circuit such as a selector or a tristate buffer.

In the conventional example, separate storage units are provided for writing and reading video data. For example, in the case of 6-bit video data, it is necessary to secure a storage unit for reading and writing for 12 bits. In the present embodiment of the present invention, reading and writing of arbitrary gradation bit data in the nth frame (n is a natural number) and the (n + 1) th frame can be performed in the same storage unit. In other words, in this embodiment, although the third video data storage unit is provided more than in the conventional example, it is only necessary to provide 10 bits for the storage unit for reading and writing in total. Can be reduced.

  According to the present invention, in the control circuit of the display device, video data of an arbitrary bit of the nth frame and the (n + 1) th frame can be stored in a common memory, and read from and written to the memory. Therefore, it becomes possible to efficiently use the physical area of the memory as compared with a case where a necessary memory is simply added. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

Further, according to the present invention, it is not necessary to select video data of arbitrary bits of the nth frame and the (n + 1) th frame by a selection circuit such as a selector in the control circuit of the display device. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.
(Embodiment 2)

  An embodiment of the present invention will be described in a different form from the first embodiment.

  FIG. 4 shows an outline of a configuration example of the control circuit of the display device according to the present invention. The control circuit includes a video data format conversion unit 401, a first video data storage unit 402, a second video data storage unit 403, a third video data storage unit 404, and a fourth video data storage unit. 405, a fifth video data storage unit 406, a sixth video data storage unit 407, a display control unit 408, and a display panel 409. When the video data format conversion unit 401 receives the video data, the video data that enables gradation expression in the pixels of the display panel, for example, video data for time gradation display in the case of a time gradation display device. Convert format to. The video data format conversion unit 401 serves as a writing means to the first video data storage unit 402 and the second video data storage unit 403, or the third video data storage unit 404 and the fourth video data storage unit 405. Writing is performed at the timing of the memory selection signal via the selector 410 and the selector 411 which are selection means. In addition, the video data format conversion unit 401 writes video data for time gradation display to the fifth video data storage unit 406 and the sixth video data storage unit 407 as writing means.

Instead of the selector 410 and the selector 411, other connection control means such as an analog switch or a tristate buffer may be used.

The display control unit 408 serving as a display control unit is one of the first video data storage unit 402 and the second video data storage unit 403, or the third video data storage unit 404 and the fourth video data storage unit 405. The video data is read out via the selector 411 and output to the display control unit. The display control unit 408 transmits the video data selected by the selector 411 to the display panel 409 in synchronization with the display timing.

  In the present embodiment, an example in which the video data input to the video data format conversion unit 401 is converted into 6-bit digital time grayscale data will be described, which also serves as a comparison with the conventional example of FIG. Of course, if the video data input to the format conversion unit is format-converted to the time gradation method or the area gradation method, it is not limited to 6 bits.

  A difference from the prior art is that, in particular, a fifth video data storage unit 406 and a sixth video data storage unit 407 are provided. In the address areas of the fifth video data storage unit 406 and the sixth video data storage unit 407, the n-th frame (n is a natural number) and the i-th bit (i is 1 <i <6; However, the video data (when the format is converted to 6 bits) is stored. That is, the fifth video data storage unit 406 and the sixth video data storage unit 407 store the video data storage units of the nth frame and the (n + 1) th frame in common.

  Next, a circuit configuration will be described with reference to FIG. First, video data is input to the video data format conversion unit 401. The video data format conversion unit 401 converts the format into video data that can express gradation, for example, video data for time gradation display in the case of a time gradation display device, and converts the data of each gradation bit. First video data storage unit 402, second video data storage unit 403, third video data storage unit 404, fourth video data storage unit 405, fifth video data storage unit 406, or sixth It is written in the video data storage unit 407. At the same time, the first video data storage unit 402, the second video data storage unit 403, the third video data storage unit 404, the fourth video data storage unit 405, the fifth video data storage unit 406, or the first 6, the display control unit 408 reads the video data written in the video data storage unit 407 and outputs the video data to the display panel 409.

  Here, the area of the memory in which the format-converted video data is written will be described. The first video data storage unit 402 includes a memory area 421, a memory area 422, a memory area 423, a memory area 424, and a memory area 425. Similarly, the second video data storage unit 403 includes a memory area 426, a memory area, and a memory area 426. An area 427 and a memory area 428 are included. The third video data storage unit 404 includes a memory area 429, a memory area 430, a memory area 431, a memory area 432, and a memory area 433. The fourth video data storage unit 405 includes a memory area 434, a memory area 435, and a memory area 436. The fifth video data storage unit 406 has a memory area 437. The sixth video data storage unit 407 includes a memory area 438, a memory area 439, and a memory area 440. The first video data storage unit 402 stores video data for the first half period of the nth frame, and the second video data storage unit 403 stores video data for the second half period of the nth frame. The third video data storage unit 404 stores the video data of the first half period of the (n + 1) frame, and the fourth video data storage unit 405 stores the video data of the second half period of the (n + 1) frame. Is stored. The fifth video data storage unit 406 and the sixth video data storage unit 407 have a period other than receiving video data of one image in one frame period, that is, video data is output to the display panel and an image is received. The video data of the nth frame and the video data of the (n + 1) th frame are stored.

  Next, a timing chart of video data will be described with reference to FIG.

In FIG. 5, the first bit data 500, the second bit data 501, the third bit data 502, the fourth bit data 503, and the fifth bit of the video data 550 in the first half period of the first frame after the format conversion. The eye data 504 and the 6th bit data 505 are output from the video data format conversion unit 401 in the first half period other than the blanking period 549 of the first frame and stored in the video data storage unit. Also, the first bit data 506, the second bit data 507, the third bit data 508, the fourth bit data 509, the fifth bit data of the video data 551 in the second half period of the first frame after the format conversion. 510 and 6th bit data 511 are output from the video data format conversion unit 401 in the latter half period other than the blanking period 549 of the first frame and stored in the video data storage unit. Similarly, the first bit data 512, the second bit data 513, the third bit data 514, the fourth bit data 515, the fifth bit of the video data 553 in the first half period of the second frame after the format conversion. Data 516 and 6th bit data 517 are output from the video data format conversion unit 401 in the first half period other than the blanking period 552 of the second frame and stored in the video data storage unit. Also, the first bit data 518, the second bit data 519, the third bit data 520, the fourth bit data 521, and the fifth bit data of the video data 554 in the second half of the second frame after the format conversion. The data 523 of the 522th and 6th bits are output from the video data format conversion unit 401 in the latter half period other than the blanking period 552 of the second frame and stored in the video data storage unit. Similarly, the first bit data 524, the second bit data 525, the third bit data 526, the fourth bit data 527, the fifth bit data 528 of the video data in the first half period of the third frame after the format conversion. , 6th bit data 529 is output from the video data format conversion unit 401 in the first half period other than the blanking period 555 of the third frame and stored in the video data storage unit. Also, the first bit data 530, the second bit data 531, the third bit data 532, the fourth bit data 533, the fifth bit data 534 of the video data in the second half period of the third frame after the format conversion. , The sixth bit data 535 is output from the video data format conversion unit 401 in the latter half period other than the blanking period 555 of the third frame and stored in the video data storage unit.

Note that “the video data in the first half period (or second half period) of the frame” in this embodiment means that the video data used in the first half period and the second half period is not interpreted as the same data amount. The distribution may be varied depending on the memory area of the data storage unit. Therefore, it is preferable that the specification of the video data storage unit to be used can be changed by changing the distribution of the division of the video data.

At this time, out of signals output from the video data storage unit to the display panel via the display control unit, the third bit data 502 in the first half period of the first frame of the video data, and the third bit in the second half period of the first frame. Data 508, the fourth bit data 509 in the second half period of the first frame, and the fifth bit data 510 in the second half period of the first frame. Here, the data 502 of the first half period in the third bit of the first frame is being written into the video data storage section in the period 538, and becomes a data reading end period to the display control section in the period 539. The third bit data 508 in the second half period of the first frame, the fourth bit data 509 in the second half period of the first frame, and the fifth bit data 510 in the second half period of the first frame are stored in the video data storage unit in the period 544 Data writing is in progress, and the period for reading data to the display control unit is reached in a period 545.

Similarly, the data 514 of the first half period in the third bit of the second frame is being written into the video data storage section in the period 540, and becomes a data read end period to the display control section in the period 541. The third bit data 520 in the second half period of the second frame, the fourth bit data 521 in the second half period of the second frame, and the fifth bit data 522 in the second half period of the second frame are stored in the video data storage unit in the period 546 Data writing is in progress, and a period for reading data to the display control unit is reached in a period 547.

In this embodiment, for the sake of explanation, the third bit data 502 in the first half period of the first frame, the third bit data 508 in the second half period of the first frame, one frame period (SYNC in FIG. 5). A fifth video data storage unit 406 for video data supplied to the display panel via the display control unit during a blanking period other than the display period in (period of one cycle of (vertical synchronization signal)), The example stored in the sixth video data storage unit 407 has been shown. However, the present invention is not limited to this, and any video data that is supplied to the display panel via the display control unit in a period other than the display period may be the nth frame (n is a natural number) and the (n + 1) th frame. Even the video data is stored in the fifth video data storage unit 406 and the sixth video data storage unit 407 in the i-th bit (i is 1 <i <m; provided that the video data is converted to m-bit format). It can be stored as video data.

FIG. 6 shows a first video data storage unit 402, a second video data storage unit 403, a third video data storage unit 404, a fourth video data storage unit 405, and a fifth video data storage. The flow of data written to the unit 406 and the sixth video data storage unit 407 will be described. In FIG. 6, the video data format conversion unit 401 and the display control unit 408 in FIG. 4 are also abbreviated as a controller.

The state of FIG. 6A represents a period 538 in the timing chart. In a period in which video data of two frames is not transmitted, that is, in a blanking period, data of the third bit data 502 in the first half of the first frame supplied to the display panel is stored in the fifth video data storage unit 406. To do. The remaining video data is the first bit data 500 in the first half period of the first frame, the second bit data 501 in the first half period of the first frame, and the fourth bit data 503 and 1 in the first half period of the first frame. The fifth bit data 504 in the first half period of the frame and the sixth bit data 505 in the first half period of the frame are stored in the first video data storage unit 402.

Further, in the first half period of the second frame, the third bit data 508 in the second half period of the first frame supplied to the display panel, the fourth bit data 509 in the second half period of the first frame, and the second half period of the first frame. The fifth bit data 510 is stored in the sixth video data storage unit 407. Further, the remaining video data is the first bit data 506 in the second half period of the first frame, the second bit data 507 in the second half period of the first frame, and the sixth bit data 511 in the second half period of the first frame. Stored in the second video data storage unit 403.

The state of FIG. 6B represents a blanking period 552 in the timing chart. The format-converted third-bit data 502 in the first half period of the first frame and the third-bit data 508 in the second half period of the first frame are read from the fifth video data storage unit 406 and the sixth video data storage unit 407. And output to the display panel via the display control unit.

The state in FIG. 6C represents a period 540 in the timing chart. 4th bit data 503 in the first half period of the first frame after the format conversion, 4th bit data 509 in the second half period of the first frame, 5th bit data 504 in the first half period of the first frame, and the second half of the first frame Data 510 of the fifth bit in the period is read from the first video data storage unit 402 and the sixth video data storage unit 407, and output to the display panel via the display control unit. Further, in the fifth video data storage unit 406, the third bit data 514 in the first half period of the second frame supplied to the display panel in the period in which the video data of the three frame period is not transmitted, that is, in the blanking period. Is stored in the third video data storage unit 406. Further, the first bit data 512 in the first half period of the second frame, which is the remaining gradation data, the second bit data 513 in the first half period of the second frame, the fourth bit data 515 in the first half period of the second frame, The fifth bit data 516 in the first half period of the second frame and the sixth bit data 517 in the first half period of the second frame are stored in the third video data storage unit 404.

The state in FIG. 6D represents a period 541 in the timing chart. Format-converted first bit data 500 in the first half period of the first frame, first bit data 506 in the second half period of the first frame, second bit data 501 in the first half period of the first frame, and second half of the first frame The second bit data 507 in the period, the sixth bit data 505 in the first half period of the first frame, and the sixth bit data 511 in the second half period of the first frame are stored in the first video data storage unit 402 and the second video. The data is read from the data storage unit 403 and output to the display panel via the display control unit. Further, the sixth video data storage unit 407 stores the third bit data 520 in the second half period of the second frame supplied to the display panel in the first half period of the third frame period, and the fourth bit in the second half period of the second frame. Data 521 and the fifth bit data 522 in the second half of the second frame are stored in the fifth video data storage unit 406. The remaining gray-scale data is the first bit data 618 in the second half of the second frame, the second bit data 619 in the second half of the second frame, and the sixth bit data 620 in the second half of the second frame. And stored in the third video data storage unit 404.

As described with reference to FIGS. 4 to 6, in the present invention, the fifth video data storage unit 406 and the sixth video data storage unit 407 have a blanking period that is a period other than the display period in one frame period. In the first half of the second frame, data of arbitrary gradation bits can be output via the display control unit, and data of arbitrary gradation bits in the next frame can be stored. That is, the fifth video data storage unit 406 and the sixth video data storage unit 407 can hold data of arbitrary gradation bits in the nth frame (n is a natural number) and the (n + 1) th frame. . Therefore, the fifth video data storage unit 406 and the sixth video data storage unit 407 can output data without using a selection circuit such as a selector or a tristate buffer.

In the conventional example, separate storage units are provided for writing and reading video data. For example, if 6-bit video data is divided into a first half period and a second half period, it is necessary to secure 24 storage units as storage units for reading and writing. In the present embodiment of the present invention, reading and writing of arbitrary gradation bit data in the nth frame (n is a natural number) and the (n + 1) th frame can be performed in the same storage unit. That is, in the present embodiment, although the fifth video data storage unit 406 and the sixth video data storage unit 407 are provided more than in the conventional example, a total of 20 storage units for reading and writing are provided. Since it is only necessary to provide a storage unit, the storage units for four locations can be reduced.

  According to the present invention, in the control circuit of the display device, video data of an arbitrary bit of the nth frame and the (n + 1) th frame can be stored in a common memory, and read from and written to the memory. Therefore, it becomes possible to efficiently use the physical area of the memory as compared with a case where a necessary memory is simply added. Therefore, it is possible to reduce the number of mounting pins, simplify the structure, save circuit space, and increase the physical utilization efficiency of the memory. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

Further, according to the present invention, it is not necessary to select video data of arbitrary bits of the nth frame and the (n + 1) th frame by a selection circuit such as a selector in the control circuit of the display device. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.
(Embodiment 3)

  In this embodiment mode, an example of a display device using a display device control circuit and an EL element for each pixel is shown in FIG.

  The display device includes a control circuit 701, a source signal line driver circuit 702, gate signal line driver circuits 703 and 704, a display unit 705, a memory 706, an FPC 707, and a connector 708. Each circuit of the display device is formed on or attached to the panel 700.

  The operation will be described. Data and control signals sent from the FPC 707 through the connector 708 are input to the control circuit 701, and the data is rearranged for output in the memory 706 (storage unit) and sent to the control circuit 701 again. The control circuit 701 sends data and signals used for display to the source signal line driver circuit 702 and the gate signal line driver circuits 703 and 704, and performs display on the display portion 705 using EL elements.

  Known source signal line driver circuits 702 and gate signal line driver circuits 703 and 704 can be used. One gate signal line driver circuit may be provided depending on the circuit configuration.

  In addition, this embodiment mode can be freely combined with any description in other embodiment modes in this specification. That is, by applying the control circuit of the display device to the control circuit 701 of this embodiment, video data of an arbitrary bit of the nth frame and the (n + 1) th frame is stored in a common memory and read from the memory. And write. Therefore, it becomes possible to efficiently use the physical area of the memory as compared with a case where a necessary memory is simply added. Therefore, it is possible to reduce the number of mounting pins, simplify the structure, save circuit space, and increase the physical utilization efficiency of the memory. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

Further, according to the present invention, it is not necessary to select video data of arbitrary bits of the nth frame and the (n + 1) th frame by a selection circuit such as a selector in the control circuit of the display device. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.
(Embodiment 4)

  In this embodiment, FIG. 8 illustrates an example of a display device that uses a control circuit of a display device and uses an EL element for each pixel, which is different from the other embodiments.

  The display device includes a connector 908 including a control circuit 901, a source signal line driver circuit 902, gate signal line driver circuits 903 and 904, a display portion 905, a memory 906, and an FPC 907. Each circuit of the display device is formed on or attached to the panel 900.

  The operation will be described. The data and control signal sent from the FPC 907 through the connector 908 are input to the control circuit 901. Then, the data is returned to the memory 906 in the FPC 907, the data is rearranged for output, and sent to the control circuit 901 again. The control circuit 901 sends data and signals used for display to the source signal line driver circuit 902 and the gate signal line driver circuits 903 and 904, and performs display on the display portion 905 using EL elements.

  The difference from Embodiment 3 is that the memory 906 is incorporated in the FPC 907. This can reduce the size of the display device.

  As in Embodiment Mode 3, well-known source signal line driver circuits 902 and gate signal line driver circuits 903 and 904 can be used. Further, one gate signal line driver circuit may be provided depending on the circuit configuration.

  In addition, this embodiment mode can be freely combined with any description in other embodiment modes in this specification. That is, by applying the control circuit of the display device to the control circuit 901 of this embodiment, video data of an arbitrary bit of the nth frame and the (n + 1) th frame is stored in a common memory and read from the memory. And write. Therefore, it becomes possible to efficiently use the physical area of the memory as compared with a case where a necessary memory is simply added. Therefore, it is possible to reduce the number of mounting pins, simplify the structure, save circuit space, and increase the physical utilization efficiency of the memory. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

Further, according to the present invention, it is not necessary to select video data of arbitrary bits of the nth frame and the (n + 1) th frame by a selection circuit such as a selector in the control circuit of the display device. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.
(Embodiment 5)

  In this embodiment mode, a control circuit that outputs to a display using an EL element having a configuration different from that of the other embodiment of the display apparatus using an EL element for each pixel is used. An example of the configuration will be described with reference to FIG.

  The time gradation display inevitably has a higher operating frequency than the analog display. In general, in order to obtain high image quality, it is necessary to suppress the occurrence of pseudo contours. For this purpose, it is necessary to increase the number of subframes to 10 or more. Therefore, the operating frequency must be increased by 10 times or more.

  In order to drive at such an operating frequency, the SRAM used for the storage unit to be used also needs to operate at high speed, and it is necessary to use a high-speed SRAM-IC.

  However, high-speed SRAMs consume a large amount of power when held, and are not particularly suitable for mobile devices. Further, in order to use a low power consumption SRAM, it is necessary to further reduce the frequency.

  As shown in FIG. 9, before the digital video signal is written into the first video data storage unit 1703, the second video data storage unit 1704, and the third video data storage unit 1708, the serial-parallel conversion circuit 1702 is provided. The digital video signal is converted from serial to parallel, and then written to the display 1705 via the switches 1706 and 1707.

  By taking such a measure, parallel reading can be performed at a low frequency even during reading, so that a low power consumption SRAM used for the storage unit can be used at a low frequency and the power of the mobile device can be reduced.

  In addition, this embodiment mode can be freely combined with any description in other embodiment modes in this specification. That is, by applying the control circuit of the display device to the control circuit for controlling the first video data storage unit 1703, the second video data storage unit 1704, and the third video data storage unit 1708 of this embodiment, Video data of an arbitrary bit of the nth frame and the (n + 1) th frame can be stored in a common memory, and can be read from and written to the memory. Therefore, it becomes possible to efficiently use the physical area of the memory as compared with a case where a necessary memory is simply added. Therefore, it is possible to reduce the number of mounting pins, simplify the structure, save circuit space, and increase the physical utilization efficiency of the memory. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

Further, according to the present invention, it is not necessary to select video data of arbitrary bits of the nth frame and the (n + 1) th frame by a selection circuit such as a selector in the control circuit of the display device. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

  As an electronic device using the present invention, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, a portable information terminal (mobile computer, portable) An image playback apparatus (specifically, a digital versatile disc (DVD)) such as a telephone, a portable game machine, or an electronic book), and an apparatus including a display that can display the image. ) And the like. Specific examples of these electronic devices are shown in FIGS.

  FIG. 10A illustrates a liquid crystal display or an OLED display, which includes a housing 1001, a support base 1002, a display portion 1003, and the like. The present invention can be applied to a driver circuit of a display device including the display portion 1003.

  FIG. 10B illustrates a video camera, which includes a main body 1011, a display portion 1012, an audio input 1013, operation switches 1014, a battery 1015, an image receiving portion 1016, and the like. The present invention can be applied to a driver circuit of a display device having the display portion 1017.

  FIG. 10C illustrates a laptop personal computer, which includes a main body 1021, a housing 1022, a display portion 1023, a keyboard 1024, and the like. The present invention can be applied to a driver circuit of a display device having the display portion 1023.

  FIG. 10D illustrates a portable information terminal which includes a main body 1031, a stylus 1032, a display portion 1033, operation buttons 1034, an external interface 1035, and the like. The present invention can be applied to a driver circuit of a display device having the display portion 1033.

  FIG. 10E illustrates a sound reproducing device, specifically, an in-vehicle audio device, which includes a main body 1041, a display portion 1042, operation switches 1043 and 1044, and the like. The present invention can be applied to a driver circuit of a display device having the display portion 1042. In this example, the on-vehicle audio device is taken as an example, but it may be used for a portable or home audio device.

  FIG. 10F illustrates a digital camera, which includes a main body 1051, a display portion (A) 1052, an eyepiece portion 1053, operation switches 1054, a display portion (B) 1055, a battery 1056, and the like. The present invention can be applied to a driver circuit of a display device including the display portion (A) 1052 and the display portion (B) 1055.

  FIG. 10G illustrates a mobile phone, which includes a main body 1061, an audio output portion 1062, an audio input portion 1063, a display portion 1064, operation switches 1065, an antenna 1066, and the like. The present invention can be applied to a driver circuit of a display device having the display portion 1064.

  Display devices used in these electronic devices can use not only glass substrates but also heat-resistant plastic substrates. Thereby, further weight reduction can be achieved.

  It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

  In addition, this embodiment mode can be freely combined with any description in other embodiment modes in this specification. For this reason, in the control circuit of the display device, video data of an arbitrary bit of the nth frame and the (n + 1) th frame can be stored in a common memory and read from and written to the memory. Therefore, it becomes possible to efficiently use the physical area of the memory as compared with a case where a necessary memory is simply added. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

Further, according to the present invention, it is not necessary to select video data of arbitrary bits of the nth frame and the (n + 1) th frame by a selection circuit such as a selector in the control circuit of the display device. Therefore, the number of mounting pins can be reduced, the structure can be simplified, the circuit space can be saved, and the physical utilization efficiency of the memory can be increased. As a result, it is possible to realize a reduction in size, a reduction in production cost, an improvement in reliability, and a reduction in power consumption of a display device and an electronic device including the control circuit of the present invention.

1 is a block diagram illustrating a display device control circuit using the present invention. 4 is a time chart showing the operation of the display device control circuit using the present invention. The block diagram which shows the flow of operation | movement of the display apparatus control circuit using this invention. The block diagram which shows embodiment using this invention. The time chart which shows embodiment using this invention. The block diagram which shows embodiment using this invention. FIG. 11 illustrates an example of a display device using the present invention. FIG. 11 illustrates an example of a display device using the present invention. FIG. 11 illustrates an example of a display device using the present invention. FIG. 14 illustrates an example of an electronic device using the invention. The figure which shows the block diagram of a prior art example. The figure which shows the time chart of the operation | movement of a prior art example.

Explanation of symbols

101 Video Data Format Conversion Unit 102 Video Data Storage Unit 103 Video Data Storage Unit 104 Video Data Storage Unit 105 Display Control Unit 106 Display Panel 107 Selector 108 Selector 111 Memory Area 112 Memory Area 113 Memory Area 114 Memory Area 115 Memory Area 116 Memory Area 117 Memory area 118 Memory area 119 Memory area 120 Memory area 200 Data 201 Data 202 Data 203 Data 204 Data 205 Data 206 Data 207 Data 208 Data 209 Data 210 Data 211 Data 212 Data 213 Data 214 Data 215 Data 216 Data 217 Data 218 Period 219 period 219 period 220 period 221 period 222 period 401 video data format conversion Unit 402 video data storage unit 403 video data storage unit 404 video data storage unit 405 video data storage unit 406 video data storage unit 407 video data storage unit 408 display control unit 409 display panel 410 selector 411 selector 412 display control unit 421 memory area 422 Memory area 423 Memory area 424 Memory area 425 Memory area 426 Memory area 427 Memory area 428 Memory area 429 Memory area 430 Memory area 431 Memory area 432 Memory area 433 Memory area 434 Memory area 435 Memory area 436 Memory area 437 Memory area 438 Memory area 439 Memory area 440 Memory area 500 Data 501 Data 502 Data 503 Data 504 Data 505 Data 506 Data 507 Data 5 8 Data 509 Data 510 Data 511 Data 512 Data 513 Data 514 Data 515 Data 516 Data 517 Data 518 Data 519 Data 520 Data 521 Data 522 Data 523 Data 524 Data 525 Data 526 Data 527 Data 528 Data 529 Data 530 Data 531 Data 532 Data 533 data 534 data 535 data 538 period 539 period 540 period 541 period 542 period 544 period 545 period 546 period 547 period 549 retrace period 550 video data 551 video data 552 retrace period 553 video data 554 video data 555 retrace period 556 video Data 557 Video data 618 Data 619 Data 620 Data 700 Panel 701 Control Road 702 the source signal line driver circuit 703 the gate signal line driver circuit 705 display unit 706 memory 706 Memory 707 FPC
708 Connector 900 Panel 901 Control circuit 902 Source signal line drive circuit 903 Gate signal line drive circuit 905 Display unit 906 Memory 907 FPC
908 Connector 1001 Case 1002 Support base 1003 Display unit 1011 Main body 1012 Display unit 1013 Audio input 1014 Operation switch 1015 Battery 1016 Image receiving unit 1017 Display unit 1021 Main body 1022 Case 1023 Display unit 1024 Keyboard 1031 Main body 1032 Stylus 1033 Display unit 1034 Operation button 1035 External interface 1041 Main unit 1042 Display unit 1043 Operation switch 1051 Main unit 1052 Display unit (A)
1053 Eyepiece 1054 Operation switch 1055 Display (B)
1056 Battery 1061 Main unit 1062 Audio output unit 1063 Audio input unit 1064 Display unit 1065 Operation switch 1066 Antenna 1100 Video data 1101 Video data 1102 Video data 1103 Video data 1104 Video data 1105 Video data 1106 Video data 1107 Video data 1108 Video data 1109 Video data 1110 Video data 1111 Video data 1401 Video data format conversion unit 1402 Video memory 1403 Video memory 1404 Display control unit 1405 Selection circuit 1702 Serial-parallel conversion circuit 1703 Video data storage unit 1704 Video data storage unit 1705 Display 1706 Switch 1708 Video data storage unit

Claims (8)

First to third video data storage means;
Writing means for writing video data to the first to third video data storage means;
Selection means for alternately switching writing of video data to the first video data storage means and writing of video data to the second video data storage means for each frame period;
Display control means for alternately switching readout of video data from the first video data storage means and readout of video data from the second video data storage means for each frame period;
In the first video data storage means and the second video data storage means, the writing of the video data and the reading of the video data are performed alternately,
In the third video data storage means, video data read by the display control means is written by the writing means in a period other than receiving video data of one image in one frame period. A display circuit control circuit. First to third video data storage means;
Writing means for converting video data into a plurality of bits and writing the video data in the first to third video data storage means;
Selection means for alternately switching writing of video data to the first video data storage means and writing of video data to the second video data storage means for each frame period;
Display control means for alternately switching readout of video data from the first video data storage means and readout of video data from the second video data storage means for each frame period;
In the first video data storage means and the second video data storage means, the writing of the video data and the reading of the video data are performed alternately,
In the third video data storage means, video data read by the display control means is written by the writing means during a period other than receiving video data of one image in one frame period. A display circuit control circuit. First to sixth video data storage means;
Writing means for writing video data to the first to sixth video data storage means;
Writing video data to the first video data storage means and the second video data storage means, and writing video data to the third video data storage means and the fourth video data storage means Selecting means for alternately switching every frame period;
Reading video data from the first video data storage means and the second video data storage means, and reading video data from the third video data storage means and the fourth video data storage means Display control means for alternately switching every frame period,
Writing the video data in the first video data storage means and the second video data storage means, and writing the video data in the third video data storage means and the fourth video data storage means, Each is performed sequentially in one frame period,
In the first video data storage means and the second video data storage means, and in the third video data storage means and the fourth video data storage means, the writing of the video data and the reading of the video data Are performed alternately
In the fifth video data storage means and the sixth video data storage means, video data read out by the display control means in a period other than receiving video data of one image in one frame period. The display circuit control circuit is written by the writing means. First to sixth video data storage means;
Writing means for converting video data into a plurality of bits and writing the video data in the first to sixth video data storage means;
Writing video data to the first video data storage means and the second video data storage means, and writing video data to the third video data storage means and the fourth video data storage means Selecting means for alternately switching every frame period;
Reading video data from the first video data storage means and the second video data storage means, and reading video data from the third video data storage means and the fourth video data storage means Display control means for alternately switching every frame period,
Writing the video data in the first video data storage means and the second video data storage means, and writing the video data in the third video data storage means and the fourth video data storage means, Each is performed sequentially in one frame period,
In the first video data storage means and the second video data storage means, and in the third video data storage means and the fourth video data storage means, the writing of the video data and the reading of the video data Are performed alternately
In the fifth video data storage means and the sixth video data storage means, video data read out by the display control means in a period other than receiving video data of one image in one frame period. The display circuit control circuit is written by the writing means.   5. A display device comprising: the control circuit of the display device according to claim 1; and a display panel provided with a light emitting element for each pixel.   The display device according to claim 5, wherein the light-emitting element is an EL element.   An electronic device comprising the control circuit according to claim 1.   The electronic apparatus according to claim 7, comprising a display device configured by the control circuit and a display panel.

Images