JPS58187995A - Image display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image display device having a display memory divided into a plurality of blocks, and more particularly to an image display device suitable for color full graphic display.

In recent years, among the display devices connected to computers, the display functions of personal computers, etc. have been required to be more sophisticated, and the central processing circuit (CPU) of electronic computers, which has been integrated into a single chip, has become more sophisticated.
microprocessor.

Hereinafter abbreviated as MpU. ) have been proposed to achieve this by making full use of their limited functions.

For example, color full graphic display is the most requested function. In response to this demand, multiple professionals have proposed a so-called bank switching method in which divided display memories are switched and accessed, and a method that further improves the bank switching method and uses input/output registers in parallel to access the display memory at high speed. has been done. Regarding the latter method, see Japanese Patent Application Laid-open No. 5
4-38724, 4! This method is described in detail in Japanese Patent Application No. 155609/1983, and is said to be particularly excellent in high-speed data transfer within a display memory and continuous writing of the same data.

The present invention further improves the remaining drawbacks of such proposals. Therefore, before explaining the present invention, the above-mentioned prior art and its drawbacks will be explained using FIGS. 1, 2, 3, and 4.

FIG. 1 is a block diagram of a display circuit in a display device or a personal computer when the above-mentioned conventional technology is applied to graphic display, where 1 is an MPU, 2 is
3 is an address bus, 3 is a data bus, and 4 is a read/write control signal line (hereinafter abbreviated as Ryy line) indicating read/write operations of the MpU. Further, 5 is an address decoder that decodes the address of the circuit necessary for display, and 6 is a CRT (C'athodg Rey) that generates various timing signals for display.
TtLbe ) control circuit (hereinafter abbreviated as C' RT C).

), 7 is a multiplexer that switches between the MPU address bus 2 and the display address signal line 8 from the CRTC in accordance with a signal supplied by the display timing signal @9. Furthermore, 10, 11.12 is display memory, 13° 14.1
5 displays the display information read out from the display memory on the display unit 1.
17. a parallel-to-serial conversion circuit for converting signals into signals that can be inputted by 6;
18 and 19 are display memory input/output circuits. moreover,
2o is an input/output control circuit that generates control signals for the display memory input/output circuits 17, 18, and 19, and 22 to 35 are signal paths connecting the circuits.

2 and 3 are examples of more detailed circuits of the display memory 10 and the display memory input/output circuit 17 of FIG. 1, and FIG. 4 is an explanatory diagram of the operation of FIG. 3.

In FIG. 1, display memories 10, 11, and 12C
'The stored contents are periodically read out as display information by various timing signals generated from the RTC 6, and the read display information is displayed as visible information on the display unit 16 through parallel-to-serial conversion circuits 13, 14, and 15, respectively. be done.

MpU i also displays these display memos +710.11.
It writes or updates display information to the address bus 12, and inputs and outputs data via the address designated via the address bus 2 and the data bus 5. Further, a signal indicating the input/output direction of this data is outputted to the output line 4.

The multiplexer 7 is switched by a signal supplied by the display timing signal line 9, and the display memories 10, 11.1
A composite address signal for driving 2 is output to composite address bus 2BK.

When the MPU 1 accesses the display memo IJ 10, 11, 12, the address decoder 5 decodes a signal indicating that the display memory is being accessed and supplies it to the input/output control circuit 2o via the signal path 29. Also, data bus 31
The R/r line 4 and display timing signal line 9 are also input to the input/output control circuit 2o.

The input/output control circuit 20 is a kind of decoding circuit, and uses these input signals to output the display memories 10゜it, 12
and generates control signals necessary for display memory input/output circuits 17, 18, 19, signal path 3o and signal path 31, 3.
Supply via 2.33.

The display memory 10 is a bit-based memory program whose memory size is defined as shown in FIG.
If PUt handles bytes (8 bits, t), memory processing is performed in bytes.

It becomes In FIG. 2, 50 to 57 are RAM (Ra
It has a storage capacity sufficient to display 11ii screens in total. Specific examples include Hitachi 4A Pitsu) RAM,
An example is EM6147, which allows graphic display of 256 dots in the horizontal direction and 128 dots in the vertical direction. Of course, it is also possible to use a larger element such as 16 bits or 641 bits, and even if it is a dynamic RAM, it can be controlled by adding a control signal from the input/output control circuit 2o. . Note that the lines 22, 23, 28, and 30 in FIG. 2 are the same as the line numbers in FIG. 1, and the other display memories 11 and 12 have the same configuration as in FIG. 2.

The display memory input/output circuit 17, as shown in FIG. . This input/output register 172 is a major feature of the prior art, and the input/output control circuit 20 controls data input/output of the input/output register 172, and a single instruction issued from the MPU 1 can exceed the range that the data bus can handle. There are K cases where input/output processing is enabled. That is, K as shown in Table 1.

Data transfer and reception between the input/output register 172 and MPU 1
In addition to data transfer between the PU 1 and the display memory 10, data transfer between the input/output register 172 and the display memory 10 is possible, for example, the display memory input/output circuit 17 in FIG.
When data is exchanged between the MPUt and the display memory 10, at the same time, another display memory input/output circuit 1 having the same configuration
8.19 is configured to exchange data between the input/output register and the display memory, thereby enabling faster input/output processing.

Table 1 H: High level, L: Low level, ↑: Trigger, X: Indeterminate Processing performance is improved as more specific examples as follows. For example, when moving the display of a certain color to another display position, as typified by screen scrolling, MpU l is the display memo! By simply performing the process of moving only the information stored in Jl0IC, the stored contents of display memos 1J11 and 12 can also be moved at the same time, making it possible to improve processing performance by approximately three times compared to the bank switching method. . Similarly, in the case of screen deletion, K, 1
Three series can be processed simultaneously by erasing processing corresponding to the series.

However, when the MPU 1 tries to write a new color to a dot at a certain coordinate on the display screen, or when it tries to read the color information at that coordinate, as in the puncture switching method,
For each of the display memories 10, 11, and 12, it was necessary to exchange data with one bit corresponding to the specified coordinates.

Furthermore, since the MPU 1 performs parallel processing on multiple bits, multiple logical operations are required to exchange data with one bit of the display memory. As a result, the procedure for displaying graphic images becomes complicated, and it is not possible to exchange information at high speed, resulting in a disadvantage that the processing performance of the MPU 1 is reduced.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to overcome the drawbacks of the prior art and to provide an image display device that simplifies the processing procedure for transmitting and receiving image information in units of dots and does not reduce the processing performance of the MPU. It is in.

In order to achieve the above object, in the present invention, one of the displayed images is
A plurality of display memory processors corresponding to the dots are connected to a plurality of memory dot input/output circuits capable of transmitting and receiving data between a plurality of bits of a plurality of display memory processors and a predetermined plurality of dots of a data node of the MpU, and a display memory operates on a bit-by-bit basis. A display memory bit input/output control circuit that can be set to non-operation is provided.The display memory bit input/output circuit operates the display memory and the memory dot input/output circuit under the control of the display memory bit input/output control circuit, and multiple bits of the multiple display memories can be set by one instruction from the MPU. It is characterized by making it possible to exchange data with the MpU.
It is now possible to exchange data with multiple display memory blocks using the same color information handled by .

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a diagram showing an embodiment of the present invention, and circuit blocks having the same functions as those in FIG. 1 are given the same symbols as in FIG. 1. In Figure 4, 170, 180, 190
200 is the memory bit input/output circuit of the display memories 10, 11 and 12, respectively, and 200 is the memory bit input/output circuit 170.
, 180, and 190, and 64 is a signal line commonly supplied from the bit input/output control circuit 200 to the memory bit input/output circuits 170, 180, and 190.

In FIG. 4, a bit input/output control circuit 200 has almost the same function as the input/output control circuit 20 in FIG. The difference is that the signal path 34 is commonly supplied to the memory pit input/output circuits 170, 180, and 190. With this configuration, the data bus 3 of the MPU 1 is connected to a plurality of blocks of display memories 10 and 11.
．． 12 and the color information of any one dot on the display screen.

This will be explained in more detail below.

5 is a diagram conceptually showing an example of the operation of FIG. 4, FIG. 6 is an example of a more detailed configuration of the bit input/output control circuit 200 of FIG. 5, and FIG. 7 is a diagram conceptually showing an example of the operation of FIG. Output circuit 180
This is an example of a more detailed configuration.

In FIG. 4, the display memories 10, 11, and 12 display the three primary colors of light (red, green, and blue, respectively abbreviated as RGB) R,
If G and B are respectively assigned, a certain point on one display screen corresponds directly to a certain bit at a certain address in the display memory 10, 11, 12, as shown in FIG. Of course, this point is the same in the conventional example, but in the present invention, each bit of the multiple block display memory is directly transferred to the MPUt as shown in FIG.
A major feature is that data can be exchanged with

The bit input/output control circuit 200 includes the functions of the input/output control circuit 200 of the conventional configuration shown in FIG. 1, as shown in FIG.
It has a function of outputting a control signal for selecting each memory chip, that is, bit by bit, to the signal path 30, and outputting selection information at that time to the signal path 54. In FIG. 6, 60 is a display mode (IJ dot operation selection circuit, 6
1 is a register for storing selection information, and 62 is a decoding circuit 61 that converts selection signals of display memos IJ10, 11, and 12 into display timing signals! An AND/NOR circuit synthesizes signals supplied from s19, and 34 is a line for outputting selection information. The line symbols in FIG. 6 correspond to those in FIG. 4, respectively. The signal supplied by the display timing signal 11819 (abbreviated as SF scratch signal) indicates the period for reading out the memory contents of 10, 11 and 12 for display when it is at a high level. This indicates that data can be exchanged with the display memories 10, 11, and 12. Therefore, during the period when the SIP'@ issue is at a high level,
A memory selection signal (abbreviated as 'S1) supplied to the display memories 1o, 11, and 12 is set to a low level (active state) K by an AND/NOR circuit 63, and a read/write control signal (abbreviated as WE1 signal). ) are set to high level (continuous state).As a result, display memories 1o, 11,
12 are all in the read state and supply image quality information to the display section. On the other hand, during the period when the SFF signal is at a low level, a signal is outputted from the decoding circuit 62 so that each bit or all bits of the display memory become active depending on the information stored in the register 61. The relationship between the input and output signals of the decoding circuit 620 is shown in Table 1.
When the human power is at low level, the output is in bit units.

Table 2 0: low level, 1: high level, x: undefined Done, display memo IJ10, 11.12
supplied to As a result, display memory 10, 11.12
Data can be exchanged between the memory bit input/output circuits 170, 180, and 190.

The above is the register 61. Decode circuit 62. A display memory dot operation selection circuit 60 that enables bit-by-bit operation of display memos IJ10, IJ11, and IJ12 is configured by an AND/NOR circuit.

In addition, since the input/output control circuit 20 functions as a decoding circuit as described in the conventional example, the input/output control circuit 20 functions as a decoding circuit as described in the conventional example.
ogramahle Read 0nly Memor
y) and pLA (Progranable Log
ic Array). Therefore, in the configuration of FIG. 6, memory bit input/output circuit 170. ．． 1s
A signal commonly supplied to O, H'o K is sent to the register 61.
The output signal is directly output to the signal path 64, but
As another configuration example, this register 6 is included in the input/output control circuit 20.
It will be obvious that it is possible to input one output signal and output it as an individual control signal.

Next, memory bit input/output circuits 170, 180, 190
This will be explained in detail using FIG. 7, using the memory bit input/output circuit 170 as a representative. As shown in FIG. 7, the memory bit input/output circuit 170 is constructed by adding a circuit for inputting/outputting bits in parallel to the bidirectional buffer circuit 171 of the conventional display memory input/output circuit 17.
It has a function that allows data to be exchanged using fixed bits and data input/output @22. In this figure, circuit blocks having the same functions as those in FIGS. 3 and 4 are given the same symbols, and corresponding lines are also given the same symbols. 173 is a buffer circuit; 174 is a data selector circuit with 8 inputs and 1 output; 175 is a buffer circuit; 176.1
A switching circuit 77 switches between operating the bidirectional buffer circuit 171 and operating the buffer circuits 173 and 175 for bit unit input/output. Also, 315
-19 indicate signal paths.

In FIG. 7, the display memory 1o is configured to display R out of the three primary colors of light.
If a color is assigned, the buffer circuit 173
, 175 are connected only to the bits of the data bus 6. Further, the signal for operating the buffer in the output direction supplied by the signal path 312 is connected to the signal path 615.
The Q output signal (hereinafter abbreviated as Q signal) of the register 61 in FIG.

In this example, when the Qs defect signal is low level, the signal path 516
and when it is at high level, it is output to the signal path 317, and is output to the bidirectional buffer circuit 171 and the buffer circuit 173, respectively.
make it work. Furthermore, the signal for operating the buffer in the input direction supplied by the signal path 313 is similarly applied to the output signal path 318 or 319 of the switching circuit 177.
is output to.

q, an operation signal is output to the signal path 318K when the signal is at a low level, and to the signal path 319 when it is at a high level to operate the bidirectional buffer circuit 171 and the buffer circuit 175, respectively. Therefore, when the Qs flaw signal is low level, the third
It can perform the same operation as the display memory input/output circuit 17 shown in the figure, and when at a high level, the display memory 10 and the input/output register 172 can exchange data only with the data bus 301 bit. The buffer circuit 173 includes the MPU1
The data selector circuit 174 is a circuit for expanding a 1-bit signal output from the display memory 10 to the data bus 3 to 8 bits, which is the bit configuration of the display memory 10.
This circuit outputs one valid bit of the 8-bit data output from 0 to the data bus 6 via the buffer circuit. The select terminal of the data selector circuit 174 receives the Qo-Q output of the register 61 in FIG.
4 and is configured to correspond to the valid bit of the display memory 1o.

As described above, the 1-display memory 10 is configured to be able to exchange data with bits over the entire data bus 3.

Similarly, the display memory 11 can exchange data with the bits, and the display memory 124C can exchange data with the D0 pit. Therefore, when writing a color on one dot in a part of one display screen as shown in Fig. 6,
Calculate which address and which bit of the display memory 10, 11, and 12 correspond to the bits, and store the bit positions in the register
Processing can be done by simply writing the color to 1 at that address. Conversely, even when reading the color of a single dot on the display screen, the process can be done simply by specifying the register 61 and reading the corresponding address, resulting in an overall improvement in processing performance that is more than double that of conventional circuits. can be expected.

In addition, in the configuration shown in FIG. 7, the display memory data input/output line 2
2 includes not only the display memory 10 but also the input/output register 17.
2 is also connected, the process of writing fixed information to the input/output register 172 can also be realized with a simple procedure. In this case, the bit input/output control circuit 200 is slightly modified, and data exchange with the data bus 6 is performed in bit units.
This can be realized simply by generating signals that cause the input/output register 172 and the other two input/output registers corresponding thereto to store data.

The above explanation is based on the assumption that 1 bit of display memory corresponds to 1 dot) [3 blocks, but 1 dot) K
It is obvious that the same configuration can be applied up to the number of bits that the MpU 1 can exchange data at one time, even if more blocks and more bits correspond.

Furthermore, although the above description has been made regarding a display device using C'RT, it goes without saying that the same configuration can be applied to other display devices such as plasma and liquid crystal display devices.

As described above, according to the present invention, when the MpU exchanges data with the display memory of multiple blocks, it is possible to exchange data all at once as color information spanning multiple blocks of display memory, which eliminates the need for conventional technology. In comparison, m111# information exchange can be realized in a procedure more than three times faster. therefore,
An image display device with improved MpU processing performance can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example of a display circuit for a display device or personal computer. FIG. 2 is a block diagram showing an example of a more detailed configuration of the display memory block in FIG. 1. FIG. 4 is a block diagram showing an example of a more detailed configuration of the display memory output circuit; FIG. 4 is a block diagram showing an embodiment of the present invention; FIG. 6 is a program diagram showing an example of a more detailed configuration of the bit input/output control circuit in FIG. 4, and FIG. 7 is a program diagram showing an example of a more detailed configuration of the memory bit input/output circuit. It is a diagram. Explanation of symbols 1-・・・・・・・・・・・・MpUlo・・・・
・・・・・・・・・Display memory 11・・・・・・・・・・
・・・・・・Display memory 12・・・・・・・・・・・・
・・・Display memory 16・・・・・・・・・・・・・・・
Display section 60...Display memory dot operation selection circuit 170...Memory bit input/output circuit 180... ...Memory bit input/output circuit 190...Memory bit input/output circuit 200...Bit input/output control circuit 3 Figure 7 No. 4 Illustration 5

Claims (1)

[Claims] 1. A central processing circuit, a plurality of display memories in which stored information is displayed as an image, and information input/output between the display memory and the central processing circuit is a display image. The display memory bit input/output control circuit controls the bit-by-bit operation of the memory bit input/output circuit and the display memory. The display memory bit input/output control circuit operates the plurality of series of display memories bit by bit, and the memory bit input/output circuit operates the plurality of series of display memories bit by bit. An image display device characterized in that it is controlled by 5 to send and receive information. 2. The display memory bit input/output control circuit has a memory operation setting circuit that sets the operation of the display memory,
Depending on the setting information of the memory operation setting circuit, it is possible to set whether the entire bit width constituting at least one series of the display memory operates, or whether the display memory operates in units of bits corresponding to one dot. iiiIgI display device according to claim 1.