JPH0962853A - Graphic processor and graphic processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a graphic processor which speedily executes a random dither processing while constitution is simplified. SOLUTION: A geometry calculation part GC converting graphic data becoming a display object into display graphic data displayed on a monitor and a rendering calculation part RC converting display graphic data obtained in the geometry calculation part GC into display picture element data on respective picture elements and writing the display picture element data in a frame buffer 5 are provided. The rendering calculation part RC is a graphic processor which adds random numbers to display picture element data and executes the random dither processing The rendering calculation part RC reads the random numbers stored in an area except for an area storing display picture element data in storage areas for one picture element and executes the random dither processing based on the random numbers which are read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a geometry operation for converting graphic data to be displayed into display graphic data displayed on a monitor based on image processing command information received from a data bus of a host processor. And a rendering operation unit for converting the display graphic data obtained by the geometry operation unit into display pixel data for each pixel and writing the display pixel data in the frame buffer, The rendering calculation unit adds a random number to the display pixel data,
The present invention relates to a graphics processor configured to perform random dither processing, and a graphics processing system including the graphics processor.

[0002]

2. Description of the Related Art Such a graphic processor is a processor which mainly performs various processes for displaying a three-dimensional image on a monitor, instead of a host processor, and is roughly divided into a geometry calculation section and a rendering calculation section. It is configured. The geometry calculation unit converts the graphic data to be displayed into display graphic data to be displayed on the monitor by performing coordinate conversion, clipping processing, and the like. Since this display graphic data is data expressed by lines or surfaces, it is necessary to convert it into data for each pixel in order to display it on the monitor, and the rendering unit performs this conversion processing.

In the rendering unit, not only the display graphic data is converted into pixel data, but also so-called hidden surface processing is executed in pixel units, and finally converted into display pixel data to be displayed on the monitor. It This display pixel data is written in a so-called frame buffer, and the written information is displayed on a monitor after D / A conversion. As described above, the display pixel data written in the frame buffer is assigned a predetermined number of bits for the purpose of expressing color information including density gradation, but the number of bits is reduced to a small number in view of processing speed and storage capacity. The brightness resolution may be reduced due to the limitation. In such a case, the so-called dither method may be applied to improve the luminance resolution at the expense of the spatial resolution.

A so-called random dither method is considered as one of the dither methods. The random dither method is
By adding a random number to the brightness information of each pixel and making the brightness information have variations, it gives the illusion that the brightness does not change stepwise according to the brightness resolution, but as if the brightness changes continuously. To do so. In order to execute the process by the random dither method, that is, the random dither process, conventionally, a structure for obtaining a random number based on a general pseudo-random number generation formula every time the random dither process is performed, or a previously obtained random number is exclusively Store it in memory,
A configuration is considered in which the random number is read in the random dither processing.

[0005]

However, the former of the above-mentioned conventional configurations has to reduce the processing speed of the graphic processor because it is necessary to execute an operation for obtaining a pseudo-random number each time random dither processing is performed. In addition, the latter of the above-mentioned conventional configurations has a disadvantage that a dedicated memory for random numbers is required and the configuration becomes complicated.
Pseudo-random numbers generally have periodicity, and if this period is short, a specific pattern appears on the monitor screen, so it is necessary to lengthen the period to some extent. The memory capacity is required, and the configuration becomes more complicated. The present invention has been made in view of the above circumstances, and an object thereof is to provide a graphic processor that can perform random dither processing rapidly while simplifying the configuration, and a graphic processing system using the graphic processor. It is in the point of providing.

[0006]

According to the present invention, the rendering operation unit has the display pixel in the storage area for one pixel in the frame buffer when performing the random dither processing. A random number stored in an area other than the area for storing data is read, and the read random number is used to execute random dither processing. That is, in the data structure of the frame buffer that stores the display pixel data, the number of bits that is an integral multiple of 8 bits is usually assigned to the display pixel data for one pixel, but the actual display for one pixel is performed. There are cases where the number of bits required for the use pixel data does not match the assigned number of bits, and there are unused bits. By using these unused bits, a random number for random dither processing is stored in advance, and the random number can be read from the rendering operation unit. Therefore,
The rendering operation unit does not need to obtain a pseudo-random number each time random dither processing is performed, and does not need to separately provide a dedicated memory for storing the random number, so that the random dither can be performed while simplifying the configuration. It has become possible to provide a graphic processor that can perform processing quickly.

According to the second aspect of the present invention, the rendering operation section causes the pixel data stored in the Z buffer, that is, the pixel data, to be displayed when the display graphic data, which is a three-dimensional image, is displayed on the monitor. The distance information from each viewpoint is read and the calculation for the hidden surface processing is executed. In parallel with the processing of reading the pixel data of the Z buffer, the random number stored in the frame buffer is read. That is, generally, since the rendering arithmetic unit can collectively address the Z buffer and the frame buffer, the random number can be read in parallel with the reading of the data from the Z buffer necessary for the hidden surface processing. Since the reading is performed, the random dither processing can be performed more quickly than in the case where the processing of reading the random number from the frame buffer is performed independently while simplifying the configuration as described above.

According to the third aspect of the present invention, the random number stored in the frame buffer is a pseudo random number obtained by calculation, and the number of random number data for one period of the pseudo random number is the frame buffer. Since it is configured so as to be equal to or larger than the storage capacity of the display pixel data, it is possible to prevent a phenomenon in which a specific pattern due to the periodicity of pseudo random numbers appears on the monitor screen. Moreover, the random numbers in the frame buffer can be read from the graphic processor, and the random dither processing can be performed quickly while simplifying the configuration of the entire graphic processing system.

According to the fourth aspect of the present invention, the rendering arithmetic unit specifies an address for the frame buffer when reading the random number from the frame buffer, but the address conversion unit specifies the specified address. After conversion based on the setting conditions, send it to the frame buffer. That is, since the random number stored in the frame buffer is fixedly set for each address of the display pixel data, the random number dither processing of the display pixel data stored at a certain address is performed. When the random number stored in the address is used, the data on the display portion on the monitor corresponding to the address is subjected to the random dither process with the same random number value. If the image displayed on the monitor is a still image or a moving image with little change, such processing will not cause any problems and a good image without flicker will be obtained, but the image displayed on the monitor will be a moving image with many changes. In such a case, a kind of noise generated by the random dither processing may appear to appear in the foreground, and the monitor display may be difficult to see. In such a case, the address conversion unit changes the address specified by the rendering operation unit according to the setting condition and sends it to the frame buffer, so that the data of the display portion on the monitor corresponding to the specified address is different. Random dither processing is performed with numerical values, and the monitor display can be made easy to see.

According to the fifth aspect of the present invention, the address conversion means changes the address designated by the rendering operation unit to the frame buffer based on the setting condition and then sends the changed address to the frame buffer. , It is possible to switch to a state in which the data is sent to the frame buffer without any change. Therefore, depending on whether the image displayed on the monitor is a still image, a moving image with few changes in the image, or a moving image with many changes in the image, the random number used for random dither processing is used properly. Therefore, even when a still image or a moving image with few changes in the image is displayed, or even when a moving image with many changes in the image is displayed, the monitor display can be easily viewed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A case in which an embodiment of a graphic processor of the present invention is applied to a graphic processing system will be described below with reference to the drawings. As shown in FIG. 1, the graphic processing system TD includes a host processor 1 that controls the entire apparatus and a graphic processing system TD that includes image processing command information (hereinafter sometimes simply referred to as “command information”). A main memory 2 for storing an operation program, a graphic processor 3 for executing image processing command information of various commands stored in the main memory 2, and a two-dimensional image for pasting on the surface of an image of a three-dimensional object. Texture buffer memory 4 for storing texture information which is information such as images, and frame buffer 5 for storing images for display.
A Z buffer 6 for hidden surface removal processing, a D / A converter 7 for converting digital image data created by the graphic processor 3 into an analog signal, and image data converted by the D / A converter 7 into an analog signal. A monitor 8 for displaying is provided. The graphic processing system TD is provided with various input / output devices, storage devices, and the like other than the above, but they are not shown.

As shown in FIG. 2, the graphic processor 3 includes an interface circuit 30 for exchanging data with the host processor 1 and the main memory 2 via a data bus DB and an address bus AB, and an interface circuit 30. A command accumulating unit 31 that stores a plurality of command information received from the data bus DB in a FIFO format, and command information received from the command accumulating unit 31 are sequentially processed to be a display target graphic expressed in a so-called world coordinate system. A geometry calculation unit GC that performs processing such as coordinate conversion in consideration of the position of the viewpoint and converts the data into display graphic data displayed on the monitor 8, and the display graphic data for each pixel. Rendering operation part RC for converting into display pixel data of
And a memory control circuit 32 for controlling the flow of data between the rendering calculation unit RC and the frame buffer 5 or the like.
And a sprite controller 36 that is a drawing mechanism that mainly handles a three-dimensional image and that is composed of a pipeline from the command storage unit 31 to the rendering calculation unit RC, and that handles a two-dimensional image. It is equipped. The rendering calculation unit RC also includes a rasterizer 33 that converts the display graphic data received from the geometry calculation unit GC into pixel data, and a pixel data storage unit that stores a plurality of pixel data received from the rasterizer 33 in a FIFO format. 34, and a pixel data processing unit 35 that performs processing such as hidden surface processing on the pixel data received from the pixel data storage unit 34 and converts the pixel data into display pixel data for each pixel.

The configuration of the geometry calculation section GC will be described in more detail. As shown in FIG. 3, the geometry calculation section GC controls each section of the geometry calculation section GC based on the command information received from the command storage section 31. Controller 40, a working memory 41 for storing vertex coordinates, normal line data, color data, etc. of graphic data to be displayed, which are included in the command information, and a working memory 41 serving as a working area for various calculations, and a working memory 41. An arithmetic unit 42 that executes arithmetic operations such as addition, subtraction, multiplication, and division on the data stored in
Data output memory 4 for storing the calculation result of the calculator 42
3, a selector 44 for selecting which of the data from the command storage unit 31 and the data from the arithmetic unit 42 is written to the working memory 41, and a register for managing the operation state of the geometry arithmetic unit GC. And 45 are provided.

The configuration of the pixel data processing unit 35 will be described in further detail. The pixel data processing unit 35 includes a controller 50 for controlling each unit in the pixel data processing unit 35.
The arithmetic unit 51 that performs processing such as random dither processing on the pixel data received from the pixel data storage unit 34 and the data to be written in the frame buffer 5 as the data (display data) to be displayed are processed by the arithmetic unit 51. A selector 52 for selecting from three types of data, data not processed by the arithmetic unit 51 or texture data read from the texture buffer, and Z for hidden surface processing.
A Z comparison circuit 53 for performing data comparison and a register 54 for managing the operation state of the pixel data processing unit 35 are provided.

The data that the pixel data processing unit 35 receives from the pixel data storage unit 34 is mainly pixel data,
The data may be data to be written to the register 54, and the data received from the pixel data storage unit 34 includes a command indicating whether to process the pixel data or whether it is a write command to the register 54. ing. The pixel data further includes a display address on the monitor screen, Z data that is the distance from the viewpoint, color data, and
A texture address and the like when the data of the texture buffer 4 is used are included, and each bit of pixel data is allocated. In the case of a write command to the register 54, a value to be written in the register 54 is assigned to the bit assigned to the display address and Z data in the pixel data.

The operation of the graphic processing system TD having the above configuration will be briefly described below. The host processor 1
Interface circuit 30 of the graphic processor 3
Command information stored in the main memory 2 is sequentially output to the data bus DB in the state where the address is designated. The command information includes, in addition to the drawing command, an interrupt signal generation command for generating an interrupt signal from the geometry calculation unit GC to the host processor 1 (hereinafter, referred to as “first interrupt signal generation command” for convenience). An interrupt signal generation command for generating an interrupt signal from the pixel data processing unit 35 to the host processor 1 (hereinafter,
For convenience, it will be referred to as a "second interrupt signal generation command"). The first interrupt signal generation command is a command for writing “1” in the interrupt signal generation bit of the register 45 of the geometry calculation unit GC, and the second interrupt signal generation command is the interrupt signal of the register 54 of the pixel data processing unit 35. This is an instruction to write "1" in the generation bit.

The position at which the first interrupt signal generation command is written in the command information is, for example, when certain command information is processed by the geometry calculator GC.
When you want to use the processing result, write it immediately after the command information. As for the position to write the second interrupt signal generation command in the command information, for example, from the state where the pixel data processing unit 35 writes the display pixel data to the frame buffer 5, the sprite controller 36 writes to the frame buffer 5. When it is desired to switch to a state in which the display pixel data is written, the command data relating to the display pixel data last written from the pixel data processing unit 35 may be written immediately after.

The command information output to the data bus DB is sequentially written in the command storage unit 31 via the interface circuit 30. The command storage unit 31
In the FIFO format, the previously stored command information is sequentially sent to the geometry calculation section GC, and the geometry calculation section GC sequentially processes the received command information. The controller 40 of the geometry calculation unit GC controls the selector 44, the calculation unit 42 and the like to perform the coordinate conversion and the like, and writes the calculation result to the data output memory 43. Controller 40
When receiving the above-mentioned first interrupt signal generation command from the command accumulating section 31, when writing, the data is written in the register 45 according to the instruction. As a result, the interrupt signal generation bit of the register 45 becomes "1", and this signal passes through the interface circuit 30 and
It is sent to the interrupt signal input of the host processor 1. In response to this interrupt request, the host processor 1 can interrupt the processing up to that point and read the data written in the data output memory 43 of the geometry calculation section GC, for example.

Further, when the controller 40 receives the second interrupt signal generation command from the command storage unit 31, the rendering is performed while maintaining the arrangement order with the display graphic data generated by the processing of the preceding and succeeding command information. It is sent to the rasterizer 33 of the arithmetic unit RC. Rasterizer 33
When the display graphic data is received from the geometry calculation unit GC, the display data is converted into pixel data of the above format while appropriately performing interpolation processing and the like, and sequentially written in the pixel data storage unit 34. When the second interrupt signal generation command is received in the middle of this process, the second interrupt signal generation command is sent to the pixel data storage unit 34 while maintaining the arrangement order with the pixel data generated by the processing of the preceding and following display graphic data.

Since the pixel data storage unit 34 is in the FIFO format, the pixel data is sent to the pixel data processing unit 35 in order from the previously written pixel data. Upon receiving the pixel data from the pixel data storage unit 34, the controller 50 of the pixel data processing unit 35 controls the arithmetic unit 51 and the Z comparison circuit 53 to sequentially perform Z data comparison and color resolution for hidden surface processing. Random dither processing to improve, shadow processing to calculate the brightness to express the shadow of an object, fog / depth skew processing to calculate the brightness to express perspective by brightness and darkness, or pasting of texture buffer data Then, the color data resulting from the processing is written as display pixel data in the designated display address of the frame buffer 5 in consideration of the processing result of the Z comparison circuit 53.

Among the above processes, the Z data comparison and the random dither process are executed in parallel, and the process steps will be briefly described. When the display address is input from the pixel data storage unit 34 to the memory control circuit 32, the memory control circuit 32 uses the address as the frame buffer 5 and the Z.
Send to buffer 6. In response to the designation of the address, the frame buffer 5 sends the data of the designated address to the arithmetic unit 51 and the Z buffer 6 sends the data of the designated address to the Z comparison circuit 54.
As shown in FIG. 5, the data stored in the frame buffer 5, that is, the pixel data for display, is allocated with a 16-bit storage area for each pixel 5a vertically and horizontally divided corresponding to the monitor display. In this 16-bit storage area, 6 bits D _{0 to} D ₅ are color codes and D _{6 to} D 5
₁₁ bits of 6 bits are used for luminance data, and 3 bits of D _{13 to} D ₁₅ of the remaining 4-bit free area are used for storing random numbers. The random number stored in the frame buffer 5 is a pseudo random number generation formula by the multiplication congruential method. X (n + 1) = (a × X (n) + c) mod m (mod means a remainder) It is the obtained pseudo-random number. Pseudo-random numbers have a periodicity, but the number of data for one period is equal to or larger than the storage capacity of the display pixel data of the frame buffer 5, for example, by performing a trial calculation, a, c, m is chosen to be an appropriate value.

When the arithmetic unit 51 receives the data including the random number from the frame buffer 5, the data D _13- .
A random number is extracted from D ₁₅ and added to the luminance data included in the color data in the pixel data received from the pixel data storage unit 34, and the random dither processing is executed. Arithmetic unit 5
In addition to the random dithering process, the writing device 1 writes it in the frame buffer 5 as display graphic data when the shadow process and the like described above are completed. However, this writing is limited to the case where the pixel data is determined by the Z comparison circuit 53 to be data on the side close to the viewpoint, and the reading is performed in D _{13 to} D ₁₅ of the display pixel data. Random numbers are written. On the other hand, the Z comparison circuit 53 that receives the Z data from the Z buffer 6 compares the Z data of the pixel data of the same display address sent from the pixel data storage unit 34,
It is determined which is closer to the viewpoint, the determination result is sent to the calculator 51, and the Z data on the closer side is written in the Z buffer 6.

The controller 50 includes a pixel data storage unit 3
When the second interrupt signal generation command, not the pixel data, is received from 4, the data is written in the register 54 according to the instruction at the time of reception. As a result, the interrupt signal generation bit of the register 54 becomes "1", and this signal passes through the interface circuit 30 and
It is sent to the interrupt signal input of the host processor 1. In response to the interrupt request, the host processor 1 may interrupt the processing up to that point, and switch from the state of writing from the pixel data processing unit 35 to the frame buffer 5 to the state of writing from the sprite controller 36 to the frame buffer 5, for example. it can. As described above, the display pixel data written in the frame buffer 5 is D /
After being converted into an analog signal by the A converter 7, it is displayed on the monitor 8.

[Other Embodiments] Hereinafter, other embodiments of the present invention will be listed. In the above-described embodiment, the display address of the pixel data and the value of the random number have a one-to-one correspondence, but as shown in FIG. 6, a circuit for designating the display address from the memory control circuit 32 to the frame buffer 5. An address conversion circuit 60, which is an address conversion means, may be provided in the middle of the process, and the display address may be changed to a setting condition and then sent to the frame buffer 5 to change the correspondence between the display address and the value of the random number. good. The address conversion circuit 60 can be switched between a state in which the address is changed according to the setting condition and a state in which the address is directly output without being changed according to an instruction from the controller 50. As the setting condition for changing the display address, the condition that a constant value is added to the display address input to the address conversion circuit 60, or the random number used in the previous random dither processing is stored, The condition such as adding the random number to the input display address may be used.

The operation when the address conversion circuit 60 shown in FIG. 6 is provided will be briefly described. Similar to the above embodiment,
The Z data comparison and the random dither processing are executed concurrently. When the display address is input from the pixel data storage unit 34 to the memory control circuit 32, the memory control circuit 32
The address is sent to the frame buffer 5 and the Z buffer 6. Of these addresses, the address sent from the memory control circuit 32 to the frame buffer 5 is input to the address input of the frame buffer 5 after the address has been changed by the address conversion circuit 60 as described above. In response to the designation of this address, the frame buffer 5 operates in the arithmetic unit 51.
The Z buffer 6 sends the data of the designated addresses to the Z comparison circuit 54. Subsequent processing in the arithmetic unit 51 and the Z comparison circuit 54 is the same as that in the above-described embodiment.

However, the computing unit 51 determines that the calculated display pixel data
Data D₁₃~ D_FifteenWrite the random number read to
Then, the random number stored in the frame buffer 5
It will change. To avoid this, the calculator 51
Write display pixel data to the frame buffer 5
Before the address change by the instruction from the controller 50
The conversion circuit 60 switches to a state where the address is not changed,
Specify the display address of the pixel data being processed and
The random number in the memory buffer 5 is read and the pixel data for display is
D ₁₃~ D_FifteenTo write the original random number data to
It is necessary. In this way, it is stored in the frame buffer 5.
Specified display address when reading the random number
The conversion process is to display a moving image with many changes on the monitor.
It is suitable for static images, but still images and moving images with few changes
, The screen may flicker, so
When reading random numbers from the frame buffer 5, the address
The output conversion circuit 60 to the state where it is output as it is without any change.
It can be switched. This switching is performed by the main memory 2
Write the image processing command information to switch the above
By including it, the operator can specify it arbitrarily.

In the above embodiment, pseudo random numbers obtained by the multiplication congruential method are used as the random numbers to be written in the frame buffer 5, but other random number generation methods such as the so-called M-sequence method are used instead of the multiplication congruential method. It is also possible to employ a pseudo-random number generated by. Alternatively, the random numbers in the random number table may be written in the frame buffer 5.

In the above embodiment, the case where the color data of the display pixel data is composed of the color code and the luminance data is illustrated, but the format in which the color is expressed by the luminance data of each of R, G and B is shown. But good. In this case, the addition of the random numbers in the random dither processing is executed for each of the R, G, and B luminance data.

In the claims, reference numerals are provided for convenience of comparison with the drawings, but the present invention is not limited to the structure shown in the attached drawings.

[Brief description of drawings]

FIG. 1 is a schematic block configuration diagram according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a graphic processor according to an embodiment of the present invention.

FIG. 3 is a block diagram of a main part according to the embodiment of the present invention.

FIG. 4 is a block diagram of a main part according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a frame buffer according to the embodiment of the present invention.

FIG. 6 is a block diagram of a main part according to another embodiment of the present invention.

[Explanation of symbols]

 1 host processor 3 graphic processor 5 frame buffer 6 Z buffer 8 monitor 60 address conversion means DB data bus GC geometry calculation unit RC rendering calculation unit

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location G09G 5/36 520 G06F 15/68 310J 9365-5H 15/72 350

Claims (5)

[Claims] 1. A process of converting graphic data to be displayed into display graphic data displayed on a monitor (8) based on image processing command information received from a data bus (DB) of a host processor (1). And a geometry calculation unit (GC) for converting the display graphic data obtained by the geometry calculation unit (GC) into display pixel data for each pixel, and displaying the display pixel data. 5) is provided with a rendering calculation unit (RC), and the rendering calculation unit (RC) is a graphic processor configured to add a random number to the display pixel data and perform random dither processing. In the frame buffer (5), the rendering calculation unit (RC) is configured to display the table in the storage area for one pixel. A graphic processor configured to read a random number stored in an area other than an area for storing display pixel data and execute the random dither processing based on the read random number. 2. The rendering operation unit (RC) reads a random number stored in the frame buffer (5) in parallel with a process of reading pixel data from a Z buffer (6) for hidden surface processing. The graphic processor according to claim 1, configured as described above. 3. The graphic processor (3) according to claim 1 or 2, and a frame buffer (5) for storing the display pixel data, wherein the random number stored in the frame buffer (5) is
A graphic that is a pseudo-random number obtained by calculation, and is configured such that the number of random-number data for one cycle of the pseudo-random number is equal to or larger than the storage capacity of the display pixel data of the frame buffer (5). Processing system. 4. When the rendering operation unit (RC) reads a random number stored in the frame buffer (5), the rendering operation unit (RC) designates to the frame buffer (5). The graphic processing system according to claim 3, further comprising address conversion means (60) for sending the address to the frame buffer (5) after changing the address based on a setting condition. 5. The address conversion means (60) specifies the frame buffer (5) by the rendering operation unit (RC) when reading a random number stored in the frame buffer (5). 5. The graphic processing according to claim 4, wherein it is configured to be switchable between a state in which the address is changed based on a setting condition and then sent to the frame buffer (5) and a state in which the address is sent to the frame buffer (5) as it is. system.