KR101933112B1 - LCD and method of driving the same - Google Patents

Abstract

The present invention provides a liquid crystal display device comprising: a liquid crystal panel including a plurality of gate lines and a plurality of data lines crossing each other to define pixels; A drive mode selector for receiving image data displayed on the liquid crystal panel, determining whether the image data is a moving image or a still image, and generating a drive mode signal corresponding to the image data; Wherein when the driving mode signal corresponds to the moving picture, the driving control unit generates a first control signal by maintaining the high frequency of the control signal, and when the driving mode signal corresponds to the still image And a timing controller for changing the high frequency of the control signal to a low frequency to generate the first control signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) display device have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used today because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

Hereinafter, a general liquid crystal display device will be described with reference to FIG.

1 is a block diagram schematically showing a general liquid crystal display device.

1, the liquid crystal display device 1 may include a liquid crystal panel 2 and a driving unit 6 for driving the liquid crystal panel 2.

In the liquid crystal panel 2, a gate line GL and a data line DL which define the pixel P are extended to each other. At this time, the pixel P may include a thin film transistor T, a storage capacitor Cst, and a liquid crystal capacitor Clc.

The driver 6 includes a gate driver 4 for outputting a gate voltage to the gate line GL, a data driver 5 for outputting a data voltage to the data line DL, and a timing controller 3 have.

The timing controller 3 receives the data control signal DS for controlling the data driver 5 and the gate control signal GS for controlling the gate driver 4 using the control signal TS received from the external system, ). In addition, the timing controller 3 aligns the input image data DD and transfers the image data DD to the data driver 5.

Such a liquid crystal display device 1 drives the driving part 3 at a high frequency in order to express a clear high quality image on the liquid crystal panel 2. [ In other words, the control signal TS input from the outside is generally a high frequency of 60 Hz or more, and the timing control section 3 uses the control signal TS having a high frequency to generate the gate control signal GS and the data control signal DS ).

The high-speed driving for driving the driving unit 3 with such a high frequency provides an effect of improving a motion blur and a judder in which images overlap each other when a moving image is displayed on a screen.

However, such a high-speed driving also has a disadvantage of increasing power consumption. However, high-speed driving even when representing a still image increases unnecessary power consumption, which is inefficient.

Meanwhile, in order to reduce unnecessary power consumption, the driving unit 3 may be driven (that is, driven at a low speed) at a low frequency (for example, 30 Hz) when still images are displayed. In this case, flicker The phenomenon is increased.

The reason for this will be described with reference to Fig. 2 is a waveform diagram showing data voltages and luminance of pixels for high-speed driving (frequency: 60 Hz) and low-speed driving (frequency: 30 Hz), respectively. Here, the horizontal axis represents time (t), and F represents a frame.

1) is turned on, the data voltage is charged in the pixel (P in FIG. 1), and the luminance gradually increases to reach the maximum value (max1, max2) Respectively. Thereafter, when the thin film transistor (T in Fig. 1) of the corresponding pixel (P in Fig. 1) is turned off, the data voltage continues to be discharged until the data voltage of the next frame is charged, (min1, min2).

At this time, the first difference gp1 between the maximum luminance value max1 and the minimum luminance value min1 of the high-speed driving is smaller than the second difference gp2 between the luminance maximum value max2 and the luminance minimum value min2 Able to know.

The reason why the difference in the luminance variation amounts in each of the high-speed driving and the low-speed driving appears is because the period of one frame is different. In other words, in the case of high-speed driving, the period of one frame (about 16.7 msec) is relatively short, so that the data voltage is discharged less and the luminance variation is also small. On the other hand, in the case of low-speed driving, the period of one frame (about 33.3 msec) is relatively long, so that a large amount of data voltage is discharged, and accordingly, a luminance variation amount is also large.

Here, since the first difference gp1 of the high-speed driving is a difference that is difficult for the viewer to perceive, the viewer does not feel the flicker phenomenon. However, since the second difference gp2 of the low- .

That is, in the case of the low-speed driving, since the period of one frame is longer than that of the high-speed driving, the luminance variation is large and the viewer feels flicker.

As described above, in order to provide a high image quality to a viewer, high-speed driving is required, but unnecessary power consumption increases when high-speed driving is performed even when a still image is displayed.

On the other hand, in order to reduce unnecessary power consumption, when the still image is displayed at a low speed, the flicker phenomenon increases and the image quality deteriorates.

An object of the present invention is to provide a liquid crystal display device and a method of driving the same that can not only reduce unnecessary power consumption but also provide a clear image quality by driving a driving unit differently for each of a moving image and a still image.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel including a plurality of gate lines and a plurality of data lines crossing each other to define pixels; A drive mode selector for receiving image data displayed on the liquid crystal panel, determining whether the image data is a moving image or a still image, and generating a drive mode signal corresponding to the image data; Wherein when the driving mode signal corresponds to the moving picture, the driving control unit generates a first control signal by maintaining the high frequency of the control signal, and when the driving mode signal corresponds to the still image And a timing controller for changing the high frequency of the control signal to a low frequency to generate the first control signal.

Wherein the timing control unit includes: a frequency conversion unit for generating the first control signal by maintaining the high frequency of the control signal in response to the drive mode signal or changing the high frequency of the control signal to the low frequency; Arranging the image data in response to the high frequency of the first control signal when the driving mode signal corresponds to the moving image and arranging the image data in the first A data processor for transforming the converted image data to correspond to the low frequency of the control signal, and rearranging the converted image data; A data control signal generator for generating a data control signal in response to the first control signal; And a gate control signal generator for generating a gate control signal in response to the first control signal and the drive mode signal.

A gate driver for outputting a turn-on voltage to the plurality of gate lines in response to the gate control signal; And a data driver for generating a data voltage corresponding to the image data and outputting the data voltage to the plurality of data lines in response to the data control signal.

Wherein the gate driver sequentially outputs the turn-on voltage to the plurality of gate wirings in response to the gate control signal when the drive mode signal corresponds to the moving picture, , One frame is divided into k fields in response to the gate control signal, the k pieces of the gate wirings are grouped into a plurality of blocks, and i And a plurality of blocks are cyclically driven, wherein k is a natural number of 2 or more, and i is a natural number of 1 or more and k or less, and each field has a different value.

The high frequency of the control signal is 50 Hz or more and the low frequency of the first control signal is less than 50 Hz.

There is provided a method of driving a liquid crystal display including a liquid crystal panel including a plurality of gate lines and a plurality of data lines crossing each other to define pixels, image data displayed on the liquid crystal panel, and a timing controller receiving a control signal A first step of generating a drive mode signal by determining whether the image data is a moving image or a still image; And a second step of operating the timing controller in a moving picture mode when the driving mode signal corresponds to the moving picture and operating the timing controller in a still picture mode if the driving mode signal corresponds to the still picture Wherein the second step generates a first control signal by maintaining a high frequency of the control signal when the driving mode signal corresponds to the moving picture and if the driving mode signal corresponds to the still image, And changing the high frequency of the control signal to a low frequency to generate the first control signal.

Wherein the second step includes arranging the image data in response to the first control signal when the drive mode signal corresponds to the moving image and if the drive mode signal corresponds to the still image, Transforming the transformed image data to correspond to the low frequency of the first control signal, and rearranging the transformed image data; And generating a gate control signal in response to the first control signal and the drive mode signal.

A third step of, in response to the gate control signal, outputting a turn-on voltage to the plurality of gate wirings; And a fourth step of generating a data voltage corresponding to the image data in response to the data control signal and outputting the generated data voltage to the plurality of data lines.

The third step sequentially outputs the turn-on voltage to the plurality of gate wirings in response to the gate control signal when the drive mode signal corresponds to the moving picture, The method comprising the steps of: dividing one frame into k fields in response to the gate control signal, dividing the plurality of gate wirings into k blocks, dividing the plurality of gate wirings into a plurality of blocks, on voltage is sequentially outputted to an i-th gate wiring, and the plurality of blocks are circulated by driving the plurality of blocks, k is a natural number of 2 or more, and i is a natural number of 1 or more and k or less, .

The high frequency of the control signal is 50 Hz or more and the low frequency of the first control signal is less than 50 Hz.

The liquid crystal display device according to the embodiment of the present invention provides an effect that unnecessary power consumption can be reduced by driving the driving unit at a low speed when displaying a still image.

Also, when a still image is displayed, one frame is divided into a plurality of fields and driven, thereby providing a clear image quality.

1 is a block diagram schematically showing a general liquid crystal display device.
2 is a waveform diagram showing data voltages and luminance of pixels of each of high-speed driving and low-speed driving;
3 is a schematic block diagram of a liquid crystal display device according to an embodiment of the present invention.
4 is a block diagram schematically illustrating a timing controller 500 according to an embodiment of the present invention.
FIG. 5 is a diagram showing a waveform diagram and a data voltage of a gate voltage when driven in a high-speed mode according to an embodiment of the present invention. FIG.
6A to 6D illustrate a waveform diagram and a data voltage of a gate voltage when driven in a low speed mode according to an embodiment of the present invention.
7 is a simulation result showing luminance change and perceived luminance during one frame of a block composed of first to fourth gate wirings in low-speed driving according to an embodiment of the present invention.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

3 is a schematic block diagram of a liquid crystal display device according to an embodiment of the present invention.

3, the liquid crystal display device 100 according to the embodiment of the present invention includes a liquid crystal panel 200, a driving unit 300 for driving the liquid crystal panel 200, And a backlight 900 for supplying light.

First, the liquid crystal panel 200 is provided with a plurality of gate lines GL extending in the first direction, for example, along the horizontal direction, and a plurality of data lines DL extending in the second direction, for example, Located. The gate wiring GL and the data wiring DL intersect with each other to define a pixel P in the form of a matrix.

Each pixel P includes a thin film transistor T, a pixel electrode and a common electrode, a liquid crystal capacitor Clc formed of liquid crystal located between these electrodes, and a storage capacitor Cst.

The thin film transistor T is formed at the intersection of the gate line GL and the data line DL. A pixel electrode (not shown) is connected to the thin film transistor T. On the other hand, a common electrode (not shown) is formed corresponding to the pixel electrode. When a data voltage is applied to the pixel electrode and a common voltage is applied to the common electrode, an electric field is formed therebetween to drive the liquid crystal.

The storage capacitor Cst serves to maintain the data voltage applied to the pixel electrode until the next frame.

Each pixel P may be composed of R, G, and B subpixels displaying red, green, and blue, for example. That is, neighboring R, G, and B sub-pixels constitute a pixel P which is a unit of image display.

The backlight 900 serves to supply light to the liquid crystal panel 200. As the light source of the backlight 900, a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or the like can be used.

Hereinafter, a driving unit 300 according to an embodiment of the present invention will be described.

The driving unit 300 according to the embodiment of the present invention changes the driving mode according to whether the image data RGB input from the external system (not shown) is a moving image or a still image.

For example, when the image data (RGB) is a moving image, the driving unit 300 is driven in a high speed mode in which the driving frequency is a high frequency, and when the image data RGB is a still image, Speed mode.

The driving unit 300 may include a driving mode selection unit 400, a timing control unit 500, a gate driving unit 600, a data driving unit 700, and a power generation unit 800 .

First, the drive mode selection unit 400 receives image data RGB from an external system such as a TV system or a video card not shown, generates a drive mode signal MS corresponding to the image data RGB And outputs it to the timing control unit 500.

Specifically, the drive mode selection unit 400 generates a drive mode signal MS corresponding to a moving image when the image data RGB is moving image, and generates a driving mode signal MS corresponding to the moving image when the image data RGB is a still image And generates a drive mode signal MS.

In other words, the driving mode signal MS is a signal for selecting the driving mode of the driving unit 300. When the image data RGB corresponds to moving image, the moving image signal MS is displayed on the liquid crystal panel 200 without motion blur Speed mode when the image data RGB corresponds to a still image and is a signal to operate the driving unit 300 in a low speed mode in order to reduce power consumption . That is, the driving mode signal MS may be a signal corresponding to one of a high-speed mode for displaying a moving picture on the liquid crystal panel 200 and a low-speed mode for displaying a still image on the liquid crystal panel 200.

The timing controller 500 receives the driving mode signal MS and the video data RGB from the driving mode selector 400 and receives a vertical synchronizing signal Vsync and a horizontal synchronizing signal Hsync from an external system And a control signal TCS such as a clock signal CLK and a data enable signal DE. Meanwhile, although not shown, the control signal TCS may be input through the interface configured in the timing controller 500.

In addition, the timing controller 500 generates the first control signal (TCS1 in FIG. 4) by maintaining or changing the driving frequency of the control signal TCS corresponding to the driving mode signal MS.

The timing controller 500 generates a gate control signal GCS and a data control signal DCS in response to the driving mode signal MS and the first control signal TCS1 in FIG. 4 and supplies them to the gate driver 600 And a data driver 700. [

In addition, the timing controller 500 aligns, converts, and rearranges the image data RGB in response to the drive mode signal MS and the first control signal TCS1 in FIG. 4, and outputs the image data RGB to the data driver 700. FIG. This will be described later in more detail with reference to FIG.

The gate driver 600 sequentially scans a plurality of gate lines GL in response to a gate control signal GCS supplied from the timing controller 500. For example, a plurality of gate lines GL are sequentially selected for every frame, and a turn-on voltage, for example, a gate high voltage Vgh is output to the selected gate line GL . By the gate high voltage (Vgh), the thin film transistor T located in the corresponding row line is turned on. On the other hand, a turn-off voltage, for example, a gate low voltage Vgl is supplied to the gate line GL until the next frame scan, and the thin film transistor T maintains the turn-off state .

The data driver 700 supplies the data voltages to the plurality of data lines DL in response to the data control signal DCS and the video data RGB supplied from the timing controller 500. [ That is, using the gamma voltage, a data voltage corresponding to the image data (RGB) is generated, and the generated data voltage is output to the data line DL.

The power generating unit 800 generates various driving voltages necessary for driving the liquid crystal display device 100. For example, the power supply voltage supplied to the timing controller 500, the data driver 700 and the gate driver 600 and the gate high voltage Vgh and the gate low voltage Vgl supplied to the gate driver 600 .

Hereinafter, the timing controller 500 according to the embodiment of the present invention will be described in more detail with reference to FIG.

4 is a block diagram schematically showing a timing controller 500 according to an embodiment of the present invention.

4, the timing control unit 500 includes a frequency conversion unit 510, a data processing unit 520, a data control signal generation unit 530, and a gate control signal generation unit 540 can do.

First, the frequency converting unit 510 receives the driving mode signal MS from the driving mode selecting unit 400 (FIG. 3) and receives the control signal TCS from an external system (not shown).

The frequency converter 510 generates the first control signal TCS1 by maintaining or changing the driving frequency of the control signal TCS in response to the driving mode signal MS.

Specifically, for example, when the drive mode signal MS corresponds to the high speed mode (when the image data (RGB) is motion picture), the frequency conversion unit 510 maintains the drive frequency of the control signal TCS as it is , And generates the first control signal TCS1. That is, when the driving mode signal MS corresponds to the high speed mode, the driving frequency of the control signal TCS is the same as the driving frequency of the first control signal TCS1. At this time, the driving frequency may be a high frequency, for example, 50 Hz or more.

On the other hand, when the drive mode signal MS corresponds to a low speed mode (when the image data RGB is a still image), the frequency conversion unit 510 changes the drive frequency of the control signal TCS to a low drive frequency Thereby generating the first control signal TCS1. At this time, the driving frequency may be less than 50 Hz including low frequencies, for example, 15 Hz, 30 Hz, and the like.

The data processor 520 receives the first control signal TCS1, the image data RGB and the drive mode signal MS and aligns or converts and rearranges the image data RGB in response to the first control signal TCS1, (700 in Fig. 3).

Specifically, when the drive mode signal MS corresponds to the high speed mode, the data processing unit 520 aligns the image data RGB and outputs the image data to the data driver 700 (FIG. 3). This is because if the driving mode signal MS corresponds to the high speed mode, the driving frequency of the control signal TCS and the driving frequency of the first control signal TCS1 are the same and correspond to the driving frequency of the first control signal TCS1 This is because there is no need to convert image data (RGB).

When the driving mode signal MS corresponds to the low speed mode, the data processing unit 520 converts the image data RGB to correspond to the driving frequency of the first control signal TCS1 and outputs the converted image data RGB And outputs them to the data driver 700. [ For example, if the control signal TCS has a driving frequency of 60 Hz and the first control signal TCS1 has a driving frequency of 30 Hz, then the data processing section 520 determines that the image data RGB has a driving frequency of 30 Hz As shown in FIG.

The data processor 520 rearranges the converted image data RGB to correspond to a plurality of gate wirings (GL in Fig. 3) sequentially scanned in response to the driving mode signal MS, 700). This will be described in more detail later with further reference to Figures 6a to 6d.

For this, the data processing unit 520 may include a storage medium such as a line memory or a frame memory, and the storage medium may be an EEPROM.

The data control signal generator 530 generates a data control signal DCS for controlling the data driver 700 in FIG. 3 in response to the first control signal TCS1 and outputs the data control signal DCS to the data driver 700 do.

The data control signal DCS includes, for example, a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, a polarity signal : POL), and the like.

The gate control signal generator 540 generates a gate control signal GCS for controlling the gate driver 600 in FIG. 3 in response to the first control signal TCS1 and the driving mode signal MS, 600 of FIG. 3).

The gate control signal generator 540 generates the gate control signal GCS so as to correspond to the driving frequency of the first control signal TCS1 having a high frequency, for example, when the driving mode signal MS corresponds to the high speed mode, .

On the other hand, when the driving mode signal MS corresponds to the low speed mode, the gate control signal generator 540 generates the gate control signal GCS to correspond to the driving frequency of the first control signal TCS1 having a low frequency . This will be described in more detail later with further reference to Figures 6a to 6d.

The gate control signal GCS may include, for example, a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE) have.

Hereinafter, the high-speed driving and the low-speed driving of the liquid crystal display according to the embodiment of the present invention will be described in detail with reference to FIG. 5 and FIGS. 6A to 6D.

5 is a diagram showing a waveform diagram of a gate voltage and aligned image data when a liquid crystal display (100 in FIG. 3) is driven in a high speed mode according to an embodiment of the present invention, and FIGS. 6 FIG. 3 is a diagram showing a waveform diagram of a gate voltage and image data converted and rearranged when a liquid crystal display (100 in FIG. 3) is driven in a low speed mode according to an embodiment of the present invention.

First, with reference to FIG. 5, the operation of the liquid crystal display (100 in FIG. 3) will be described when the drive mode signal (MS in FIG. 3) corresponds to the high speed mode.

When the driving mode signal (MS in Fig. 3) corresponds to the high speed mode, the driving frequency of the control signal (TCS in Fig. 4) and the first control signal (TCS1 in Fig. 4) In Fig. 5, 60 Hz will be described for convenience of explanation. Here, a horizontal axis parallel to the horizontal direction represents time (t), and F represents a frame.

The driving frequency of the first control signal (TCS1 in FIG. 4) is 60 Hz, and the driving unit (300 in FIG. 3) including the gate driving unit (600 in FIG. 3) and the data driving unit do.

3) in response to a gate control signal (GCS in Fig. 3) supplied from the timing control section (500 in Fig. 3) every frame, the gate driver (600 in Fig. 3) GLn are sequentially selected, and a gate high voltage Vgh, which is a turn-on voltage, is supplied to the selected gate wiring. On the other hand, the gate-low voltage Vgl, which is a turn-off voltage, is supplied to the first to the n-th gate lines GL until the next frame scan.

In other words, when the driving mode signal (MS in Fig. 3) corresponds to the high speed mode, the first to nth gate wirings GL1 to GLn are sequentially scanned every frame, and the gate high voltage Vgh is supplied .

4) corresponding to the first to nth gate wirings GL1 to GLn to which the turn-on voltage is supplied, the video data (RGB in Fig. 4) N-th data D1 to Dn and supplied to a data line (DL in Fig. 3).

Here, the first data D1 corresponds to the first gate line GL1, the second data D2 corresponds to the second gate line GL2, and the n-th data Dn corresponds to the n- (GLn).

Hereinafter, the driving of the liquid crystal display (100 in FIG. 3) will be described with reference to FIGS. 6A to 6D when the drive mode signal (MS in FIG. 4) corresponds to the low speed mode.

When the drive mode signal (MS in Fig. 4) corresponds to the low speed mode, the drive frequency of the first control signal (TCS1 in Fig. 4) generated by converting the high frequency to the low frequency may be, for example, less than 50 Hz.

First, when the driving mode signal (MS in FIG. 4) corresponds to the low speed mode, the driving unit (300 in FIG. 3) drives one frame by dividing it into at least two fields.

To this end, the first to nth gate wirings GL1 to GLn are divided into a plurality of blocks, wherein each block includes gate wirings corresponding to the number of fields.

For example, when one frame is divided into two fields and driven, the plurality of blocks includes two gate wirings.

Also, a plurality of blocks are cyclically driven by repeating the number of times that gate wirings having the same ordinal number in each block are sequentially selected in a plurality of blocks and a gate high voltage (Vgh) is applied thereto.

Specifically, gate wirings (for example, first gate wirings of each block) having the same ordinal number in each of a plurality of blocks are sequentially selected in a plurality of blocks, and again, gate wirings (For example, the second gate wiring of each block) are sequentially selected. Thus, gate wirings having the same ordinal number are sequentially selected in each of the plurality of blocks, and by repeating this, all of the first to nth gate wirings are scanned.

In addition, the video data (RGB in Fig. 4) are rearranged in the data processing section (520 in Fig. 4) to correspond to the first to nth gate wirings GL1 to GLn to which the turn- Of DL).

A concrete example will be given with reference to Fig. 6A.

Here, FIG. 6A shows an example in which the driving frequency is 30 Hz and one frame (about 33.3 msec) is divided into two fields (one field = 16.7 msec) and driven.

As shown in Fig. 6A, each of the plurality of blocks includes two gate wirings corresponding to two fields.

For example, the first block BL1 includes first and second gate lines GL1 and GL2, and the second block BL2 includes third and fourth gate lines GL3 and GL4.

At this time, in the first to k-th blocks BL1 to BLk, the gate wirings having the same ordinal numbers are sequentially selected in the respective blocks, which is cyclically driven by repeating the number of fields twice.

For example, the first gate line GL1, which is the first gate line of the first block BL1, is selected and the gate high voltage Vgh is applied, and then the first gate line GL1 of the second block BL2 The third gate wiring GL3 is selected and the gate high voltage Vgh is applied.

By sequentially selecting the first gate wiring of each of the plurality of blocks, the first gate wiring of the k-th block BLk, which is the last block, is selected up to the (n-1) th gate wiring GLn-1.

That is, during the first field of one frame, gate wirings having the same ordinal number, for example, the first gate wirings, are sequentially selected in each of the plurality of blocks, and the gate high voltage (Vgh) is applied.

Then, during the second field of one frame, the second gate line GL2, which is the second gate line of the first block BL1, is selected and the gate high voltage Vgh is applied, and then the second gate line GL2 of the second block BL2 The fourth gate wiring GL4 as the second gate wiring is selected and the gate high voltage Vgh is applied.

By sequentially selecting the second gate wiring of each of the plurality of blocks, the nth gate wiring GLn, which is the second gate wiring of the kth block BLk, which is the last block, is selected.

That is, during the second field of one frame, gate wirings having the same ordinal number in each of the plurality of blocks, for example, the second gate wirings not selected during the first field, are sequentially selected and the gate high voltage Vgh is applied .

At this time, the image data (RGB in Fig. 4) is rearranged so as to correspond to the selected gate wiring and outputted to the data wiring (DL in Fig. 3). For example, during the first field, the video data (RGB in FIG. 4) is divided into the first data D1 and the third data GL2 so as to correspond to the first gate line GL1 and the third gate line GL3 sequentially selected. (D3). During the second field, the video data (RGB in Fig. 4) is transferred to the second data line D2 and the fourth data D4 so as to correspond to the second gate line GL2 and the fourth gate line GL4 sequentially selected. ).

On the other hand, the first gate wirings of each block are sequentially selected and the second gate wirings of the respective blocks are sequentially selected, and the order may be reversed. In other words, the second gate wiring of each block can be sequentially selected, and then the first gate wiring of each block can be sequentially selected.

An example is given with reference to FIGS. 6B to 6D.

Here, FIGS. 6B to 6D show an example in which the driving frequency is 15 Hz and one frame (about 66.7 msec) is driven by being divided into four fields (one field = about 16.7 msec).

Here, description of the same or similar parts to those in Fig. 6A will be omitted.

As shown in FIGS. 6B to 6D, each block BL includes four gate lines corresponding to four fields.

In addition, the gate wirings having the same ordinal number are sequentially selected four times in each of the plurality of blocks BL, so that the plurality of blocks BL are cyclically driven.

6B shows a state in which the first gate lines GL1, GL5 and GL9 of the respective blocks BL are sequentially selected during the first field and the second gate lines GL2 GL6 and GL10 are sequentially selected and the third gate lines GL3, GL7 and GL11 of the respective blocks BL are sequentially selected during the third field. During the fourth field, And the fourth gate wiring GL4, GL8, and GL12 are sequentially selected.

Also, the image data (RGB in Fig. 4) is rearranged corresponding to the selected gate wiring.

During the first field, the first gate lines GL1, GL5, and GL9 of the respective blocks BL are sequentially selected. During the second field, the third gate lines GL3 , GL7 and GL11 are sequentially selected and the second gate lines GL2, GL6 and GL10 of the respective blocks BL are sequentially selected during the third field, and during the fourth field, And the fourth gate wiring GL4, GL8, and GL12 are sequentially selected.

Also, the image data (RGB in Fig. 4) is rearranged corresponding to the selected gate wiring.

During the first field, the first gate lines GL1, GL5, and GL9 of the respective blocks BL are sequentially selected. During the second field, the fourth gate lines GL4 GL8 and GL12 are sequentially selected and during the third field the second gate lines GL2, GL6 and GL10 of the respective blocks BL are sequentially selected and during the fourth field, And the third gate wiring GL3, GL7, and GL11 are sequentially selected.

Also, the image data (RGB in Fig. 4) is rearranged corresponding to the selected gate wiring.

As described above, when the driving mode signal (MS in FIG. 4) corresponds to the low-speed mode, one frame is driven by being divided into at least two fields. For this purpose, .

 In addition, a plurality of blocks are cyclically driven as many times as the number of the gate wirings having the same ordinal number is successively selected in each block.

By driving in this way, the following effects are obtained.

First, in the case of a moving image, a moving image can be clearly displayed on a liquid crystal panel without a residual image by performing high-speed driving, thereby providing an effect of improving image quality.

On the other hand, in the case of a still image, low-speed driving is performed, and power consumption is reduced.

At this time, at the time of low-speed driving, a flicker phenomenon (a screen flickering phenomenon) which occurs due to a large amount of luminance change during one frame is improved, which will be described with reference to FIG.

7 is a simulation result showing luminance change and perceived luminance during one frame of a block composed of first to fourth gate wirings when one frame is divided into four fields and driven at low speed according to an embodiment of the present invention.

In the first field, a turn-on voltage is applied to the first gate line GL1, and a data voltage is applied to the corresponding pixel in the first field. Accordingly, the luminance of the corresponding pixel corresponding to the first gate line GL1, GL5, ... of each block is gradually increased until the 1F / 4 time point, but after the 1F / 4 time point, GL1, GL5, ... are gradually decreased. At this time, the perceived luminance gradually increases, but has the largest value at the middle point of the first field, and gradually decreases to 1F / 4.

Then, in the second field, a turn-on voltage is applied to the second gate lines GL2, GL6, ... of each block, and a data voltage is applied to the corresponding pixel. Thus, the luminance of the pixel corresponding to the pixels adjacent to the first gate lines GL1, GL5, ... of the respective blocks, that is, the second gate lines GL2, GL6, ... of each block is 1F / 2. Accordingly, the reduced perceived brightness is increased again as the luminance is complemented by applying the turn-on voltage to the second gate lines GL2, GL6, ... of each block.

In other words, turn-on voltages are sequentially applied to gate wirings adjacent to each other within each frame, and the turn-on voltages are successively applied to the gate wirings adjacent to each other without dividing them into a plurality of fields, And the luminance of the corresponding pixel corresponding to the pixel is complemented.

 That is, adjacent gate wirings have the effect of recharging the data voltage after one field shorter than one frame, rather than immediately charging the data voltage again at the next timing.

As a result, the change in luminance is moderated, and the width of the change in the perceived luminance is reduced, thereby improving the flicker phenomenon.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

100: liquid crystal display device 200: liquid crystal panel 300:
400: drive mode selection unit 500: timing control unit
510: Frequency converter 520: Data processor
530: Data control signal generation unit 540: Gate control signal generation unit
MS: drive mode signal

Claims (13)

A liquid crystal panel including a plurality of gate lines and a plurality of data lines crossing each other and defining pixels;
A drive mode selection unit receiving image data displayed on the liquid crystal panel from an external system, determining whether the image data is a moving image or a still image, and generating a drive mode signal corresponding to the image data;
A first control signal is generated by receiving the drive mode signal and receiving a high frequency control signal from the external system and maintaining a high frequency of the control signal when the drive mode signal corresponds to the moving image, And generating a first control signal by changing the high frequency of the control signal to a low frequency when the signal corresponds to the still image, and controlling the gate control including the gate start pulse in response to the first control signal and the drive mode signal A timing control unit including a gate control signal generator for generating a signal;
A gate driver for outputting a turn-on voltage to the plurality of gate lines in response to the gate control signal,
Lt; / RTI >
Wherein the timing control unit comprises:
Receiving the control signal including the data enable signal and the drive mode signal and maintaining the high frequency of the control signal when the drive mode signal corresponds to the moving image and if the drive mode signal corresponds to the still image A frequency converter for converting the high frequency of the control signal into a low frequency to generate the first control signal;
When the drive mode signal corresponds to the moving image, aligns the image data in response to a high frequency of the input first control signal, and when the drive mode signal corresponds to the still image, A data processor for transforming the converted image data to correspond to a low frequency of a control signal and rearranging the converted image data;
Further comprising a data control signal generator for generating a data control signal in response to the input first control signal,
Wherein the gate control signal generator generates the gate control signal so as to correspond to a high frequency of the first control signal input when the driving mode signal corresponds to the moving picture and when the driving mode signal corresponds to the still image Generates the gate control signal to correspond to a low frequency of the input first control signal,
Wherein the gate driver comprises:
On voltage to the plurality of gate wirings in response to the gate control signal when the driving mode signal corresponds to the moving picture,
Wherein when the driving mode signal corresponds to the still image, one frame is divided into four first to fourth fields in response to the gate control signal, and the plurality of gate wirings are grouped into four consecutive ones, On voltage is sequentially output to the i-th gate line in each of the plurality of blocks for each field, and the plurality of blocks are cyclically driven, and i is a natural number of 1 to 4, Have different values
Liquid crystal display device.
delete The method according to claim 1,
And a data driver for generating a data voltage corresponding to the image data and outputting the data voltage to the plurality of data lines in response to the data control signal.
delete The method according to claim 1,
Wherein the high frequency of the control signal is 50 Hz or more and the low frequency of the first control signal is less than 50 Hz.
A liquid crystal panel including a plurality of gate lines and a plurality of data lines intersecting with each other to define pixels, image data displayed on the liquid crystal panel, and a high frequency control signal including a data enable signal from an external system A method of driving a liquid crystal display including a timing controller,
A drive mode selection unit for generating a drive mode signal by determining whether the image data is a moving image or a still image;
A second step of operating the timing controller in a moving picture mode if the driving mode signal corresponds to the moving picture and operating the timing controller in a still picture mode if the driving mode signal corresponds to the still picture;
And a third step of, in the gate driver, outputting a turn-on voltage to the plurality of gate lines in response to a gate control signal including a gate start pulse,
The second step comprises:
Wherein when the driving mode signal corresponds to the motion picture, the frequency converter of the timing controller generates a first control signal by maintaining a high frequency of the control signal, and when the driving mode signal corresponds to the still image, Changing the high frequency of the first control signal to a low frequency to generate the first control signal;
The data processing unit of the timing control unit aligns the image data in response to a high frequency of the first control signal inputted when the driving mode signal corresponds to the moving image and if the driving mode signal corresponds to the still image Converting the image data to correspond to a low frequency of the input first control signal and rearranging the converted image data;
Generating a data control signal in response to the input first control signal in a data control signal generator of the timing controller;
In response to the first control signal and the drive mode signal, the gate control signal generation unit of the timing control unit generates a gate control signal corresponding to the high frequency of the first control signal input when the drive mode signal corresponds to the moving picture, Generating the control signal so that the gate control signal corresponds to the low frequency of the first control signal inputted when the drive mode signal corresponds to the still image,
In the third step,
On voltage to the plurality of gate wirings in response to the gate control signal when the driving mode signal corresponds to the moving picture,
Wherein when the driving mode signal corresponds to the still image, one frame is divided into four first to fourth fields in response to the gate control signal, and the plurality of gate wirings are grouped into a plurality of consecutive blocks On voltage is sequentially output to the i-th gate line in each of the plurality of blocks for each field to drive the plurality of blocks in a cyclic manner, and i is a natural number of 1 to 4, Having different values
A method of driving a liquid crystal display device.
delete The method according to claim 6,
And a fourth step of generating a data voltage corresponding to the image data in response to the data control signal and outputting the data voltage to the plurality of data lines.
delete The method according to claim 6,
Wherein the high frequency of the control signal is 50 Hz or more and the low frequency of the first control signal is less than 50 Hz. The method according to claim 1,
For each of the plurality of blocks,
In the first field, the turn-on voltage is outputted to the first gate wiring among the four consecutive gate wirings,
In the second field, the turn-on voltage is outputted to the second gate wiring among the four consecutive gate wirings,
In the third field, the turn-on voltage is outputted to the third gate wiring among the four consecutive gate wirings,
In the fourth field, the turn-on voltage is outputted to the fourth gate wiring among the four consecutive gate wirings
Liquid crystal display device.
The method according to claim 1,
For each of the plurality of blocks,
In the first field, the turn-on voltage is outputted to the first gate wiring among the four consecutive gate wirings,
In the second field, the turn-on voltage is outputted to the third gate wiring among the four consecutive gate wirings,
In the third field, the turn-on voltage is outputted to the second gate wiring among the four consecutive gate wirings,
In the fourth field, the turn-on voltage is outputted to the fourth gate wiring among the four consecutive gate wirings
Liquid crystal display device.
The method according to claim 1,
For each of the plurality of blocks,
In the first field, the turn-on voltage is outputted to the first gate wiring among the four consecutive gate wirings,
In the second field, the turn-on voltage is outputted to the fourth gate wiring among the four consecutive gate wirings,
In the third field, the turn-on voltage is outputted to the second gate wiring among the four consecutive gate wirings,
In the fourth field, the turn-on voltage is outputted to the third gate wiring among the four consecutive gate wirings
Liquid crystal display device.

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