KR20120067709A - Lcd and method of driving the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a driving method thereof are provided to improve image quality by respectively controlling delay time between blocks. CONSTITUTION: A back light comprises a plurality of LEDs. The back light provides light on a liquid crystal panel. The plurality of LEDs is classified into a plurality of blocks. A timing controller creates a dimming control signal corresponding to image data signal. A lamp drive part(700) successively drives the plurality of blocks. The lamp drive part creates a PWM(Pulse Width Modulation) signal. The lamp drive part controls delay time corresponding to the PWM signal. The lamp drive part comprises a block drive part(710) and a duty control part(720).

Description

Liquid crystal display and its driving method {LCD and method of driving the same}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device for adjusting a delay time between lamp blocks in response to a PWM signal generated by a lamp driver of the liquid crystal display device.

       As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal displays (LCDs), plasma display panels (PDPs), organic fields Various flat display devices such as organic light emitting diodes (OLEDs) are being utilized.

Among these flat panel display devices, liquid crystal display devices are widely used because they have advantages of miniaturization, light weight, thinness, and low power driving. On the other hand, an active matrix type liquid crystal display device in which a plurality of pixels are arranged in a matrix form and a switching transistor is formed in each of these pixels is currently widely used.

The backlight of the liquid crystal display device is mainly a cold cathode fluorescent lamp (CCLF) type using a fluorescent tube, but environmentally friendly use of mercury has been required. For this reason, recently, a light emitting diode (LED) lamp is promising as a light source.

1 and 2 are diagrams schematically showing a delay time according to a duty ratio between blocks including a plurality of LED lamps according to the related art.

As shown in Figs. 1A and 2A, the delay time DT between each block BL has always been constant regardless of the duty ratio of each block BL.

Accordingly, as shown in FIGS. 1B and 2B, each block BL is driven regardless of the response speed LC of the liquid crystal, resulting in a motion blur phenomenon. There is this.

In addition, since the response speed LC of the liquid crystal is not sufficiently reflected, there is a problem that the image quality is deteriorated.

SUMMARY OF THE INVENTION The present invention has a problem to provide a liquid crystal display device and a driving method thereof which can improve image quality by adjusting a delay time between blocks corresponding to the duty ratio of each block composed of a plurality of lamps.

In order to achieve the above object, the present invention is a liquid crystal panel; A backlight including a plurality of LEDs divided into a plurality of blocks for providing light to the liquid crystal panel; A timing controller configured to generate a dimming control signal in response to the image data signal; And a lamp driver for sequentially driving the plurality of blocks in response to a delay time, wherein the lamp driver generates a PWM signal in response to the dimming control signal and adjusts the delay time in response to the PWM signal. Provide a display device.

The lamp driver generates a PWM signal in response to the dimming control signal, and adjusts the delay time in response to the PWM signal, and sequentially drives the plurality of blocks in response to the delay time. It includes a block driver.

The timing controller may include an image information unit configured to analyze luminance of the image data signal and generate a dimming control signal, a control signal generator configured to generate a gate control signal and a data control signal, and align the image data signal. It includes a data processing unit.

The duty information unit includes a memory for storing the PWM signal and the delay time corresponding to the dimming control signal.

A backlight including a plurality of LEDs divided into a plurality of blocks for providing light to the liquid crystal panel, a timing controller for generating a dimming control signal in response to an image data signal, and a plurality of the blocks sequentially in response to a delay time A method of driving a liquid crystal display device including a lamp driver, comprising: analyzing the luminance of the image data signal to generate the dimming control signal; Generating a PWM signal in response to the dimming control signal; A liquid crystal display driving method includes adjusting the delay time in response to the PWM signal.

The lamp driver generates a PWM signal in response to the dimming control signal, and adjusts the delay time in response to the PWM signal, and sequentially drives the plurality of blocks in response to the delay time. It includes a block driver.

The timing controller may include an image information unit configured to analyze luminance of the image data signal and generate a dimming control signal, a control signal generator configured to generate a gate control signal and a data control signal, and align the image data signal. It includes a data processing unit.

The duty information unit includes a memory for storing the PWM signal and the delay time corresponding to the dimming control signal.

The liquid crystal display device according to the present invention has an effect of improving the MPRT by adjusting the delay time of each block in response to the duty ratio of the block composed of a plurality of lamps.

Accordingly, the image quality of the liquid crystal panel is improved.

1 and 2 schematically show the duty ratio of a conventional ramp block and the delay time between the blocks.
3 is a schematic view of a liquid crystal display device according to an embodiment of the present invention;
4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
5 schematically illustrates a timing controller according to an embodiment of the present invention.
6 is a timing diagram schematically showing a lamp driver according to an embodiment of the present invention.
7 shows schematically a block of a lamp according to an embodiment of the invention;
8 and 9 are diagrams schematically showing the duty ratio of the ramp block and the delay time between the blocks according to an embodiment of the present invention.
10 is a view showing a simulation result according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

3 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention, and FIG. 4 is an equivalent circuit diagram schematically showing pixels of a liquid crystal panel according to an embodiment of the present invention.

As illustrated, the liquid crystal display device 100 according to the embodiment of the present invention includes a liquid crystal panel 200, a backlight 900, and a driver D.

The liquid crystal panel 200 includes two substrates facing each other, for example, an array substrate AS and an opposite substrate OS, and a liquid crystal layer positioned between the two substrates.

In the array substrate AS of the liquid crystal panel 200, a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction cross each other to form a matrix. A plurality of pixels P arranged in the form of) is defined.

Referring to FIG. 4, in each pixel P, a switching transistor T connected to the gate line and the data line GL and DL is formed. The switching transistor T is connected to the pixel electrode. Meanwhile, a common electrode is formed corresponding to the pixel electrode, and when voltage is applied to the pixel electrode and the common electrode, an electric field is formed between them to drive the liquid crystal. The pixel electrode, the common electrode, and the liquid crystal positioned between these electrodes constitute a liquid crystal capacitor Clc. Meanwhile, a storage capacitor Cst is further configured in each pixel P, which stores a data voltage applied to the pixel electrode until the next frame.

The backlight 900 serves to supply light to the liquid crystal panel 200.

Specifically, the backlight 900 is provided on the rear surface of the liquid crystal panel 200 to supply light from the rear surface of the liquid crystal panel 200 so that the difference in transmittance of the liquid crystal panel 200 is expressed to the outside.

Here, the backlight 900 is divided into an edge type and a direct type according to the arrangement of the light sources. In the edge type, one or a pair of light sources is disposed at one side of the light guide plate (not shown). There is one edge 1Edge having a structure, and two edges 2Edge having a structure in which two or two pairs of light sources are disposed on each side of the light guide plate 901.

In addition, there are four edges 4Edge having a structure in which four or four light sources are disposed on each of four sides of the light guide plate 901.

The direct type has a structure in which several light sources are disposed below the optical sheet (not shown).

Accordingly, in the state of active research on the lightweight thin liquid crystal display device in recent years, the edge type is more suitable for the lightweight thin liquid crystal display device than the direct type.

The backlight 900 may be a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (LED), or a light emitting diode (LED). use.

Among them, LEDs are particularly widely used as light sources for displays with features such as small size, low power consumption, and high reliability.

Here, in the embodiment of the present invention, as the backlight 900, an edge type LED 900 may be used. Hereinafter, for convenience of explanation, the LED 900 will be described as an example of the backlight 900.

The driver D includes a timing controller 300, a gate driver 400, a data driver 500, a gamma voltage supply unit 600, a lamp driver 700, a power generator 800, and It may include.

Hereinafter, the timing controller 300 according to the exemplary embodiment of the present invention will be described in more detail with reference to FIG. 5.

5 is a view schematically showing a timing controller 300 according to an embodiment of the present invention.

As shown in FIG. 5, the timing controller 300 according to the embodiment of the present invention may include a control signal generator 310, a data processor 320, and an image information unit 330.

First, the timing controller 300 enables the image data signal RGB, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the clock signal CLK, and the data enabler from an external system such as a TV system or a video card. The control signal TCS, such as the signal DE, is received. Although not shown, such signals may be input through an interface configured in the timing controller 300.

Here, the control signal generator 310 of the timing controller 300 uses the input control signal TCS to control the gate control signal GCS and the data driver 500 for controlling the gate driver 700. Generate a data control signal DCS for control.

The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The data control signal (DCS) includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), and a polarity signal (POL). It may include.

The gate start pulse (GSP) informs the start line, that is, the first line of the screen, from among 1 vertical, and the gate shift clock (GSC) is a switching transistor configured in the pixel (P) of the liquid crystal panel 200. Specify the time that (T) is on. In addition, the gate output enable signal GOE controls the output of the gate driver 400.

The source start pulse SSP informs the starting point of the data, namely, the first pixel P, in one horizontal, and the source sampling clock SSC latches the data based on the rising and falling edges. (latch) In addition, the source output enable signal SOE serves to control the output of the data driver 500, and the polarity signal POL is polarized to drive the liquid crystal in the positive (+) polarity or the negative (-) polarity. This is a signal to inform.

In addition, the data processor 320 of the timing controller 300 receives the image data signal RGB from an external system, arranges the image data signal RGB, and transmits the image data signal RGB to the data driver 500.

In addition, the image information unit 330 of the timing controller 300 receives the image data signal RGB from an external system and generates a dimming control signal DS in response thereto. In this case, it will be apparent to those skilled in the art that the image data signal RGB may be input from the data processor 320.

In addition, the image information unit 330 of the timing controller 300 transmits the generated dimming control signal DS to the lamp driver 800.

Specifically, for example, the image information unit 330 analyzes the luminance characteristic of the image data signal RGB in units of at least one frame, and according to the luminance characteristic of the analyzed image, The dimming control signal DS for adjusting the on / off time is generated and transmitted to the lamp driver 800.

That is, since the dimming duty ratio of the backlight 900 inverter is adjusted to change the luminance and the brightness according to the image data signal RGB, the duty ratio of the backlight 900 may be changed. do. In detail, for example, the dimming control signal DS may be generated to include a large amount of dimming signal in the case of the bright image data signal RGB, and to include a small dimming signal in the case of the dark image data signal RGB. .

Accordingly, for example, when the image data signal RGB is a bright image data signal RGB through luminance analysis of the image data signal RGB, the on time of the LED 900 is increased to increase the duty ratio ( duty ratio), on the other hand, in the case of a dark image data signal RGB, the duty ratio is reduced by reducing the on time of the LED 900.

The power generator 800 generates various driving voltages necessary for driving the liquid crystal display 100. For example, the power supply voltage supplied to the timing controller 300, the data driver 500, the gate driver 400, and the lamp driver 700, the gate high voltage and the gate low voltage supplied to the gate driver 400, and the like. Will generate

The data driver 500 supplies the data voltages to the plurality of data wirings DL in response to the data control signal DCS and the image data signal RGB supplied from the timing controller 300. That is, the gamma reference voltage is used to generate a data voltage corresponding to the image data RGB, and output the generated data voltage to the data wiring DL.

The gate driver 400 sequentially scans the plurality of gate wirings GL in response to the gate control signal GCS supplied from the timing controller 300. For example, a plurality of gate lines GL are sequentially selected during each frame, and a gate voltage is output to the selected gate lines GL. By the gate voltage, the switching transistor T located in the corresponding row line is turned on. On the other hand, the turn-off voltage is supplied to the gate line GL until the next frame is scanned, so that the switching transistor T is maintained in the turn-off state.

The gate driver 400 may be manufactured in an IC form and connected to the liquid crystal panel 200 or may be directly formed on the liquid crystal panel 200. The method in which the gate driver 400 is directly formed in the liquid crystal panel 200 is called a GIP (Gate In Panel) method. In such a GIP method, in the process of forming an array element including the switching transistor T, the gate wiring GL, and the data wiring DL in the liquid crystal panel 200, the gate driving unit 400 may be formed by the liquid crystal panel 200. Can be formed directly.

The gamma voltage supply unit 600 generates a gamma voltage Vgamma by dividing the high potential voltage and the low potential voltage generated from the power generator 700, and supplies the gamma voltage Vgamma to the data driver 500.

The lamp driver 700 includes a duty ratio of the backlight 900 and a plurality of LEDs 900 in response to the dimming control signal DS supplied from the timing controller 300, and logically controls the backlight 900. Adjust the delay time between the blocks. That is, the duty ratio of the plurality of LEDs 900 constituting each block is adjusted, and for example, the timing at which the blocks are turned on is adjusted.

The lamp driver 700 sequentially drives the plurality of lamps 900 in blocks in response to a delay time between blocks.

Hereinafter, the lamp driving unit 700 according to the embodiment of the present invention will be described in more detail with reference to FIG. 6.

6 is a view schematically showing a lamp driver 700 according to an embodiment of the present invention.

As illustrated in FIG. 6, the lamp driver 700 may include a block driver 710 and a duty adjuster 720.

First, the block driver 710 of the lamp driver 700 sequentially drives the plurality of lamps 900 in blocks in response to the delay time DT supplied from the duty adjuster 720. .

With reference to FIG. 7 further, the driving in units of blocks will be described in more detail.

FIG. 7 is a diagram schematically illustrating a plurality of LEDs 900 divided into a plurality of blocks.

As shown in FIG. 7, the plurality of lamps 900 are sequentially driven, for example, from the top to the bottom of the block BL. Here, the block logically divides the plurality of lamps 900 into at least one lamp in the column direction.

In this case, the plurality of blocks BL may be, for example, the first block BL1, the second block BL2, the third block BL3,. The sixth block BL6 is sequentially driven.

Here, the driving start time of each block BL is determined in response to the delay time DT received from the duty information unit 720. That is, each block BL may be driven corresponding to the delay time DT.

Specifically, for example, when the delay time DT between the blocks BL is long, the interval between the start timings of the driving of each block BL is long, whereas when the delay time DT is short, each block ( The interval at the start of the drive of BL) is short.

More specifically, for example, after the delay time DT from the start point of driving the first block BL1, the driving of the second block BL2 is started. Similarly, after the delay time DT from the start point of driving the second block BL2, the driving of the third block BL3 is started.

Here, the division into six blocks BL is an example of the present invention, and may be divided into a plurality of blocks BL, and the gate wiring GL may correspond differently to each block BL. Is apparent to those skilled in the art.

As described above, the plurality of lamps 900 are driven on and off in units of blocks BL, and thus, even without a separate partition wall, there is a partition effect not affected by light diffused between the plurality of lamps 900.

In addition, as the backlight 900 is driven by the scanning method, the motion picture response time (MPRT) value is improved, thereby improving the video quality of the liquid crystal panel 200.

Hereinafter, the duty adjustment unit 720 of the lamp driver 700 will be described in more detail.

Referring back to FIG. 6, the duty adjustment unit 720 may include a PWM generation unit 721 and.

First, the PWM generator 721 of the duty controller 720 adjusts the plurality of blocks BL to have a predetermined duty ratio in response to the dimming control signal DS supplied from the timing controller 300.

For this purpose, for example, the PWM generator 720 may include at least one memory, and may store the duty ratio corresponding to the input dimming control signal DS.

That is, the PWM generator 720 may drive the burst mode, for example, to vary the on / off time of each block BL.

Specifically, the PWM generation unit 721 generates a PWM signal pulse width modulation (PWM) in response to the dimming control signal DS.

Here, the PWM signal PWM is a square wave signal for adjusting the duty ratio of the on time and the off time of the LED 900 constituting the block BL. Therefore, the light emission time and the amount of current of the LED 900 flowing through the LED 900 are adjusted according to the on / off duty ratio of the PWM signal PWM. That is, the light emission time and the current amount of the LED 900 constituting the block BL is adjusted. Specifically, for example, the duty width when the PWM signal PWM is on is increased to increase the current and the light emission time flowing into the LED 900, and the duty width when the PWM signal PWM is on to reduce the LED. The current and the light emission time flowing into the 900 are reduced.

Therefore, as described above, for example, in the case of the bright image data signal RGB, the duty width when it is on, and in the case of the dark image data signal RGB, the duty width when it is on, is reduced.

That is, the PWM generator 721 generates the PWM signal PWM in response to the dimming control signal DS corresponding to, for example, the luminance information of the video data signal RGB.

In addition, the generated PWM signal PWM is transmitted to the delay time adjusting unit 722.

Although not shown, the PWM generator 721 converts a power signal from the outside into a DC power source. Then, the output timing of the DC power supply is controlled in accordance with the PWM signal PWM to supply the backlight 900.

Hereinafter, the delay time adjusting unit 722 according to the embodiment of the present invention will be described in more detail with reference to FIGS. 8 to 10.

8 and 9 are graphs schematically showing delay times according to duty ratios of blocks according to an embodiment of the present invention, and FIG. 10 is a simulation result tested according to an embodiment of the present invention.

The delay time adjustment unit 722 adjusts the delay time DT between the blocks BL in response to the input PWM signal PWM. That is, the delay time DT between the blocks BL is adjusted according to the duty ratio of the block BL. Also, information about the adjusted delay time DT is transmitted to the block driver 710.

To this end, for example, the delay time adjusting unit 722 may include at least one memory, and may store the delay time DT corresponding to the input PMW signal PWM.

Specifically, as shown in FIGS. 8A and 9A, in the embodiment of the present invention, the delay time DT between each block BL corresponds to the duty ratio of the block BL. Adjusted.

That is, the delay time adjustment unit 722 adjusts the delay time DT between the blocks BL in correspondence with the duty ratio of the blocks BL.

Specifically, for example, when the duty ratio of each block BL is large, that is, when the ON period of the PWM signal PWM is large, the delay time DT between the blocks BL may be small. On the other hand, when the duty ratio of each block BL is small, that is, when the ON period of the PWM signal PWM is small, the delay time DT between the blocks BL may be large.

As a result, as shown in FIGS. 8B and 9B, the blocks BL may be sequentially driven in response to the response speed LC of the liquid crystal according to each duty ratio. In addition, by sequentially driving each block BL corresponding to the response speed LC of the liquid crystal, image quality is improved.

Here, in the embodiment of the present invention, the adjustment of the delay time DT in response to the PWM signal PWM has been described as an example. However, it will be apparent to those skilled in the art that the PWM signal PWM and the delay time DT may be adjusted in response to the dimming control signal DS. To this end, a memory for storing the PWM signal PWM and the delay time DT corresponding to the dimming control signal DS may be provided.

As described above, the lamp driver 700 according to the embodiment of the present invention divides the plurality of LEDs 900 into a plurality of blocks BL logically, and scans them in units of blocks BL. Drive 900.

Further, for example, the luminance of the image data signal RGB is analyzed to generate a corresponding dimming control signal DS. In response to the generated dimming control signal DS, a PWM signal PWM is generated so that the duty ratio of each block BL can be adjusted, and the delay time DT between each block BL is also adjusted according to the duty ratio. do.

Accordingly, as shown in FIG. 10, in the embodiment of the present invention, the duty ratio and the delay time are adjusted in response to the response speed LC of the liquid crystal, thereby improving the image quality of the liquid crystal panel 200. to provide. In addition, MPRT also provides an improved effect.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and their equivalents.

300: timing controller 310: control signal generator 320: data processor
330: Image information unit 700: Lamp driver 710: Block driver
720: duty controller 721: PWM generator 722: delay time controller
PWM: PWM Signal DS: Dimming Control Signal

Claims (8)

A liquid crystal panel;
A backlight including a plurality of LEDs divided into a plurality of blocks for providing light to the liquid crystal panel;
A timing controller configured to generate a dimming control signal in response to the image data signal;
It includes a ramp driver for sequentially driving a plurality of the blocks corresponding to the delay time,
The lamp driver generates a PWM signal in response to the dimming control signal,
Adjusting the delay time in response to the PWM signal
LCD display device.
The method of claim 1,
The lamp driving unit includes:
A duty information unit generating the PWM signal in response to the dimming control signal and adjusting the delay time in response to the PWM signal;
It includes a block driver for sequentially driving the plurality of blocks in response to the delay time
LCD display device.
The method of claim 1,
The timing control unit,
An image information unit for analyzing the luminance of the image data signal and generating a dimming control signal corresponding thereto;
A control signal generator for generating a gate control signal and a data control signal;
And a data processor to align the image data signal.
LCD display device.
The method of claim 2,
The duty information unit,
And a memory configured to store the PWM signal and the delay time corresponding to the dimming control signal.
LCD display device.
A backlight including a plurality of LEDs divided into a plurality of blocks for providing light to the liquid crystal panel, a timing controller for generating a dimming control signal in response to an image data signal, and a plurality of the blocks sequentially in response to a delay time In the liquid crystal display device driving method comprising a drive unit for driving the lamp,
Analyzing the luminance of the image data signal to generate the dimming control signal;
Generating a PWM signal in response to the dimming control signal;
Adjusting the delay time in response to the PWM signal;
Liquid crystal display driving method.
The method of claim 5, wherein
The lamp driving unit includes:
A duty information unit generating the PWM signal in response to the dimming control signal and adjusting the delay time in response to the PWM signal;
It includes a block driver for sequentially driving the plurality of blocks in response to the delay time
Liquid crystal display driving method.
The method of claim 5, wherein
The timing control unit,
An image information unit for analyzing the luminance of the image data signal and generating a dimming control signal corresponding thereto;
A control signal generator for generating a gate control signal and a data control signal;
And a data processor to align the image data signal.
Liquid crystal display driving method.
The method according to claim 6,
The duty information unit,
And a memory configured to store the PWM signal and the delay time corresponding to the dimming control signal.
Liquid crystal display driving method.

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