KR102038992B1 - Display device and method for driving the same - Google Patents

Abstract

According to the present invention, a panel including gate lines and data lines intersecting each other to define a pixel, and dividing a frame into K fields, and K horizontally with respect to the sequence of gate lines in which the remainder divided by K in each field is j The gate driver for supplying the gate signal sequentially every cycle-K is a natural number of 2 or more, j has a natural value of 0 or less than K, and has a different value in each field-and outputs a data voltage every K horizontal periods for the data lines. A display device including a data driver is provided.

Description

DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to a display device and a method of driving the display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal displays (LCDs), plasma display panels (PDPs), organic fields Various flat panel display devices such as organic light emitting diode display devices (OLEDs) are being utilized.

Such a display device may include a panel displaying an image through a pixel defined by the intersection of the gate lines and the data lines. In the panel, the display device supplies a signal to the gate lines so that each data line is connected to the pixel. In addition, the display device displays an image on each pixel by applying a data voltage obtained by converting the image data to data lines connected to the pixel.

In this case, a data voltage may be applied to the data lines at a time when a signal is not supplied to the gate lines. For example, when a touch is sensed in an area adjacent to each pixel after displaying an image in each pixel, a signal may not be supplied to the gate lines during the time of sensing the touch. When a change in the data voltage occurs during this non-scan time, power consumption of the display device may increase. When not connected to a pixel, the data lines may appear to be capacitive loads rather than resistive loads, where voltage fluctuations and frequencies determine power consumption. When unnecessary data voltage fluctuation occurs during the scan time, power consumption of the display device is increased.

In this background, an object of the present invention is to provide a technique for reducing power consumption of a display device by minimizing a change in data voltage at non-scanning time in one aspect.

In another aspect, an object of the present invention is to provide a technique for supplying a data voltage to data lines at a period in which a gate signal is supplied to a gate line.

In another aspect, an object of the present invention is to provide a data voltage output technique for low frequency driving in image data for high frequency driving.

In order to achieve the above object, in one aspect, the present invention provides a panel comprising gate lines and data lines that cross each other to define a pixel, divided one frame into K fields, divided by K in each field. A gate driver for sequentially supplying a gate signal every K horizontal periods to a sequence of gate lines where the remainder is j, where K is a natural number of 2 or more, j is a natural number of 0 or less than K, and has different values in each field; and A display device includes a data driver configured to output a data voltage every K horizontal periods with respect to the data lines.

In another aspect, the present invention relates to a method of driving a display device including gate lines and data lines that define pixels by crossing each other, wherein one frame is divided into K fields, and the remainder divided by K in each field. Sequentially supplying a gate signal every K horizontal periods for the gate lines in which j is k, where K is a natural number of 2 or more, j is a natural number of 0 or less than K, and has different values in each field. A display device driving method includes outputting a data voltage every K horizontal periods with respect to lines.

As described above, according to the present invention, the power consumption of the display device can be reduced by minimizing the fluctuation of the data voltage at the non-scan time. In addition, according to the present invention, the data voltage may be supplied to the data lines in accordance with the period in which the gate signal is supplied to the gate line, and the data voltage for low frequency driving may be output from the image data for high frequency driving. As a result, power consumption of the display device may be reduced.

1 is a block diagram of a display device according to an exemplary embodiment.
2 is a block diagram illustrating a data driver of a display device according to an exemplary embodiment.
3 is a view showing signal waveforms driven by 60 Hz.
4 is a diagram for explaining four-field division driving and scan / touch driving.
5A to 5D are diagrams showing signal waveforms in four-field division driving.
6 is an exemplary diagram of signal waveforms that output data voltages every four horizontal periods in four-field division driving.
7A to 7D are other exemplary diagrams of signal waveforms that output data voltages every four horizontal periods in four-field division driving.
8 is a comparison diagram of a signal waveform outputting a data voltage in one horizontal period and a signal waveform outputting a data voltage in four horizontal periods in four-field division driving.
9 is a circuit diagram for describing power consumption of a capacitive load.
10 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are assigned to the same components as much as possible even though they are shown in different drawings. In addition, in describing the embodiments of the present invention, if it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

In addition, in explaining the component of this invention, terms, such as 1st, 2nd, A, B, (a), (b), can be used. These terms are only for distinguishing the components from other components, and the nature, order or order of the components are not limited by the terms. If a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected to or connected to that other component, but there may be another configuration between each component. It is to be understood that the elements may be "connected", "coupled" or "connected". In the same context, when a component is described as being formed "on" or "under" another component, that component is both formed directly on the other component or indirectly through another component. It should be understood to include.

1 is a block diagram of a display device 100 according to an exemplary embodiment.

Referring to FIG. 1, the display device 100 may include a panel 110, a data driver 120, and a gate driver 130. In addition, the display device 100 may further include a timing controller 140 according to the configuration of the embodiment. Hereinafter, an exemplary embodiment in which the display device 100 includes the timing controller 140 will be described.

The timing controller 140 controls the data driver 120 based on external timing signals such as vertical / horizontal synchronization signals Vsync and Hsync and image data RGB and clock signal CLK input from a host system (not shown). The data control signal DCS for controlling the control signal and the gate control signal GCS for controlling the gate driver 130 may be output.

In addition, the timing controller 140 converts the image data RGB input from the host system (not shown) into a data signal format used by the data driver 120 and converts the converted image data R'G'B '. The data driver 120 may supply the data. For example, the timing controller 140 may supply the image data R′G′B ′ that is converted according to the resolution or pixel structure of the panel 110 to the data driver 120. The image data RGB and the converted image data R'G'B 'may also be referred to as image signals, image digital data, or data.

The data driver 120 converts the converted image data R'G'B 'in response to the data control signal DCS and the converted image data R'G'B' input from the timing controller 140. The data voltage is converted into a data voltage (analog pixel signal or data signal) which is a voltage value corresponding to the gray scale value and supplied to the data line.

The gate driver 130 sequentially supplies a gate signal (a scan signal, a gate pulse, a scan pulse, or a gate on signal) to the gate line in response to the gate control signal GCS input from the timing controller 140.

The panel 110 includes a plurality of pixels Px, Px + 1, and Px + 2 defined by the intersection of the plurality of gate lines GL1 to GLm and the plurality of data lines DL1 to DLn.

Each pixel may have a different structure depending on the image display method of the panel 110. For example, when the panel 110 displays an image according to a liquid crystal display method, the pixel may have a structure in which a liquid crystal is included between both electrodes.

As another example of the pixel, when the panel 110 displays an image according to an organic electroluminescence method, the pixel includes at least one of an anode as a first electrode, a cathode as a second electrode, and a light emitting layer. An organic electroluminescent device may be included. The light emitting layer included in each organic light emitting diode may include at least one light emitting layer or a white light emitting layer among red, green, blue, and white light emitting layers.

A gate line GLy and a data line DLx are connected to each pixel of the panel 110, and a switching transistor positioned between the gate line GLy and the data line DLx may be formed. The gate driver 130 supplies a gate signal to the gate line GLy to turn on the switching transistor so that the data line DLx can be connected to the pixel. In addition, a data voltage output from the data driver 120 is applied to the pixel connected to the data line DLx to display an image.

The data driver 120 receives image data received from the timing controller 140 using a reset signal RESET and an output enable signal SOE among the data control signals DCS from the timing controller 140. Convert (DATA) to data voltage and output.

2 is a block diagram illustrating a data driver 120 of the display device 100 according to an exemplary embodiment.

Referring to FIG. 2, the data driver 120 may include a shift register 210, a latch unit 220, a data register 230, a converter 240, an output unit 250, and the like.

The shift register 210 generates a sampling signal that induces the serially input image data to be sequentially sampled and stored in the latch unit 220 and sequentially supplies the sampling signal to the latch unit 220.

The data register 230 temporarily stores the image data DATA supplied from the timing controller 140 and transfers the image data DATA to the latch unit 220. The latch unit 220 sequentially samples the image data transmitted through the data register 230 in accordance with the sampling signal from the shift register 210. At this time, the latch unit 220 stores the sampled data according to the reset signal in units of one horizontal line, and simultaneously outputs the image data stored in units of one horizontal line to the converter 240 in response to the SOE signal.

The latch unit 220 may be divided into a first latch and a second latch according to an embodiment. The first latch may be serially input through the data register 230 according to a clock sequentially supplied from the shift register 210. The sampled image data is sampled and stored, and the stored image data is simultaneously output to the second latch. The second latch stores the image data supplied from the first latch, and then simultaneously outputs the stored image data to the converter 240 in response to the SOE signal.

The converter 240 converts the image data into a data voltage and simultaneously outputs the converted data voltage of one horizontal line to the output unit 250. In this case, the data voltage may be a gamma reference voltage.

The output unit 250 has an output buffer and outputs data voltages formed in the output buffer through the data lines. In this case, the output unit 250 may amplify and output the data voltage to prevent the data voltage from being distorted by the RC time constant of the data lines.

A sequence in which the data driver 120 receives image data and outputs a data voltage will be described with reference to a signal waveform diagram.

3 is a view showing signal waveforms driven by 60 Hz.

Referring to FIG. 3, a gate signal waveform is displayed at the top and a signal waveform related to the data drive is displayed at the bottom to indicate a relationship in which the data voltage is applied to the pixel according to the gate driving. First, the signal waveform related to data driving will be described first.

Image data transmitted from the host system to the timing controller 140 together with the data enable signal DE are transferred from the timing controller 140 to the data driver 120 without being converted or converted. Such image data includes data corresponding to one horizontal line within one horizontal period. In FIG. 3, the waveform indicated by DE may be understood as inputting data corresponding to one horizontal line to the data driver 120 within one horizontal period.

Referring to FIG. 3, image data corresponding to the first horizontal line 1H is input through the data register 230 in the first horizontal period. The first horizontal line 1H image data input as described above is stored in the latch unit 220 according to the reset signal. The first horizontal line 1H image data stored in the latch unit 220 is output according to the SOE signal, converted into a data voltage through the converter 240, and then output to the output unit 250. In this case, the output unit 250 includes an output buffer and maintains the data voltage output through the output buffer for a predetermined time within one horizontal period.

The data voltage for the first horizontal line 1H output from the output unit 250 is output in a second horizontal period, which is the next horizontal period. FIG. 3 illustrates that a data voltage corresponding to the first horizontal line 1H is output from the j-th data line DLj of the data lines.

A gate signal (gate pulse) is supplied to a gate line Gate1 interlocked with the pixels of the first horizontal line in a second horizontal period in which the data voltage of the first horizontal line 1H is output through the data lines. . The pixels of the first horizontal line are connected to the data lines according to the gate signal supplied through the gate line 1 (Gate1). The data of the first horizontal line 1H is the data lines while the pixels and the data line are connected. The voltage is supplied to display an image on the first horizontal line pixels.

During the second horizontal period in which the output unit 250 outputs the data voltage for the first horizontal line 1H, the latch unit 220 erases the data stored according to the reset signal and inputs the second horizontal line 2H. Save the image data for). When the SOE signal is input to the data driver 120, the image data for the second horizontal line 2H is converted into a data voltage and output through the output unit 250 in the next third horizontal period. In addition, the gate signal (gate pulse) is applied to the gate line Gate 2 which is interlocked with the pixels of the second horizontal line so that the data voltage of the second horizontal line 2H output in the third horizontal period is transferred to the pixels. Supplied.

In the same manner, the data voltages of the third horizontal line 3H to the eighth horizontal line 8H are supplied to the pixels through the data lines, and the gate lines Gate 3 to the gate are linked to the pixels of the corresponding horizontal line. The gate signal is sequentially supplied to the line 8 (Gate8).

In this manner, the image display for the entire horizontal line can be driven at 60 Hz. Since 60 Hz is 16.67 ms in time, the image display for the entire horizontal line in the 60 Hz driving can be performed within 16.67 ms.

The display device 100 may be driven at a high frequency (for example, a frequency of 50 Hz or more) in order to express high definition on the panel 110. However, such high frequency driving may have a disadvantage of increasing power consumption of the display device 100. Accordingly, when high frequency driving is not required, such as a still image, the display device 100 may drive low frequency (eg, less than 50 Hz) to reduce power consumption.

The field division driving method may be used as the low frequency driving method of the display device 100. Hereinafter, low frequency driving using such field division driving will be described. In the following embodiments, the four-field division driving will be described, but the present invention is not limited to such four-field division driving. For example, the display device 100 may drive K-field division. Here, K is a natural number of 2 or more.

4 is a diagram for explaining four-field division driving and scan / touch driving.

FIG. 4A shows that one frame is divided into four fields and driven at 15 Hz. Referring to FIG. 4A, one frame outputted at a period of 15 Hz (66.68 ms) may be divided into four fields. In each field, the gate signal is supplied to gate lines of the same order, the remainder of which is divided by four. In more detail, gate signals are sequentially supplied to gate lines (eg, gate line 1 and gate line 5) in which the remainder divided by 4 in the first field is 1 (eg, gate line 1 and gate line 5). The gate signal is sequentially supplied to gate lines (eg, gate line 2 and gate line 6) in which the remainder divided by 4 in the second field, which is the next sequence of the first field, is two. Subsequently, the gate signals are sequentially supplied to the gate lines (for example, gate line 3 and gate line 7) in which the remainder divided by 4 in the third field is 3, and in the fourth field. The gate signals are sequentially supplied to the gate lines in sequence (eg, gate line 4 and gate line 8) having a remainder divided by four.

As one frame is divided into four fields and driven at a low frequency, a longer time for sensing a touch can be obtained through a non-scan time in which a gate signal is not applied.

4B is a sequence diagram illustrating that a non-scan time for sensing a touch is inserted between scan times to which a gate signal is applied. Referring to FIG. 4B, the gate signal is supplied at intervals of four horizontal periods according to four-field division driving. In this case, the gate signal is supplied at one horizontal period among the four horizontal periods, and the touch is applied within the remaining three horizontal periods. Can be sensed. If the time for recognizing the touch is long, there is an effect of improving the sensitivity of the touch.

5A to 5D are diagrams showing signal waveforms in four-field division driving.

Referring to FIG. 5A, a gate signal is supplied to gate line Gate 1 and gate line 5 having a remainder divided by 4 in the first field. The gate signal is not supplied to the gate lines (not shown) whose division divided by 4 in FIG. 5A is not 1. Each gate signal is supplied at four horizontal period intervals. In this case, touch sensing may be performed during the non-scan time when the gate signal is not supplied.

The image data transferred from the host system to the data driver 120 through the timing controller 140 may be data having the same period as the 60 Hz driving shown in FIG. 3 regardless of the 15 Hz 4 field division driving. The host system can transmit the image data to a system such as a TV system or a video card independently of the driving of the display device 100. Accordingly, even if the display device 100 performs a four-field division driving of 15 Hz, the image data is driven at 60 Hz. It may be the same period of data.

5A, as described with reference to FIG. 3, image data of the first horizontal line 1H input to the data driver 120 in the first horizontal period is stored in the latch unit 220 and then SOE. The signal is converted along with the signal and output to the data lines in a second horizontal period in the form of a data voltage. The data voltage for the first horizontal line 1H thus output is supplied to the pixels of the first horizontal line connected to the data lines by the gate signal supplied to the gate signal Gate1 to display an image on the corresponding pixel. do.

Image data supplied every horizontal period is continuously converted to a data voltage and output. Accordingly, data voltages for the second horizontal line 2H are output to the data lines in the third horizontal period. However, at this time, since the gate signal is not supplied to the gate line Gate2, the data voltages supplied to the data lines in the third horizontal period are not transferred to the pixel. Similarly, the data voltages for the third and fourth horizontal lines 3H and 4H and the data voltages for the sixth and sixth horizontal lines 6H to 8H are not transferred to the pixel. In the first field, the data voltage for the first horizontal line 1H and the data voltage for the fifth horizontal line 5H are supplied to the first horizontal line pixel and the fifth horizontal line pixel, respectively.

5B is a diagram illustrating signal waveforms in a second field. Referring to FIG. 5B, data voltages of a second horizontal line 2H and a sixth horizontal line 6H supplied to a horizontal period in which a gate line is driven are determined. The second horizontal line pixels and the sixth horizontal line pixels are respectively supplied.

Similarly, referring to FIG. 5C, which is a diagram illustrating signal waveforms in a third field, data voltages for the third and seventh horizontal lines 3H and 7H, which are supplied to the horizontal period in which the gate line is driven, are respectively set to third. The horizontal line pixels and the seventh horizontal line pixels are supplied. Referring to FIG. 5D corresponding to the fourth field, data voltages of the fourth horizontal line 4H and the eighth horizontal line 8H, which are supplied to the horizontal period in which the gate line is driven, are respectively different from the fourth horizontal line pixel. It is supplied to the eighth horizontal line pixel.

Changing the output of the data voltage when the data line is not connected to the pixel may be a factor in increasing the power consumption of the display device 100. In particular, as shown in FIGS. 5A to 5D, in a horizontal pattern (Horizontal Patten) having a large variation in the data voltage, the waste of power consumption may appear larger.

The display device 100 according to an exemplary embodiment may maintain the output of the data voltage at a non-scan time when the gate signal is not supplied to the gate line. In addition, the display device 100 may supply the data voltage to the data lines in accordance with a period in which the gate signal is supplied to the gate line. In addition, the display device 100 outputs a data voltage output (for example, an output period of the data voltage) for driving a low frequency (for example, 15 Hz) from image data for driving a high frequency (for example, 60 Hz). Matching).

6 is an exemplary diagram of signal waveforms that output data voltages every four horizontal periods in four-field division driving. FIG. 6 shows a first field of four fields, and it can be understood that other fields are applied in the same manner as the first field.

Referring to FIG. 6, as illustrated in FIG. 3, image data of all horizontal lines is sequentially input to the data driver 120 every horizontal period.

In this case, the input image data is selected at intervals of 4 horizontal periods, and the selected image data is converted into data voltages and output at intervals of 4 horizontal periods. The data driver 220 converts the image data into data voltages at four horizontal periods and outputs the selected image data every four horizontal periods. The data driver 220 may convert the image data stored in the latch unit 220 into a data voltage according to the SOE signal, and output the data voltage. The SOE signal is received every four horizontal periods, so that the data driver 220 is spaced four horizontal periods apart. Image data can be converted and output.

In detail, the data driver 120 receives image data every horizontal period and stores the image data in the latch unit 220 according to a reset signal every horizontal period. In the first horizontal period, the image data for the first horizontal line 1H is stored in the latch unit 220. The image data stored in the latch unit 220 is converted into a data voltage according to the SOE signal and output to the output unit 250. The data voltage output to the output unit 250 may maintain its output value through the output buffer in the second horizontal period.

Subsequently, the image data for the second horizontal line 2H is stored in the latch unit 220 in the second horizontal period. However, since the SOE signal is not received in the second horizontal period, the output unit 250 continuously maintains the data voltage for the first horizontal line 1H. Since the SOE signal is not received in the third and fourth horizontal periods, the output unit 250 continuously maintains the data voltage for the first horizontal line 1H.

The SOE signal is received again in the fifth horizontal period, which becomes the four horizontal periods, and outputs the data voltage for the fifth horizontal line 5H stored in the latch unit 220 to the output unit 250. Since SOE is not received even in the sixth to eighth periods, the output unit 250 maintains the data voltage for the fifth horizontal line 5H until the eighth horizontal period.

As a result, the data driver 120 converts the image data input every one horizontal period into a data voltage according to the output enable signal SOE received at four horizontal period intervals.

In this case, the data voltage output every four horizontal periods is a data voltage obtained by converting image data corresponding to a pixel turned on by the gate signal. Referring to FIG. 6, the SOE is received in conjunction with a gate line to which a gate signal is supplied. For example, before the gate signal is supplied to the gate line 1, the SOE is received to latch image data for the first horizontal line. The output unit 250 outputs the output unit 250 to the output unit 250.

7A to 7D are other exemplary diagrams of signal waveforms that output data voltages every four horizontal periods in four-field division driving.

7A shows signal waveforms in the first of four fields. Referring to FIG. 7A, a gate signal is supplied to gate line 1 and gate line 5 having a remainder divided by 4 in the first field. The gate signal is not supplied to the gate lines (not shown) where the remainder divided by 4 in FIG. 7A is not 1.

Referring to FIG. 7A, the latch unit 220 selects and stores image data every four horizontal cycles with respect to image data input every one horizontal cycle. In addition, the data driver 120 converts the stored image data into a data voltage according to the SOE signal received at four horizontal period intervals and outputs the converted data voltage. Through this, the data driver 120 selects the input image data at intervals of 4 horizontal periods, converts the selected image data into data voltages, and outputs the data at every 4 horizontal cycles.

In detail, the data driver 120 receives image data every horizontal period and stores the image data in the latch unit 220 according to a reset signal received or generated every four horizontal periods. In the first horizontal period, the image data for the first horizontal line 1H is stored in the latch unit 220. The image data stored in the latch unit 220 is converted into a data voltage according to the SOE signal and output to the output unit 250. The data voltage output to the output unit 250 may maintain its output value through the output buffer in the second horizontal period.

Subsequently, the image data for the second horizontal line 2H is received in the second horizontal period, but the reset signal is not received or generated, so the latch unit 220 continuously stores the previous image data. Since the reset signal is not received or generated in the third and fourth horizontal periods, the latch unit 220 continues to store the image data for the first horizontal line 1H until the fourth horizontal period.

Since the SOE signal is not received in the second to fourth horizontal periods, the output of the output unit 250 is also maintained at the data voltage for the first horizontal line 1H.

In the fifth horizontal period, image data for the fifth horizontal line 5H is stored in the latch unit 220. The image data stored in the latch unit 220 is converted into a data voltage according to the SOE signal and output to the output unit 250. The data voltage output to the output unit 250 may maintain its output value through the output buffer in the sixth horizontal period.

Subsequently, since the reset signal is not received or generated in the sixth to eighth periods, the latch unit 220 stores the image data for the fifth horizontal line 5H, which is the previous image data.

Since the SOE signal is not received in the sixth to eighth periods, the output of the output unit 250 is also maintained at the data voltage for the fifth horizontal line 5H.

7B is a diagram illustrating signal waveforms in a second field. Referring to FIG. 7B, a reset signal and an SOE signal are received or generated in a second horizontal period and not received or generated in a third horizontal period to a fifth horizontal period. . Accordingly, the data voltage for the second horizontal line 2H is continuously maintained as an output from the third horizontal period to the sixth horizontal period in which the gate signal for the second horizontal line is generated.

Similarly, referring to FIG. 7C, which illustrates signal waveforms in the third field, the reset signal and the SOE signal are received or generated in the third horizontal period and not received or generated in the fourth to sixth horizontal periods. Accordingly, the data voltage for the third horizontal line 3H is continuously maintained as an output from the fourth horizontal period to the seventh horizontal period in which the gate signal for the third horizontal line is generated.

Referring to FIG. 7D, which is a diagram illustrating signal waveforms in a fourth field, the reset signal and the SOE signal are received or generated in the fourth horizontal period and not received or generated in the fifth to seventh horizontal periods. Accordingly, the data voltage for the fourth horizontal line 4H is continuously maintained as an output from the fifth horizontal period to the eighth horizontal period in which the gate signal for the fourth horizontal line is generated.

7A to 7D, the display apparatus 100 continuously maintains the previous data voltage output during the non-scan time when the gate signal is not supplied.

8 is a comparison diagram of a signal waveform outputting a data voltage in one horizontal period and a signal waveform outputting a data voltage in four horizontal periods in four-field division driving.

Referring to the upper graph of FIG. 8, the data voltage output to the DLj data line is changed every one horizontal period. Accordingly, four voltage variations occur from the third horizontal period at which the gate signal is output to the gate line 1 (Gate1) to the seventh horizontal period at which the gate signal is output to the gate line 5 (Gate1).

In contrast, referring to the lower graph of FIG. 8, the data voltage output to the DLj data line is changed every four horizontal periods, and the gate line 5 (Gate1) is performed from the third horizontal period at which the gate signal is output to the gate line 1 (Gate1). ), No voltage fluctuation occurs until the seventh horizontal period at which the gate signal is output.

In the display device 100, the data lines may have a capacitive load (capacitive load) in relation to other wirings (eg, common electrode wiring or touch sensing line). In addition, the output unit 250 outputting the data voltage to the data lines may have a capacitor in the output buffer. Unlike resistive loads, such capacitive loads increase power consumption as voltage fluctuates.

9 is a circuit diagram for describing power consumption of a capacitive load.

The amount of charge Q stored in the capacitive load is represented by the product of the capacitance C and the voltage V. The current I flowing into the capacitive load is represented by the rate of change of the charge amount Q. At this time, if the capacitance is constant, the rate of change dQ of the charge amount is proportional to the rate of change dV of the voltage, and the power P expressed as the product of the current I and the voltage V eventually becomes the voltage V It is expressed as being proportional to the product of the rate of change (dV) of the voltage. This is expressed as a formula as follows.

[Equation 1]

Q = C x V

I = dQ / dt = d (CV) / dt = C x dV / dt

P = I x V = C x V x dV / dt

Referring to Equation 1, it can be seen that the data driver 120 having the capacitive load consumes more power when the voltage variation dV is large. The display device 100 according to the exemplary embodiment reduces the voltage variation dV by maintaining the data voltage constant at a non-scan time when the data line is not connected to the pixel. As a result, the power consumption of the display device 100 is reduced. When the embodiment described with reference to FIGS. 7A through 7D of the present invention is applied to a horizontal pattern having a large variation in data voltage, power consumption is reduced by about 24%.

Meanwhile, as described above, the 15 Hz driving or the four field division driving is only one example, and the present invention is not limited thereto. For example, the display device 100 can perform 7.5Hz 8 field division driving. In this case, the data driver 120 may maintain the output of the data voltage for eight horizontal periods.

In the above, the display apparatus 100 according to the exemplary embodiment of the present invention has been described. Hereinafter, a method of driving the display apparatus 100 according to the exemplary embodiment of the present invention will be described. The above-described embodiments of the display apparatus 100 may be applied to the following method of driving the display apparatus 100 as long as the embodiments do not contradict each other.

10 is a flowchart illustrating a method of driving the display device 100 according to an exemplary embodiment.

Referring to FIG. 10, the display device 100 including gate lines and data lines that cross a pixel to define pixels receives image data from a host system and transfers the received image data to the data driver 120 ( S1000). In this case, the image data may include data for one horizontal line every one horizontal period.

In operation S1010, the display apparatus 100 divides one frame into K fields, and sequentially supplies gate signals for every K horizontal periods to gate lines of the order in which the remainder divided by K in each field is j. K is a natural number of 2 or more, j is a natural number of 0 or less than K, and has different values in each field. For example, j may be 2 in the first field, j may be 0 in the second field, j may be 3 in the third field, and j may be 1 in the fourth field.

The gate signal supplied to the gate line may be a gate pulse within one horizontal period. For example, for four-field division driving, the gate signal is sequentially supplied every four horizontal periods, but the gate pulse period in which the data lines are connected to the pixel may be within one horizontal period. The touch may be sensed in the remaining three horizontal periods during which no gate pulse is generated during the four horizontal periods.

The display apparatus 100 outputs a data voltage every K horizontal periods with respect to the data lines (S1020). In this case, the output data voltage is a conversion value of the image data for the pixel connected by the gate line. In other words, the display device 100 outputs a data voltage obtained by converting image data corresponding to a pixel turned on by the gate signal every K horizontal periods. For example, when a gate signal for the first horizontal line 1H is applied, the data voltage output for the data lines is the data voltage for this first horizontal line 1H.

The data voltage output to the data lines can remain substantially constant during the K horizontal period.

Meanwhile, in the data voltage output step S1020, the display apparatus 100 may select image data input every one horizontal cycle at intervals of K horizontal cycles, and convert the selected image data into data voltages and output the converted data voltage. In this case, the display device 100 may convert the image data into a data voltage according to an output enable signal (SOE) received at intervals of K horizontal periods and output the converted data voltage.

In addition, in the data voltage output step S1020, the display apparatus 100 stores image data input every one horizontal cycle according to a reset signal received or generated at a K horizontal cycle interval, and is received at a K horizontal cycle interval. The stored image data may be converted into a data voltage and output according to the enable signal SOE. The reset signal or the SOE signal may be generated by the timing controller 140 of the display device 100.

The terms "comprise", "comprise" or "having" described above mean that a corresponding component may be included unless specifically stated otherwise, and thus does not exclude other components. It should be construed that it may further include other components. All terms, including technical and scientific terms, have the same meanings as commonly understood by one of ordinary skill in the art unless otherwise defined. Terms commonly used, such as terms defined in a dictionary, should be interpreted to coincide with the contextual meaning of the related art, and shall not be construed in an ideal or excessively formal sense unless explicitly defined in the present invention.

The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and changes without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

Claims (10)

A panel comprising gate lines and data lines crossing each other to define a pixel;
A gate driver for dividing a frame into K fields and sequentially supplying a gate signal for every K horizontal periods to the gate lines of a sequence of j divided by K in each field, where K is a natural number of 2 or more, and j is 0. Or have a different value in each field with a natural number less than K; And
A data driver for outputting a data voltage every K horizontal periods with respect to the data lines, and maintaining a supply of a data voltage corresponding to one image data during K horizontal periods;
And a non-scan time during (K-1) horizontal periods between the horizontal periods to which the gate signal is supplied, wherein touch sensing is performed at the non-scan time.
The method of claim 1,
The data driver,
And selecting the input image data at intervals of the K horizontal period, and converting the selected image data into a data voltage and outputting the converted data voltage.
The method of claim 1,
The data driver,
And converting the input image data into a data voltage according to an output enable signal (SOE) received at intervals of K horizontal periods.
The method of claim 1,
The data driver,
Image data input every 1 horizontal period is stored according to the reset signal received or generated at K horizontal cycle intervals, and data stored according to the output enable signal (SOE, Source Output Enable) received at the K horizontal cycle intervals. And a display device converting the voltage to output the voltage.
The method of claim 1,
And a data voltage output at each of the K horizontal periods is a data voltage obtained by converting image data corresponding to a pixel turned on by the gate signal.
A method of driving a display device including gate lines and data lines crossing each other to define a pixel, the method comprising:
Dividing a frame into K fields, and sequentially supplying a gate signal every K horizontal periods for the gate lines of the order in which the remainder divided by K in each field is j, where K is a natural number of 2 or more, and j is 0 or Have a different value in each field with a natural number less than K; And
Outputting a data voltage every K horizontal periods with respect to the data lines, and maintaining a supply of a data voltage corresponding to one image data for K horizontal periods;
And a non-scan time during (K-1) horizontal periods between the horizontal periods to which the gate signal is supplied, wherein touch sensing is performed at the non-scan time.
The method of claim 6,
In the data voltage output step,
And selecting the input image data at intervals of the K horizontal period and converting the selected image data into a data voltage and outputting the converted data voltage.
The method of claim 6,
In the data voltage output step,
And converting the input image data into a data voltage according to an output enable signal (SOE, Source Output Enable) received or generated at intervals of K horizontal periods.
The method of claim 6,
In the data voltage output step,
Image data input every 1 horizontal cycle is stored according to the reset signal received or generated at K horizontal cycle intervals, and stored according to the output enable signal (SOE, Source Output Enable) received or generated at K horizontal cycle intervals. And converting the data into a data voltage to output the data voltage.
The method of claim 6,
In the data voltage output step,
And outputting a data voltage obtained by converting image data corresponding to a pixel turned on by the gate signal every K horizontal periods.

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