KR102503786B1 - Device for digital driving based on subframe and display device comprising thereof - Google Patents

Abstract

The present invention relates to a timing controller, which is a device for generating control signals for each subframe according to multi-addressing, and a display device including the timing controller. A subframe conversion unit that converts, a multi-addressing control unit that overlaps sections of a plurality of subframes, and a data line control that generates K data enable signals for controlling addressing in the overlapped subframe sections and applies them to the data driver. A timing controller including a signal generator and a gate line control signal generator for controlling addressing in overlapping subframe sections, generating K vertical synchronization signals and applying them to a gate driver, and a display device including the timing controller are presented.

Description

Digital driving device based on subframe and display device including the same {DEVICE FOR DIGITAL DRIVING BASED ON SUBFRAME AND DISPLAY DEVICE COMPRISING THEREOF}

The present invention relates to a digital driving device based on a subframe and a display device implementing the same.

A display device (or display device) is a device that visually displays data, such as a liquid crystal display, an electrophoretic display, an organic light emitting display, and an inorganic EL display. , (Electro Luminescent Display), Field Emission Display, Surface-conduction Electron-emitter Display, Plasma Display, and Cathode Ray, display), etc.

A liquid crystal display device (LCD) is an electronic device that converts various electrical information generated from various devices into visual information by using a change in liquid crystal transmittance according to an applied voltage and transmits it. The liquid crystal display has the advantages of mass production possibility, ease of driving means, realization of high image quality, and realization of a large-area screen, and is widely used as an alternative means that can overcome the disadvantages of the conventionally used CRT (Cathode Ray Tube). am.

Meanwhile, in an organic light emitting display device, a light emitting layer is formed between two different electrodes, and when electrons generated from one electrode and holes generated from the other electrode are injected into the light emitting layer, the injected electrons and holes are combined to form axcitons. A display device that displays an image by emitting light while the generated exciton falls from an excited state to a ground state, and can realize low-power driving, thin structure, and excellent image quality .

The above-described display devices may apply a digital driving method in which grayscales are divided into subframes and driven when displaying one image. On the other hand, subframe driving is divided into an addressing period and an emission period, and when these subframes are overlapped, it is possible to scan several times, so time can be efficiently used. Accordingly, there is a need for a method of overlapping and driving subframes and a display device implementing the method.

The present invention proposes a method of independently providing a control signal for each subframe in multi-addressing driving.

The present invention proposes a method of independently providing a signal to be applied to a gate line, such as a vertical synchronization signal, for each subframe in multi-addressing driving.

The present invention proposes a method of independently providing a signal to be applied to a data line, such as a data enable signal, for each subframe in multi-addressing driving.

A display device according to an embodiment of the present invention includes a display panel, a gate driver, a data driver, and a timing controller generating control signals for each subframe according to multi-addressing.

A display device according to another embodiment of the present invention includes a timing controller that converts a frame period into K subframes and overlaps them to perform multi-addressing.

A display device according to another embodiment of the present invention includes a timing controller that performs multi-addressing, and the timing controller converts one frame period into K subframes each including an addressing period and an emission period. A multi-addressing controller for overlapping sections of L subframes less than or equal to K, and a data line control generating K data enable signals for controlling addressing in the overlapped subframe section and applying them to the data driver. It includes a signal generator.

A display device according to another embodiment of the present invention includes a timing controller that performs multi-addressing, and the timing controller converts one frame period into K subframes each including an addressing period and an emission period. and a gate line control signal generator for controlling addressing in the overlapping subframe intervals, generating K vertical synchronization signals, and applying them to the gate driver.

The timing controller according to an embodiment of the present invention converts a frame period into K subframes and overlaps them to perform multi-addressing.

A timing controller according to another embodiment of the present invention includes a subframe conversion unit that converts one frame period into K subframes each including an addressing period and an emission period, and a period of L subframes less than or equal to K. and a multi-addressing control unit for overlapping subframes and a data line control signal generation unit for generating K data enable signals for controlling addressing in the overlapping subframe period and applying them to the data driver.

A timing controller according to another embodiment of the present invention controls a subframe converting unit that converts one frame period into K subframes each including an addressing period and an emission period, and controls addressing in overlapping subframe periods, and a gate line control signal generator for generating K vertical synchronization signals and applying them to the gate driver.

In implementing multi-addressing when the present invention is applied, a timing controller, which is a device for controlling driving in subframe units instead of frame units, and a display device including the timing controller are provided.

In implementing multi-addressing when the present invention is applied, even if gate lines are addressed beyond the subframe unit or the data enable time for each subframe is different, independent driving is possible in units of subframes, which can increase efficiency A timing controller and a display device including the timing controller are provided.

When the present invention is applied, when multi-addressing is applied in a large-area, high-resolution display panel and a display device to which such a display panel is applied, data is easily controlled for each subframe, while adjusting the order of applying scan signals to gate lines between subframes A timing controller and a display device including the timing controller are provided.

The effects of the present invention are not limited to the above-mentioned effects, and those skilled in the art can easily derive various effects of the present invention from the configuration of the present invention.

1 is a diagram showing a display device to which an exemplary embodiment of the present invention is applied.
2 is a diagram showing a subframe driving method.
3 is a diagram showing a multi-addressing driving method according to an embodiment of the present invention.
4 is a diagram showing an addressing time point of a multi-addressing driving method according to an embodiment of the present invention.
5 is a diagram showing the configuration of a timing controller according to an embodiment of the present invention.
6 is a diagram showing a configuration of a signal when subframes are mixed in multi-addressing driving.
7 is a diagram showing waveforms to which Vsync and DE are applied to each of a plurality of subframes by a timing controller according to an embodiment of the present invention.
8 is a diagram showing the configuration of a data line control signal generator according to an embodiment of the present invention.
9 is a diagram showing waveforms when a representative signal conversion unit is an OR gate according to an embodiment of the present invention.
10 is a diagram showing the configuration of a gate line control signal generator according to an embodiment of the present invention.
11 is a diagram showing an operation of a gate line control signal generator according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings so that those skilled in the art can easily carry out the present invention. This invention may be embodied in many different forms and is not limited to the embodiments set forth herein.

In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification. Further, some embodiments of the present invention are described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Hereinafter, the display device will be described focusing on the organic light emitting display device, but the present invention is not limited thereto, and can be applied to various display devices to which a subframe and digital drive are applied, such as a liquid crystal display device, in addition to the organic light emitting display device.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

In addition, in implementing the present invention, components may be subdivided for convenience of explanation, but these components may be implemented in one device or module, or one component may be implemented in a plurality of devices or modules. It may be divided into and implemented.

1 is a diagram showing a display device to which an exemplary embodiment of the present invention is applied. A display device 100 to which the embodiments are applied includes a display panel 110 in which gate lines GL1 to GLn and data lines DL1 to DLm are crossed, and a display panel 110 disposed in the display panel 110. The gate driver 120 for driving the gate lines, the data driver 130 for driving the data lines disposed on the display panel 110, and the driving timing of the gate driver 120 and the data driver 130 are controlled. It includes a timing controller (Timing Controller, 140) and the like.

Each sub-pixel P is defined in the display panel 110 by crossing the gate lines GL1 to GLn and the data lines DL1 to DLm. The sub-pixel is for displaying one color and can display any one color among red (R), green (G), blue (B), and selectively white (W). The aforementioned colors may be replaced according to embodiments.

The data driver 130 may be implemented with a plurality of source drive integrated circuits (ICs). The data driver 130 receives digital video data RGB from the timing controller 140 and applies a second signal to the display panel 110 . Looking more closely, the data driver 130 converts the digital video data RGB into a gamma compensation voltage to generate a data voltage in response to a source timing control signal from the timing controller 140, and converts the data voltage to a gate signal. is supplied to the data lines DL of the display panel 110 to be synchronized. The data driver 130 may be connected to the data lines DL of the display panel 110 through a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driver 120 drives the gate lines GL1 to GLn by sequentially supplying a first signal, for example, a scan signal, to the gate lines GL1 to GLn. To this end, it receives a clock signal and receives a clock signal. Based on this, scan signals are sequentially supplied to the gate lines GL1 to GLn.

The timing controller 140 may be configured on a source printed circuit board (PCB), and a gate drive integrated circuit (hereinafter referred to as 'gate drive IC') is connected to a display panel using a Tape Automated Bonding (TAB) method. It may be configured on a display panel in a COG (Chip On Glass) method or electrically connected to the display panel in a COF (Chip On Film) method.

The timing controller 140 receives digital video data (RGB) from an external host system through an interface such as a low voltage differential signaling (LVDS) interface, a transition minimized differential signaling (TMDS) interface, or a mobile industrial processor interface (MIPI). . The timing controller 140 transmits digital video data RGB input from the host system to the data driver 130 .

The timing controller 140 receives timing signals such as video data (RGB), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a main clock signal (MCLK), and a data enable signal (DE) from the outside, Based on this timing signal, the gate control signal (GCS) is applied to the gate driver 120, and the data control signal (DCS) and the above-described image data (RGB) are applied to the data driver 130 as an image for sub-pixels to display. Data (R'G'B') is applied. A plurality of integrated circuits (source drive ICs) constituting the data driver 130 are controlled to apply signals to data lines within a predetermined area.

Although not shown in FIG. 1 , the display device 100 further includes a power supply unit, which supplies voltage or current by applying power to the data driver 130 , the gate driver 120 , and the display panel 110 .

A digital driving method using a subframe may be divided into an address display separation (ADS) method and an address while display (AWS) method.

One frame may be divided into multiple subframes. Each subframe represents one bit of applied data. One subframe is further divided into an addressing period for applying an input value to a channel and an emission period for light emission. As an embodiment, in representing R, G, B, and optionally W (white), the data signal may be configured such that n bits represent gray levels. In this case, n subs corresponding to n bits. Frames may exist.

When n subframes are arranged corresponding to n bits, each subframe may correspond to a bit at a specific position.

2 is a diagram showing a subframe driving method.

210 of FIG. 2 shows a case where a 6-bit data signal is configured and 6 subframes are applied, MSB to LSB of the data signal are allocated to the first subframe to the sixth subframe.

The display device 100 may set an emission time in each subframe, which may apply a weight for each subframe. For example, in a 6-bit data signal, the subframe corresponding to the most significant bit (MSB) is the first subframe (SF1), the next bit is the second subframe (SF2), and so on. The bit (Least Significant Bit, LSB) can be configured to be the 6th subframe (SF6). A light emitting period of each subframe may have a different weight depending on the location of a corresponding bit. For example, if the gradation value is 20 in decimal, if it is converted into a 6-bit binary number, it becomes “010100” and controls to emit light at the second subframe SF2 and the fourth subframe SF4.

220 of FIG. 2 shows a case in which a 6-bit data signal is configured and 6 subframes are applied, and LSB to MSB of the data signal are allocated to the first subframe to the sixth subframe.

The display device 100 may set an emission time in each subframe, which may apply a weight for each subframe. For example, in a 6-bit data signal, the subframe corresponding to the least significant bit (LSB) is the first subframe (SF1), the next bit is the second subframe (SF2), and so on. The bit (Most Significant Bit, MSB) can be configured to be the 6th subframe (SF6). A light emitting period of each subframe may have a different weight depending on the location of a corresponding bit. For example, if the gradation value is 20 in decimal, if it is a 6-bit binary number, it becomes “010100” and controls to emit light at the third subframe SF3 and the fifth subframe SF5.

A driving method using such a subframe is referred to as a digital driving method. In this case, the luminance of the organic light emitting diode in each subframe is the same, but the gray level can be adjusted due to the difference in the length of the light emitting section.

3 is a diagram showing a multi-addressing driving method according to an embodiment of the present invention. In the multi-addressing driving method, the emission period of the first subframe and the addressing period of the second subframe are overlapped, and as a result, the addressing period is formed densely, thereby reducing the total scan time. In FIG. 3 , each sub-pixel of the display device is turned on or off by dividing a grayscale expressed by 5 bits into 5 subframes. FIG. 3 is a scheme for allocating a Least Significant Bit (LSB) to the first subframe like 220 in the embodiment of FIG. 2 . Here, while the first bit scan (Nth frame 1 ^st bit scan, SF1) of the Nth frame continues from the first gate line (GL1) to the last gate line (GLn), the second bit scan (Nth frame 2 ^nd bit scan) , SF2) follows. This is because the addressing section and the emission section are different in each scan process, and the data signal can be applied to each sub-pixel even if the addressing section is different and the emission sections overlap. The multi-addressing drive as shown in FIG. 3 can perform multiple scans during the same time, so time can be used efficiently. However, driving is complicated in that a plurality of subframes are overlapped, and signals suitable for these subframes must be applied. In particular, the number of gate lines increases as the area increases, and the number of subframes increases as the gradation increases, resulting in increased driving complexity.

4 is a diagram showing an addressing time point of a multi-addressing driving method according to an embodiment of the present invention. For convenience of description, a case in which the number of gate lines is 10 will be described. It was previously described in FIG. 3 that five subframes are sequentially scanned. In FIG. 4, 10 gate lines are overlapped for each subframe to show a point in time at which a scan signal is applied. A unit in which scan signals are sequentially applied for a total of five subframes is called a unit period. Looking at the order in which the scan signal is applied in the first unit period 410, after the scan signal corresponding to the first subframe SF1 is applied in GL1, the scan signal corresponding to the fourth subframe SF4 is applied in GL7. do. Next, a scan signal corresponding to the 5th subframe SF5 in GL3 is applied, then a scan signal corresponding to the 2nd subframe SF2 in GL1, and finally a 3rd subframe SF3 in GL10. A scan signal for is applied.

Referring to the configuration of FIG. 4 , overlapping of subframes is an embodiment in which addressing intervals of a plurality of subframes exist within a unit interval, but do not overlap between these addressing intervals. Here, the order in which scan signals are applied is not the order of gate lines. Therefore, a sequence controller for controlling the sequence of these gate lines is required. In addition, in order to apply the data signal to the subpixels of the gate line, it is necessary to control the data signal for each subframe. Accordingly, the timing controller must be able to apply data enable (DE) and a vertical synchronization signal (Vsync), which are control signals for applying data, for each subframe. In the present specification, overlapping of subframes refers to all embodiments in which a process of applying a scan signal to a gate line of a display panel in one subframe and a process of applying a scan signal to a gate line of a display panel in another subframe are also included. include In this embodiment, a data enable signal and a vertical synchronization signal are required for each subframe, and it is necessary to implement a display device that manages information on gate lines to which each scan signal is applied and a timing controller implementing the same. , take a look at this.

5 is a diagram showing the configuration of a timing controller according to an embodiment of the present invention. That is, as an embodiment of a digital driving device based on a subframe, the timing controller will be mainly described. However, the digital driving device based on the subframe of the present invention is not limited to the timing controller and may be a subcomponent constituting the timing controller.

The configuration of the timing controller 140 includes a subframe converter 510, a multi-addressing controller 520, a data line control signal generator 530, and a gate line control signal generator 540. The data line control signal generation unit 530 generates a data line for each subframe and provides a function of converting the data line into a representative data enable signal. In addition, the gate line control signal generation unit 540 controls the order of gate lines to which scan signals are applied between subframes operated by multi-addressing to be selected for each subframe.

Looking at each in more detail, the subframe converter 510 converts one frame period into K subframes each including an addressing period and an emission period. For example, when data representing gray levels of subpixels is 10 bits, one frame period can be converted into 10 subframes.

The multi-addressing control unit 520 controls to overlap sections of L subframes less than or equal to K. As in the multi-addressing illustrated in FIGS. 3 and 4 , when focusing on a specific subframe, gate lines may be sequentially selected. However, when examining all subframes, the addressing sections of each subframe are not sequential, and can move between several gate lines as shown in FIGS. 3 and 4 . The multi-addressing control unit 520 may overlap sections of subframes in consideration of K, which is the number of subframes in a frame section, lengths of subframe sections, and lengths of addressing sections.

The data line control signal generation unit 530 generates K data enable signals for controlling addressing in overlapping subframe periods and applies them to the data driver 130 . The gate line control signal generation unit 540 controls addressing in overlapping subframe sections, generates K vertical synchronization signals, and applies them to the gate driver 120 .

In the configuration of FIG. 5 , since the data line control signal generator 530 and the gate line control signal generator 540 generate signals for each subframe, driving can be controlled in units of subframes instead of units of frames. In particular, since subframes are mixed due to multi-addressing, gate lines are addressed beyond the subframe unit, and the data enable time may be different for each subframe, the application of the configuration of FIG. 5 increases driving efficiency. can In addition, since driving information unique to each subframe is provided, data can be easily controlled for each subframe.

6 is a diagram showing a configuration of a signal when subframes are mixed in multi-addressing driving. When one vertical synchronization signal, Vsync, and one data enable signal, DE, are applied to each subframe, it is difficult to set the reference signal because the high/low of Vsync and DE are mixed. It is difficult. Vsync constitutes a frame unit, and when a plurality of subframes overlap in one frame, it becomes difficult to configure Vsync for the start and end of one subframe. That is, since another subframe starts between the start and end of a subframe, the configuration of Vsync becomes complicated. Accordingly, Vsync and DE may be applied for each subframe by applying the configuration shown in FIG. 5 . This will be reviewed in FIG. 7 .

7 is a diagram showing waveforms to which Vsync and DE are applied to each of a plurality of subframes by a timing controller according to an embodiment of the present invention. Vertical synchronization signals for each subframe are composed of Vsync_SF1, Vsync_SF2, ..., respectively. Similarly, the data enable signal for each subframe is also composed of DE_SF1, DE_SF2, ..., and the like. 5, the data line control signal generation unit 530 generates K data enable signals (the number of subframes) for controlling addressing in overlapping subframe intervals, thereby generating a data driver (FIG. 1). of 130). In addition, the gate line control signal generation unit 540 of FIG. 5 generates K vertical synchronization signals for addressing control in overlapping subframe sections and applies them to the gate driver (120 of FIG. 1).

Since vertical synchronization signals and data enable signals are set for each subframe as shown in FIG. 7 , it is easy to control driving for each subframe, and driving efficiency can be increased. That is, data and signals necessary for driving are independently set for each subframe to ensure efficiency and ease of driving.

8 is a diagram showing the configuration of a data line control signal generator according to an embodiment of the present invention.

The data line control signal generator 530 includes a DE signal generator 531 that generates K data enable signals for each of the K subframes and a representative signal conversion that generates a representative data enable signal from the generated signals. section 532. The DE signal generator 531 generates DE signals DE_SF1, DE_SF2, ..., DE_SFK for each subframe. And this signal is applied to the representative signal converter 532 to generate one representative DE signal. The representative DE signal DE converted by the representative signal converter 532 is applied to the data driver.

In the configuration shown in FIG. 8 , since the DE signal generating unit 531 generates a data enable signal for each subframe, the data enable signal between each subframe can be independently controlled. That is, in generating the data enable signal in the timing controller, instead of complexly calculating the data enable signal to be applied to the currently scanned gate line, the data enable signal is generated for each subframe, and the current scan is made of these signals. A data enable signal of a subframe corresponding to a gate line may be applied. Therefore, since the data enable signal can be independently driven between subframes, control is easy and driving efficiency can be increased.

The representative signal converter 532 may be variously selected according to the DE signal for each subframe. For example, when the DE signal is a high signal, the representative DE signal DE representing these signals can be output through an OR gate. In this case, the representative signal conversion unit 532 performs the OR An (OR) gate is an example. On the other hand, when the DE signal is a low signal, the representative DE signal DE representing these signals can be output through an AND gate. In this case, the representative signal conversion unit 532 (AND) gate as an example.

9 is a diagram showing waveforms when a representative signal conversion unit is an OR gate according to an embodiment of the present invention. An embodiment in which K is 8 will be mainly described. 910 shows a logical sum (OR) gate 915 that is an embodiment of the representative signal conversion unit 532 .

Data enable signals for each of the eight subframes are generated by the data line control signal generation unit 530 from DE_SF1 to DE_SF8. This signal is input to the input terminal of the logical sum (OR) gate 915, which is the representative signal conversion unit 532. Also, a representative DE signal DE is output from an output terminal of the OR gate 915 .

920 is a diagram showing a relationship between a representative DE signal DE and data enable signals for each of 8 subframes in the configuration of 910 .

Each of the data enable signals 925 is composed of high signals that do not overlap with each other. These signals are connected to the input terminal of the OR gate 915, and the OR gate 915 outputs the DE signal as shown in 926. This signal is applied to the data driver 130.

When the high signal of the data enable signals 925 of the independently operating subframes is applied to the data driver 130, it is applied as a representative data enable signal 926, which is called a logical sum (OR) gate 915. When applied as a configuration, the OR gate 915 can quickly generate a representative data enable signal without increasing the complexity of the entire circuit.

10 is a diagram showing the configuration of a gate line control signal generator according to an embodiment of the present invention.

When multi-addressing is not applied, one Vsync corresponds to one frame, and gate lines are sequentially selected for subframes constituting one frame so that scan signals can be sequentially applied. However, when multi-addressing is applied, it has been seen in FIGS. 3 and 4 that frame sections overlap each other and subframes constituting a frame section also overlap. Accordingly, each Vsync signal is configured, and gate lines to which scan signals are applied for each subframe may also be configured differently. Accordingly, the gate line control signal generator 540 includes a Vsync signal generator 541 for generating vertical synchronization signals for each K subframe and a gate line to which a scan signal is applied for each K subframe, as shown in FIG. 10 . An address control unit 542 for storing identification information is further included.

The Vsync signal generator 541 generates Vsync signals (Vsync_SF1, Vsync_SF2, ...) for each subframe under the control of the multi-addressing generator 520 of FIG. 5 . This becomes a criterion for each subframe in setting the vertical synchronization signal, addressing period, and emission period for each subframe.

The address controller 542 includes K counters 1010a, 1010b, ..., 1010k for storing identification information on gate lines to which scan signals are applied for each K subframe. And, it includes a multiplexer (MUX) 1020 to which identification information for gate lines generated by these counters is input and instruction information (SEL) for selecting one of these identification information is input. The identification information output from the multiplexer 1020 becomes information identifying a gate line to which data is applied, that is, to be addressed.

Summarizing the configuration of FIG. 10 , the vertical synchronization signal Vsync is independently set so that a frame section can be differently determined for each subframe. Therefore, even if there are a plurality of vertical synchronization signals within the same section, it can be set to define a frame section for each subframe, thereby increasing driving efficiency.

In addition, in the prior art, scan signals are applied in order of gate lines and only one address needs to be stored. However, as shown in FIG. 4, in the multi-addressing method, the order of gate lines to which scan signals are applied is sequential only for each subframe. , It is not sequential based on the entire display panel. Since the addressing intervals for each subframe overlap within one unit interval 410, it has been a complicated problem to store and restore the order of gate lines. However, when the configuration shown in FIG. 10 is applied, since there is an address controller 542 that stores identification information on gate lines to which scan signals are applied for each subframe and outputs them in order for each subframe, The order of applying scan signals to the lines may be maintained. Therefore, it is possible to provide efficiency in controlling driving of the gate line.

In particular, counters 1010a, 1010b, ..., 1010k may be provided for each subframe. The counter for each subframe combines the information on the subframe selected at the time when the current scan signal is applied among the identification information on a plurality of gate lines provided by each counter, so that the address control unit 542 obtains the identification information on the gate line. output, so that a scan signal can be applied to the corresponding gate line. The configuration of FIG. 10 also enables independent operation of subframes, so that scan signals can be applied without errors for each subframe even if the addressing intervals of a plurality of subframes are complexly configured.

11 is a diagram showing an operation of a gate line control signal generator according to an embodiment of the present invention.

1110 shows the inputs and outputs of multiplexer 1020. To the multiplexer 1020, identification information generated by 10 counters for each subframe (CNT_SF1, CNT_SF2, ..., CNT_SF10) is provided to an input terminal. In addition, indication information (SEL) for selecting a subframe to be currently applied among these pieces of identification information is applied. The indication information may be applied as 4 bits (S3, S2, S1, S0). As a result, the output identification information is information identifying the gate line to be addressed, and one of the identification information generated from CNT_SF1, CNT_SF2, ..., CNT_SF10 is selected, and this selection is the indication information S3, S2, S1 , is done through S0. The number of bits of these indication information may increase or decrease according to the number of subframes. Accordingly, the indication information may increase or decrease according to the number of bits of data representing the gray level.

Reference numeral 1120 shows an example of information input to the multiplexer 1020 and output information. CNT_SF1, CNT_SF2, ..., CNT_SF10 are counters that count gate lines for each subframe. The numbers output from CNT_SF1, CNT_SF2, ..., CNT_SF10 become gate line identification information. For example, CNT_SF1 is a gate line to which a scan signal is applied in the first subframe, and numbers 6 and 7 are indicated.

In this way, identification information on the gate line is provided for each subframe by a plurality of counters, and the multiplexer 1020 determines which subframe is the gate line to which the current scan signal is applied among the input identification information, that is, the corresponding subframe. According to the indication information (S3, S2, S1, S0) for selecting, identification information about the gate line is output. That is, as for the identification information (GL_number) selected by the multiplexer 1020, even if 6, 86, 84, 80, etc., which are identification information of gate lines, are output and a scan signal is applied to the corresponding gate line, subframes overlap. The order within each subframe may be maintained.

As reviewed in FIG. 11, a counter may be provided for each subframe, and a scan signal may be applied to a gate line by providing the counter to an input terminal of a multiplexer.

The present invention is summarized as follows. In multi-address driving, a control signal is generated for each subframe so that the subframes can be controlled independently of each other. An example of the control signal may be Vsync, which is a vertical synchronization signal, and DE signal, which is a data enable signal. can be applied to all

When the present invention is applied, when multi-addressing is applied to a large-area, high-resolution display panel and a display device to which such a display panel is applied, the addressing section must be complexly controlled for each subframe. While easily controlling data for each subframe, it is possible to adjust the order of applying scan signals to gate lines between subframes. To this end, a memory for storing identification information such as gate line addresses and a counter and a multiplexer are combined to control the order of gate lines so that scan signals can be accurately applied to specific gate lines of specific subframes, thereby enabling efficient scanning. sequence can be derived.

In addition, when the present invention is applied, efficient driving of multi-addressing is possible. This enables efficient use of time as it can be scanned multiple times at the same time in preparation for conventional digital driving. Since another subframe starts before the addressing period of one subframe ends, the scan order of subframes can be mixed. In the present invention, since the DE and Vsync signals are assigned to each subframe, this scan order is assigned to each subframe. And, in particular, since it can be adjusted according to the characteristics of a subframe, it is possible to implement multi-addressing.

Although the above has been described based on the embodiments of the present invention, various changes or modifications may be made at the level of those skilled in the art. Accordingly, it will be understood that such changes and modifications are included within the scope of the present invention as long as they do not depart from the scope of the present invention.

100: display device
110: display panel
120: gate driver
130: data driver
510: subframe converting unit
520: multi-addressing control unit
530: data line control signal generator
531: DE signal generator
532: representative signal conversion unit
540: gate line control signal generator
541: Vsync signal generator
542: address control unit
1010a, 1010b, ..., 1010k: counter

Claims (12)

a display panel on which a plurality of sub-pixels defined by intersections of gate lines and data lines are arranged;
a gate driver applying a first signal to the gate line;
a data driver applying a second signal to the data line; and
A subframe converting unit that converts one frame period into K subframes each including an addressing period and an emission period; a multi-addressing control unit that overlaps L subframe periods less than or equal to K; A data line control signal generating unit generating K data enable signals for controlling addressing in a subframe period and applying the generated data enable signals to the data driver, controlling addressing in the overlapping subframe period, and generating K vertical synchronization signals A display device including a timing controller including a gate line control signal generator for generating and applying the gate line control signal to the gate driver.
According to claim 1,
The data line control signal generator may include a DE signal generator configured to generate K data enable signals for each of the K subframes; and
The display device further comprises a representative signal converter for generating a representative data enable signal from the generated signals.
According to claim 2,
The K data enable signals are high signals that do not overlap with each other,
The representative signal conversion unit is a logical sum (OR) gate having the K data enable signals as input terminals.
According to claim 1,
The gate line control signal generator
a Vsync signal generating unit generating data K vertical synchronization signals for each of the K subframes; and
and an address controller configured to store identification information on a gate line to which a scan signal is applied for each of the K subframes.
According to claim 4,
The address control unit includes K counters.
According to claim 5,
The address control unit
A first input terminal receiving identification information for K gate lines to which scan signals are applied for each subframe in the K counters, and a second input terminal receiving instruction information for selecting one of the K subframes; A display device comprising a multiplexer including an output terminal outputting any one of the K pieces of identification information received from the first input terminal according to the instruction information input from the second input terminal.
A timing controller controlling operations of sub-pixels of a display panel in which a plurality of sub-pixels defined by intersections of gate lines and data lines are arranged, comprising:
a subframe converting unit for converting one frame period into K subframes each including an addressing period and an emission period;
a multi-addressing controller for overlapping sections of L subframes less than or equal to K;
a data line control signal generation unit generating K data enable signals for controlling addressing in the overlapping subframe intervals and applying them to a data driver; and
and a gate line control signal generation unit configured to control addressing in the overlapping subframe intervals, generate K vertical synchronization signals, and apply the generated K vertical synchronization signals to a gate driver.
According to claim 7,
The data line control signal generator may include a DE signal generator configured to generate K data enable signals for each of the K subframes; and
The timing controller further comprises a representative signal converter for generating a representative data enable signal from the generated signals.
According to claim 8,
The K data enable signals are high signals that do not overlap with each other,
The representative signal conversion unit is a logical sum (OR) gate having the K data enable signals as input terminals, the timing controller.
According to claim 7,
The gate line control signal generator
a Vsync signal generating unit generating data K vertical synchronization signals for each of the K subframes; and
The timing controller further comprises an address controller storing identification information on a gate line to which a scan signal is applied for each of the K subframes.
According to claim 10,
Wherein the address control unit includes K counters, the timing controller.
According to claim 11,
The address control unit
A first input terminal receiving identification information for K gate lines to which scan signals are applied for each subframe in the K counters, and a second input terminal receiving instruction information for selecting one of the K subframes; and a multiplexer including an output terminal outputting one of the K pieces of identification information received from the first input terminal according to the instruction information input from the second input terminal.

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