KR102270604B1 - Image display system - Google Patents

Abstract

The present invention relates to an image display system capable of preventing FRC noise by matching the application order of FRC patterns between a host system and a display device regardless of driving conditions.
The video system of the present invention includes a host system and a display device. The host system includes a first FRC dithering unit for correcting and outputting first image data to second image data smaller than the number of bits of the first image data using a plurality of first FRC patterns that are different for each frame. The display device includes a second FRC dithering unit for correcting the second image data supplied from the host system to third image data smaller than the number of bits of the second image data using a plurality of second FRC patterns different for each frame and outputting the corrected second image data. do. The operation time of the second FRC dithering unit is controlled according to the enable signal supplied from the host system.

Description

Image display system {IMAGE DISPLAY SYSTEM}

The present invention relates to an image display system, and to an image display system capable of minimizing generation of dithering noise due to abnormal driving.

As a flat panel display device that has recently been spotlighted as a display device, a liquid crystal display (LCD) using liquid crystal, an OLED display using an organic light emitting diode (OLED), and electrophoresis using electrophoretic particles A display device (ElectroPhoretic Display; EPD) and the like are representative.

A display device includes a display panel displaying an image through a pixel array in which each pixel (sub-pixel) is independently driven by a thin film transistor (TFT), a panel driver driving the display panel, and controlling the panel driver and a timing controller, a power supply, and the like. The panel driver includes a gate driver driving gate lines of the display panel and a data driver driving data lines of the display panel.

The display device includes a frame rate control dithering (FRC dithering) circuit in order to increase grayscale expression power higher than the number of grayscales determined by the number of bits of image data. The FRC dithering circuit performs a dithering process for spatially and temporally dispersing lower bits of image data using different FRC patterns according to grayscale values and frames to fine-tune grayscale values to increase grayscale expression power, that is, color depth. increase

A host system that supplies image data to the display device further includes an FRC dithering circuit for color correction and the like.

Although the FRC pattern used in the host system and the FRC pattern used in the display device are different from each other, the order of application of the FRC pattern applied to the host system on a frame-by-frame basis so as to minimize FRC noise (dithering noise) with an appropriate combination; The order of application of the FRC pattern applied to the device is designed to match.

However, when power is turned on or when power is supplied to the display device at different times, such as when the power is turned on or when a mode for changing a frequency is different, the FRC pattern application sequence of the FRC dithering circuit of the host system and the FRC dithering circuit of the display device may be mismatched. For this reason, there is a problem in that FRC noise such as stripes is generated when the FRC pattern of the host system and the FRC pattern of the display device are incorrectly combined.

The FRC noise is mainly generated in the liquid crystal display device in which the polarity of the data voltage is periodically inverted, but may also occur in the OLED display device, so the present invention is not limited to the liquid crystal display device.

The present invention has been devised to solve the above problems, and the problem to be solved by the present invention is to display an image capable of preventing FRC noise by matching the application order of the FRC patterns between the host system and the display device regardless of driving conditions. to provide a system.

In order to solve the above problems, an image display system according to an embodiment of the present invention includes a host system and a display device. The host system includes a first FRC dithering unit for correcting and outputting first image data to second image data smaller than the number of bits of the first image data using a plurality of first FRC patterns that are different for each frame. The display device includes a second FRC dithering unit for correcting the second image data supplied from the host system using a plurality of second FRC patterns different for each frame into third image data smaller than the number of bits of the second image data and outputting the corrected second image data. do. The operation time of the second FRC dithering unit is controlled according to an enable signal supplied from the host system.

The order in which the plurality of first FRC patterns are applied by the first FRC dithering unit and the order in which the plurality of second FRC patterns are applied by the second FRC dithering unit are matched by the enable signal.

The first FRC dithering unit counts the input vertical synchronization signal and outputs first frame information for selecting one of a plurality of first FRC patterns, and controls an operation time of the second FRC dithering unit from the host system and an enable generator for generating an enable signal and outputting the enable signal to the display device when a control signal is input. The second FRC dithering unit is enabled when the enable signal is supplied from the enable generator of the host system, and counts the vertical synchronization signal supplied from the host system to select any one of the plurality of second FRC patterns. and a second frame counter for outputting information.

According to the enable signal, the first frame information of the first frame counter and the second frame information of the second frame counter are matched in a predetermined order.

The enable signal generator generates an enable signal when a control signal is input and a reset signal is input from the first frame counter.

The enable signal is supplied from the host system as an option signal to the display device, is mapped to at least one bit of the LVDS format through an LVDS (Low Voltage Differential Signal) interface, and is supplied, or DPCP through an eDP (embedded Display Port) interface (Display Port Configuration Data) included and supplied.

The video display system according to the present invention controls the operation timing of the FRC dithering unit of the display device by supplying an enable signal from the FRC dithering unit of the host system whenever necessary, so that the application order of the FRC patterns of the host system and the display device can always be matched. have.

Accordingly, the image display system according to the present invention can prevent FRC noise due to mismatch between the FRC pattern of the host system and the FRC pattern of the display device.

1 is a block diagram schematically showing an image display system according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram illustrating, for example, the configuration of one sub-pixel of an OLED panel applied as the display panel shown in FIG. 1 .
FIG. 3 is an equivalent circuit diagram illustrating, for example, the configuration of one sub-pixel of a liquid crystal panel applied as the display panel shown in FIG. 1 .
FIG. 4 is a block diagram schematically illustrating first and second FRC dithering units respectively embedded in the host system and the timing controller shown in FIG. 1 .
5 is an exemplary view comparing the present invention in which the application order of the first and second FRC patterns in the first and second FRC dithering units is not matched with the prior art.
6 is a block diagram illustrating an internal configuration of the first and second FRC dithering units shown in FIG. 4 .
7 is an exemplary diagram illustrating first FRC patterns stored in the first LUT shown in FIG. 6 .
8 is a block diagram schematically illustrating a host system and a display device using an LVDS interface according to another embodiment of the present invention.
9 is an exemplary diagram illustrating a data transmission format of the LVDS interface shown in FIG. 8 .

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram schematically showing an image display system according to an embodiment of the present invention.

The image display system illustrated in FIG. 1 includes a display device 100 and a host system 200 . The display device 100 includes a timing controller 300 , a data driver 20 and a gate driver 30 that are panel drivers, a display panel 40 , and a power supply not shown.

The display panel 40 displays an image through a pixel array in which pixels are arranged in a matrix form. Each pixel of the pixel array is composed of red (R; hereinafter R), green (Green; hereinafter G), and blue (Blue; hereinafter B) sub-pixels. Alternatively, the R/W/B/G sub-pixels to which a white (W) sub-pixel having higher luminous efficiency than the RGB sub-pixel is added may be configured. Alternatively, each pixel can be As the display panel 50 , an LCD panel or an OLED panel may be applied.

For example, when the display panel 40 is an OLED panel, each of the R/G/B or R/W/B/G sub-pixels is a high-potential power supply (EVDD) line and a low-potential power supply (EVDD) line as shown in FIG. 2 , respectively. An OLED element connected between the potential power supply (EVSS) lines, and a pixel circuit connected to the data line DL and the gate line GL and driving the OLED element are provided. The pixel circuit includes at least a switching transistor ST, a driving transistor DT, and a storage capacitor Cst. The switching transistor ST charges the storage capacitor Cst with a voltage corresponding to the data signal from the data line DL in response to the scan pulse from the gate line GL, and the driving transistor DT is connected to the storage capacitor Cst. Cst) controls the current supplied to the OLED device according to the charged voltage to control the amount of light emitted from the OLED device.

In contrast, when the display panel 40 is a liquid crystal panel, each of the R/G/B or R/W/B/G sub-pixels is a gate line GL and a data line DL as shown in FIG. 3 . and a thin film transistor (TFT) connected to and a liquid crystal capacitor (Clc) and a storage capacitor (Cst) connected in parallel to the thin film transistor (TFT). The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode through the thin film transistor TFT and the common voltage Vcom supplied to the common electrode, and drives the liquid crystal according to the charged voltage to achieve light transmittance. adjust the The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

The data driver 20 receives a data control signal and image data from the timing controller 300 . The data driver 20 is driven according to the data control signal, and uses a reference gamma voltage set supplied from a gamma voltage generator (not shown) that is built in or provided separately outside the data driver 20 to the grayscale voltages respectively corresponding to the grayscale values of the data. Then, digital image data is converted into an analog image data signal using the subdivided grayscale voltages. The data driver 20 converts each of the R/G/B data into an analog R/G/B signal and supplies it to the data lines respectively connected to the R/G/B sub-pixels of the display panel 40 , Each of the R/W/G/B data is converted into an analog R/W/G/B signal and supplied to the data lines respectively connected to the R/W/G/B sub-pixels of the display panel 40 .

The data driver 20 includes a plurality of data driving ICs (Integrated Circuits) that divide and drive the data lines DL of the display panel 40 , and each data driving IC includes a tape carrier package (TCP) and a chip (COF). On Film), flexible print circuit (FPC), etc. is mounted on a circuit film and attached to the display panel 10 by a TAB (Tape Automatic Bonding) method, or mounted on the display panel 40 by a COG (Chip On Glass) method. can be

The gate driver 30 drives each of the plurality of gate lines of the display panel 40 using a gate control signal supplied from the timing controller 300 . The gate driver 30 supplies a scan pulse of a gate-on voltage to each gate line in a corresponding scan period in response to a gate control signal, and supplies a gate-off voltage in the remaining period. The gate driver 30 may receive a gate control signal from the timing controller 300 or may receive a gate control signal from the timing controller 300 via the data driver 20 . The gate driver 30 is composed of at least one gate IC and is mounted on a circuit film such as TCP, COF, FPC, etc. to be attached to the display panel 40 in a TAB method or mounted on the display panel 40 in a COG method. can In contrast, the gate driver 30 is formed on the thin film transistor substrate together with the thin film transistor array constituting the pixel array of the display panel 40 , so that the gate driver 30 is a gate in panel (GIP) type embedded in the non-display area of the display panel 40 . can be provided as

The host system 200 supplies image data and a timing synchronization signal to the display device 100 . The host system 200 converts image data including a system on chip having a built-in scaler into a resolution data format suitable for display on the display panel 40 of the display device 100 and outputs it do. For example, the host system 200 may be any one of a system of a portable terminal such as a computer, a TV system, a set-top box, a tablet, or a mobile phone.

The timing controller 300 receives image data and timing signals from the host system 200 . The timing controller 300 outputs image data from the host system 200 to the data driver 20 by performing image processing such as necessary image quality compensation. The timing controller 300 generates a data control signal and a gate control signal for controlling driving timings of the data driver 20 and the gate driver 30, respectively, using the timing signals supplied from the host system 200 to generate the data driver ( 20) and the gate driver 30, respectively. The timing signal supplied from the host system 200 to the timing controller 300 includes a dot clock, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal, but the vertical synchronization signal and the horizontal synchronization signal may be omitted here. When the vertical synchronization signal and the horizontal synchronization signal are omitted, the timing controller 300 may generate and use the vertical synchronization signal and the horizontal synchronization signal by counting the data enable signal according to the dot clock. The data control signals supplied from the timing controller 300 to the data driver 20 include a source start pulse, a source sampling clock, a polarity control signal, and a source output enable signal. The gate control signals supplied from the timing controller 300 to the gate driver 30 include a gate start pulse, a gate shift clock, and a gate output enable signal.

The host system 200 includes a first FRC dithering unit 210 , and the timing controller 300 of the display device 100 includes a second FRC dithering unit 310 .

When the operating time of the first FRC dithering unit 210 of the host system 200 and the operating time of the second FRC dithering unit 310 of the display device 100 are different from each other, the first FRC dithering unit 210 The host system 200 supplies the enable signal to the display device 100 so that the application order of the first FRC pattern and the application order of the second FRC pattern in the second FRC dithering unit 310 match as designed. to control the timing of the operation of the second FRC dithering unit 310 of the timing controller 300 .

For example, when the power of the host system 200 is turned on, or when only the power of the display device 100 is turned off and on to change the mode according to the change of the input frequency in the host system 200 , the host system ( When the power-on timings of the 200 ) and the display device 100 are different from each other, the operating timings of the first and second FRC dithering units 210 and 310 may not match. In this case, the host system 200 supplies an enable signal to the display device 100 to control the operation timing of the second FRC dithering units 210 and 310 to enable the first and second FRC dithering units 210 and 310 to operate. The timing of the operation can be matched.

Accordingly, even when the power-on timings of the host system 200 and the display device 100 are different from each other, the application order of the first FRC pattern in the first FRC dithering unit 210 and the second FRC dithering unit 310 are Match the application order of the second FRC pattern. Accordingly, the image display system according to the present invention can prevent FRC noise caused by mismatching of the FRC pattern application order of the host system 200 and the display device 100 .

4 is a block diagram schematically showing first and second FRC dithering units respectively built in the host system and the timing controller shown in FIG. 1 , and FIG. 5 is a first and second FRC dithering unit in the first and second FRC dithering units. It is an exemplary diagram showing the comparison of the present invention in which the application sequence of the pattern is not matched with the prior art.

4 and 5 , the first FRC dithering unit 210 built into the host system 200 applies a plurality of first FRC patterns P11, P12, P13, and P14 that are different for each frame. By dithering the first image data VD1 , the second image data VD2 having a reduced number of bits compared to the first image data VD1 is output. When the power of the host system 200 is turned on and the input voltage Vin1 is supplied, the first FRC dithering unit 210 operates so that the internal first frame counter counts the vertical synchronization signal Vsync, and the counted frame A plurality of first FRC patterns P11 , P12 , P13 , and P14 are sequentially selected according to the information 1 , 2 , 3 , and 4 and applied to the first input data VD1 .

The second FRC dithering unit 310 built in the timing controller 300 of the display device 100 applies a plurality of second FRC patterns P21, P22, P23, and P24 different for each frame to the host system 200 . The third image data VD3 having a reduced number of bits compared to the second image data VD2 is output by dithering the second image data VD2 input from the . After the host system 200 is powered on, when the input voltage Vin2 is supplied to the display device 100 , the second FRC dithering unit 310 operates to generate a second frame counter internal to the vertical synchronization signal Vsync. A frame is counted by counting , and a plurality of second FRC patterns P21, P22, P23, and P24 are sequentially selected according to the frame count value (1, 2, 3, 4) to select the second input data (VD2) applies to

However, as shown in FIG. 5 , when the operation timings of the first and second FRC dithering units 210 and 310 are different, the frame count values of the first and second FRC dithering units 210 and 310 are different and thus the first FRC pattern. The application order of the fields P11 to P14 and the application order of the second FRC patterns P21 to P24 may not match.

To prevent this, in the host system 200 of the present invention, the power of the host system 200 is turned on or only the power of the display device 100 is turned off in order to change the mode according to the change of the input frequency in the host system 200 . A control signal for controlling an operation timing of the second FRC dithering unit 310 of the display device 100 when the power-on timings of the host system 200 and the display device 100 are different from each other, such as when the display device 100 is turned on. (CNT) occurs. When the control signal CNT is input, the first FRC dithering unit 210 of the host system 200 is enabled when the internal first frame counter counts up to the set value 4 and then resets as shown in FIG. 5 . A signal EN is generated and supplied to the display device 100 .

When the enable signal EN is input from the host system 200 , the second FRC dithering unit 210 of the display device 100 starts a counting operation by an internal second frame counter, thereby performing first and second FRC dithering. Frame count values of the units 210 and 310 may be matched. Accordingly, since the application order of the first FRC patterns P11 to P14 and the application order of the second FRC patterns P21 to P24 always match even in a specific driving state, FRC noise can be prevented.

6 is a block diagram illustrating an internal configuration of the first and second dithering units shown in FIG. 4 .

The first FRC dithering unit 210 of the host system 200 includes a frame counter 212 corresponding to a frame determining unit generating frame information of the currently input first image data VD1, and the first image data VD1. ) based on the line counter 214 and the pixel counter 216 corresponding to the pixel position determination unit generating the pixel position information of , frame information, the pixel position information, and the lower bits LB1s of the first image data VD1 a first look-up table (LUT) 218 for selecting and outputting a dither value D1 from a plurality of pre-stored first FRC patterns P11 to P14, and first image data ( an adder 220 that adds the dither value D1 from the first LUT 218 to the upper bit UB1s of VD1) and outputs the second image data VD2, an input control signal CNT, and a frame counter and an enable signal EN generator 230 for generating and outputting an enable signal EN in response to a reset signal from 212 . The first image data VD1 includes R, G, and B data, and the first FRC dithering unit 210 performs FRC dithering on each of the R, G, and B data. To this end, the first FRC patterns P11 to P14 may be stored for each color in the first LUT 218 .

The frame counter 212 corresponding to the frame determination unit counts the number of frames by counting the input vertical synchronization signal Vsync, and outputs the counted frame number information to the first LUT 218 .

The line counter 214 and the pixel counter 216 corresponding to the pixel position determining unit use the input synchronization signals Vsync, Hsync, DE, and DCLK to determine the pixel position of the currently input first image data VD1. is detected, and the detected pixel position information is output to the first LUT 218 .

For example, the line counter 214 counts the horizontal synchronization signal Vsync in a period in which the vertical synchronization signal Vsync and the data enable signal DE are simultaneously enabled to obtain a pixel vertical value of the first image data VD1. The position is sensed, and the pixel counter 216 counts the dot clock DCLK during the enable period of the data enable signal DE to detect the horizontal position of the first image data VD1, and the detected first image The pixel position information of the data VD1 is output to the first LUT 218 .

A plurality of first FRC patterns P11 to P14 are stored in the first LUT 218 . For example, as shown in FIG. 7 , each of the plurality of first FRC patterns P11 to P14 different for each frame has a size of 4*4 pixels, 0, 1/8, 2/8, 3/8, It includes a plurality of dithering blocks arranged so that the number of pixels having a dither value of [1] (black) gradually increases according to grayscale values of 4/8, 5/8, 6/8, and 7/8. Each dithering block having a size of 4*4 pixels has a dither value of [1] (black) or [0] (white), and a grayscale value is determined in proportion to the number of dither values [1]. In addition, in the plurality of first FRC patterns P11 to P14, the positions of pixels having a dither value of [1] are set differently for each frame with respect to the same grayscale value, and the position of the pixels of the same grayscale value is set differently according to frame information from the first frame counter 212 . Accordingly, the plurality of first FRC patterns P11 to P14 are sequentially selected.

In the plurality of first FRC patterns P11 to P14, the 4*4 pixel size of each dithering block and the position of the dithering bit “1” may be variously changed according to a designer's needs.

The first LUT 218 selects any one of the plurality of first FRC patterns P11 to P14 according to frame information from the frame counter 212, and selects one of the first image data VD1 from the selected first FRC pattern. Low-order bits LB1s For example, the low-order 3 bits LB1s of each color data and the dither value D1 corresponding to the pixel position information from the line counter 214 and the pixel counter 216 are selected for each color. print out

The adder 220 includes the remaining high-order bits UB1s of the first image data VD1, for example, the high-order 10 bits UB1s of each color data, and a dither value for each color selected and supplied by the first LUT 218 . (D1) is added, and second image data VD2, each color data having a size of 10 bits, is supplied to the timing controller 8 .

The enable signal EN generator 230 generates an enable signal EN in response to the input control signal CNT and a reset signal from the frame counter 212 to perform the second FRC dithering of the display device 100 . output to the unit 310 . The enable signal EN generator 230 receives a control signal CNT indicating a specific driving state in which the power-on timings of the host system 200 and the display device 100 are different from each other, and the frame counter 212 . After counting up to the set value (4), when a reset signal is input, an enable signal EN is generated and supplied to the second FRC dithering unit 310 of the display device 100 to provide a frame second FRC dithering unit ( 310 enables the frame counter 312 .

The second FRC dithering unit 310 built in the timing controller 300 is a frame determining unit generating frame information of the second image data VD2 supplied from the first FRC dithering unit 210 of the host system 200 . a frame counter 312 corresponding to , a line counter 314 and a pixel counter 316 corresponding to a second pixel position determining unit generating pixel position information of the second image data VD2; A second LUT that selects and outputs a dither value D2 for each color from a plurality of pre-stored second FRC patterns P21 to P24 based on the location information and the low-order bits LB2s for each color of the second image data VD2 318 and an adder for outputting the third image data VD3 by adding the dither value D2 for each color from the second LUT 318 to the upper bit UB2s for each color of the second image data VD2 (320).

In the second FRC dithering unit 310 , the frame counter 312 , the line counter 314 , the pixel counter 316 , and the adder 320 are the frame counter 212 and the line counter of the first FRC dithering unit 210 . 214 , the pixel counter 216 , and the adder 220 perform the same operation, and thus a detailed description thereof will be omitted.

The second LUT 318 includes a plurality of first FRC patterns P11 to P14 stored in the first LUT 218 and a plurality of second FRC patterns P21 to P14 different from each other. The plurality of second FRC patterns P21 to P14 have different positions of the dither value [1] for each frame, similar to the above-described first FRC patterns P11 to P14, and the second FRC patterns P21 to P14. Each of the dithering blocks includes a plurality of dithering blocks having a different number of dither values [1] according to the grayscale value of the lower bit LB2s, and each dithering block may have the same or different pixel size of 4*4 as shown in FIG. can

The frame counter 312 of the first FRC dithering unit 310 is enabled in response to the enable signal EN supplied from the first FRC dithering unit 210 of the host system 200 to count the number of frames, The counted frame information is output to the second LUT 318 . The second LUT 318 sequentially selects and uses a plurality of second FRC patterns P21 to P24 according to frame information from the frame counter 312 .

Accordingly, since the frame count values of the first and second FRC dithering units 210 and 310, that is, frame information, are matched by the enable signal EN, even in a specific driving state, the first FRC patterns P11 to P14 FRC noise can be prevented by always matching the application order of , and the application order of the second FRC patterns P21 to P24.

Meanwhile, the host system 200 assigns any one option line to the enable signal EN generated from the first FRC dithering unit 210 in an interface for transmitting a TTL (Transistor Transistor Logic) signal as shown in FIG. It may be supplied to the second FRC dithering unit 310 of the display device 100 .

Contrary to this, input is performed through various interfaces such as a low voltage differential signal (LVDS) interface for data transmission/reception between the host system 200 and the display device 100, a display port (DP) or an embedded display port (eDP) interface. The enable signal EN may be supplied from the host system 200 to the display device 100 .

The DP (Display Port) or eDP (embedded Display Port) interface is an interface method that integrates an LVDS interface and a Digital Visual Interface (DVI), and uses the host system 200 as a source unit and the display device 100 as a sink unit. to enable two-way communication. The host system 200 transmits image data to the display device 100 through the main link, and displays Display Port Configuration Data (DPCD), which is information for setting the eDP environment of the display device 100, through an auxiliary channel when the power is turned on. transmitted to the device 100 . Accordingly, the host system 200 includes the enable signal EN supplied from the first FRC dithering unit 210 in the DPCD and transmits it to the display device 100 , and the timing controller 300 enables the internal register. The frame counter 312 of the second FRC dithering unit 310 is adjusted to match the frame counter 212 of the first FRC dithering unit 210 by storing the signal EN and supplying it to the second FRC dithering unit 310 . can be enabled.

8 is a block diagram schematically illustrating a timing controller of a host system and a display device using an LVDS interface.

Referring to FIG. 8 , the host system 200 converts the image data VD2, the timing signal, and the enable signal EN from the first FRC dithering unit 210 into an LVDS format and displays them. to the timing controller 300 of the device 100 .

The timing controller 300 of the display device 100 restores the image data VD2, the timing signal, and the enable signal EN from the LVDS format transmitted from the host system 200 in the LVDS receiver 340 to the second FRC. It is supplied to the dithering unit 330 .

As shown in FIG. 9 , the LVDS transmitter 240 and the receiver 340 transmit and receive data in RGB units corresponding to one pixel per clock. The data format of one pixel unit transmitted per clock includes RGB data and timing signals DE, Vsync, and Hsync, and the LVDS transmitter 240 receives an enable signal EN from the first FRC dithering unit 210 . When is supplied, the enable signal EN is mapped to any one of at least two unused bits and transmitted.

For example, when the R/G/B data in the image data VD2 each has 10 bits, the LVDS transmitter 240 converts 35 bits per clock cycle P to 7 bits, as shown in FIG. 9 . Each is divided into 5 and transmitted through 5 transmission line pairs (A, B, C, D, E), and the clock is transmitted through one clock transmission line pair (CLK). 35 bits transmitted per clock cycle P are 10-bit first color data [DT10:DT19], 10-bit second color data [DT20:DT29], and 10-bit third color data [DT30:DT39] , a 1-bit data enable signal DE, a 1-bit vertical sync signal Vsync, a 1-bit horizontal sync signal Hsync, and a 1-bit enable signal EN.

The timing controller 300 supplies the enable signal EN supplied through the LVDS receiving unit 340 to the FRC dithering unit 310 to match the second frame counter 212 of the first FRC dithering unit 210 . The frame counter 312 of the FRC dithering unit 310 may be enabled.

The video display system according to the present invention controls the operation timing of the FRC dithering unit of the display device by supplying an enable signal from the FRC dithering unit of the host system whenever necessary, thereby always matching the application order of the FRC patterns of the host system and the display device have.

Accordingly, the image display system according to the present invention can prevent FRC noise due to mismatch between the FRC pattern of the host system and the FRC pattern of the display device.

In the above, it has been shown and described as a specific embodiment to illustrate the technical idea of the present invention, but the present invention is not limited to the same configuration and operation as the specific embodiment as described above, and various modifications do not depart from the technical spirit of the present invention. It can be implemented within the scope. Accordingly, such modifications should be considered to fall within the scope of the present invention, and the scope of the present invention should be determined by the following claims.

200: host system 210: first FRC dithering unit
100: display device 300: timing controller
310: second FRC dithering unit 20: data driver
30: gate driver 40: display panel
212, 312: frame counter 214, 314: line counter
216, 316: pixel counter 218: first LUT
318: second LUT 220, 320: adder
230: enable signal (EN) generator 240: LVDS transmitter
340: LVDS receiver

Claims (5)

A host system including a first FRC dithering unit for correcting and outputting first image data to second image data smaller than the number of bits of the first image data by using a plurality of first frame rate control (FRC) patterns that are different for each frame and;
Using a plurality of second FRC patterns different for each frame, the second image data supplied from the host system is corrected to be third image data smaller than the number of bits of the second image data, and outputted, and outputted from the host system. An image display system comprising a display device including a second FRC dithering unit whose operation time is controlled according to an enable signal. The method according to claim 1,
Displaying an image matching the order in which the plurality of first FRC patterns are applied by the first FRC dithering unit and the order in which the plurality of second FRC patterns are applied by the second FRC dithering unit by the enable signal system. The method according to claim 1,
The first FRC dithering unit
a first frame counter for counting the input vertical sync signal and outputting first frame information for selecting any one of the plurality of first FRC patterns;
and an enable signal generator for generating and outputting the enable signal to the display device when a control signal for controlling an operation time of the second FRC dithering unit is input from the host system;
The second FRC dithering unit
It is enabled when the enable signal is supplied from the enable signal generator of the host system, and a second method for selecting one of the plurality of second FRC patterns by counting the vertical synchronization signal supplied from the host system a second frame counter for outputting frame information;
A video display system in which the first frame information of the first frame counter and the second frame information of the second frame counter are matched in a predetermined order by the enable signal. 4. The method according to claim 3,
The enable signal generator generates the enable signal when the control signal is input and a reset signal is input from the first frame counter. 4. The method according to claim 3,
The enable signal is
supplied as an option signal from the host system to the display device;
The host system is mapped to at least one bit of the LVDS format through an LVDS (Low Voltage Differential Signal) interface between the display device and supplied;
An image display system included in Display Port Configuration Data (DPCP) and supplied through an embedded Display Port (eDP) interface between the host system and the display device.

Images