KR101604491B1 - Display device and driving method thereof - Google Patents

Abstract

The present invention relates to a display device, and more particularly, to a display device that compares a specific pattern stored in a memory with an input image to generate a bank selection signal of a first logic when substantially the same data as the specific pattern is input, A timing controller for generating a bank select signal of a second logic when the first bank select signal is input; And generating the gamma voltage as a first voltage in response to a first logic of the bank selection signal and generating the gamma voltage as a second voltage different from the first voltage in response to a second logic of the bank selection signal And a gamma voltage generating circuit. The output voltage swing width of the data driving circuit becomes smaller when data substantially the same as the specific pattern is input when data other than the specific pattern is input.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF

The present invention relates to a display device and a driving method thereof.

Various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs). Such a flat panel display may be a liquid crystal display, a field emission display (FED), a plasma display panel (PDP), an electroluminescence device (EL) ). The electroluminescent device EL is divided into an inorganic electroluminescent device and an organic light emitting diode (OLED) according to the material of the light emitting layer.

An active matrix liquid crystal display device displays a moving image by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be miniaturized as compared with a cathode ray tube (CRT), and is applied not only to a display device in a portable information device, an office machine, a computer, but also to a telvision, thereby quickly replacing a cathode ray tube. The liquid crystal display device includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a data driving circuit for supplying a data voltage to data lines of the liquid crystal display panel, gate lines (or scan lines) A control circuit for controlling the driving circuits, a light source driving circuit for the backlight unit, a power supply circuit for generating analog driving voltages of the liquid crystal display panel and a voltage required for driving the circuits, and the like Respectively.

When data of a specific pattern is input to the display device, the power consumption and the heat generation temperature of the drive circuit increase. The data of the specific pattern is data in which the white gradation data and the black gradation data alternate in a short period. When the data of this specific pattern is input, the data driving circuit must switch the analog voltage of the white gradation and the analog voltage of the black gradation quickly, so that the consumption current is increased and the heat generation temperature is also increased.

The present invention provides a display device and a driving method thereof capable of suppressing power consumption and temperature rise of driving circuits when data of a specific pattern is input when data of a specific pattern is input.

A display device of the present invention includes: a display panel in which data lines and gate lines cross each other; A data driving circuit for converting digital data into gamma voltages and supplying the digital data to the data lines; A gate driving circuit for sequentially supplying gate pulses to the gate lines; A memory for storing a specific pattern; A comparator for comparing a specific pattern stored in the memory with an input image to generate a bank select signal of a first logic when substantially the same data as the specific pattern is input and when a data other than the specific pattern is inputted, A timing controller for generating a bank selection signal; And generating the gamma voltage as a first voltage in response to a first logic of the bank selection signal and generating the gamma voltage as a second voltage different from the first voltage in response to a second logic of the bank selection signal And a gamma voltage generating circuit. The output voltage swing width of the data driving circuit becomes smaller when data substantially the same as the specific pattern is input when data other than the specific pattern is input.

The method of driving the display device includes: storing a specific pattern in a memory; A bank selection signal of a first logic is generated when substantially the same data as a specific pattern is inputted, and when a data other than the specific pattern is input, Generating a selection signal; And generating a gamma voltage as a first voltage in response to a first logic of the bank selection signal and generating the gamma voltage as a second voltage different from the first voltage in response to a second logic of the bank selection signal .

The present invention defines a specific pattern that causes power consumption and a rise in a heating temperature, defines it in a memory, and determines whether the specific pattern is input in an input image through a pattern recognition algorithm using a pattern stored in a memory. According to the present invention, when the data of the specific pattern is input, the gamma voltages inputted to the data driving circuit are adjusted to suppress the power consumption and the temperature rise of the driving circuit portions of the display device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

1 to 3, the liquid crystal display device of the present invention includes a liquid crystal display panel 100, a data driving circuit 102 connected to the data lines 105 of the liquid crystal display panel 100, a liquid crystal display panel A timing controller 101 for controlling the data driving circuit 102 and the gate driving circuit 103 connected to the gate lines 106 of the liquid crystal display panel 100; A power integrated circuit (hereinafter referred to as "power module IC") 105 for generating driving voltages, and a programmable gamma voltage generator 106 (hereinafter referred to as P- And a non-volatile memory 107.

The liquid crystal display panel 100 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel 100 includes a pixel array for displaying video data. The pixel array includes TFTs formed at intersections of the data lines 105 and the gate lines 106, pixel electrodes connected to the TFTs, storage capacitors connected to the pixel electrodes, and the like. The liquid crystal cells of the pixel array are driven by the voltage difference between the pixel electrode 1 for charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied so that the amount of light incident from the backlight unit And displays an image of the video data.

On the upper glass substrate of the liquid crystal display panel 100, a black matrix, a color filter, and a common electrode are formed. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode. The common electrode 2 is formed by a combination of IPS (In Plane Switching) mode and FFS Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system. The liquid crystal mode of the liquid crystal display panel 100 applicable to the present invention may be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above.

The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The data driving circuit 102 includes a plurality of source drive ICs. Each of the source drive ICs samples and latches the digital video data (RGB) input from the timing controller 101 under the control of the timing controller 101, and converts the digital video data into data of a parallel data system. Each of the source drive IC is used for the positive / negative gamma reference voltages (V _GMA1 ~ V _GMAN) from the digital video data converted to parallel data transmission system P-GMA circuit 106 into an analog gamma compensation voltage And generates a positive / negative analog video data voltage to be charged in the liquid crystal cells. And each of the source drive ICs inverts the polarity of the positive / negative analog video data voltage in accordance with the polarity control signal POL and supplies the data voltage to the data lines 105. [

The gate drive circuit 103 includes a plurality of gate drive ICs. The gate driving circuit 103 sequentially supplies gate pulses (or scan pulses) to the gate lines under the control of the timing controller 101.

The timing controller 101 receives RGB digital video data, a vertical synchronization signal Vsync, a horizontal synchronization signal Vsync from the system board 104 through an interface receiving circuit such as an LVDS (Low Voltage Differential Signaling) interface and a TMDS (Transition Minimized Differential Signaling) A timing signal such as a signal Hsync, a data enable signal DE, and a dot clock CLK. The timing controller 101 transmits RGB digital video data to the source drive ICs of the data driving circuit 102 in a mini LVDS interface manner. The timing controller 101 generates data timing control signals SSP, SSC and SOE and a polarity control signal POL for controlling the operation timings of the source drive ICs using the timing signals Vsync, Hsync, DE and CLK, And generates gate timing control signals GSP, GSC and GOE for controlling the operation timing of the gate drive circuit 103. [ The timing controller 101 controls the timing controller 101 so that the digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array of the liquid crystal display panel 100 at a frame frequency of 60 x i (i is a positive integer) And the frequency of the data timing control signal can be multiplied by a frame frequency reference of 60 x i Hz.

The data timing control signal includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), and a source output enable (SOE). The source start pulse SSP controls the data sampling start timing of the data driving circuit 102. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driving circuit 102 on the basis of the rising or falling edge. If the signal transmission scheme between the timing controller 101 and the data driving circuit 102 is a mini LVDS interface, the source sampling clock SSC and the source start pulse SSP may be omitted. The polarity control signal POL inverts the polarity of the data voltage output from the data driving circuit 102 in a period of N (N is a positive integer) horizontal period. The source output enable signal SOE controls the output timing of the data driving circuit. Each of the source drive ICs generates a charge share voltage or a common voltage Vcom in response to the pulse of the source output enable signal SOE when the polarity of the data voltage supplied to the data lines 105 is changed Data lines 105 and supplies the data voltages to the data lines during the low logic period of the source output enable signal SOE. The charge sharing voltages are average voltages of neighboring data lines to which data voltages of opposite polarities are supplied.

The gate timing control signals GSP, GSC and SOE include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE) . The gate start pulse (GSP) controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive circuit 103.

The timing controller 101 compares the input image data with a specific pattern stored in the nonvolatile memory 107 to determine whether the specific pattern data is input. The timing controller 101 outputs a bank selection signal SEL having a different logic value according to the presence or absence of data input of a specific pattern. The bank selection signal SEL is a control signal for adjusting the output voltage of the P-GMA circuit 106. The bank select signal SEL is generated with the first logic (e.g., high logic) when a specific pattern causing the power consumption of the source drive ICs and the rise in the heating temperature is input, while the normal data other than the specific pattern is input (E. G., Low logic). ≪ / RTI > The pattern recognition algorithm of the timing controller 101 is disclosed in Korean Patent Application Nos. 10-2008-0032638 (2008.04.08), Korean Patent Application 10-2008-0055419 (2008.06.12), 10- 2008-0134694 (Dec. 26, 2008), No. 10-2008-0134147 (Dec. 26, 2008).

The non-volatile memory 107 stores a predetermined pattern defined in advance. The specific pattern stored in non-volatile memory 107 may be modified, added, and deleted through I ² C communication and a ROM writer. Pulse information of the data timing control signals SSP, SSC and SOE, the polarity control signal POL and the gate timing control signals GSP, GSC and GOE may be stored in the nonvolatile memory 107. [ The non-volatile memory 107 may be an EEPROM (Electrically Erasable Programmable Read-Only Memory).

The system board 104 receives the RGB video data input from a broadcast receiving circuit or an external video source and outputs a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE, a dot clock CLK, To the timing controller 101 via the LVDS interface or the TMDS interface transmission circuit. The system board 104 includes a graphic memory for storing video data inputted from a broadcast receiving circuit or an external video source, a graphic processor for converting the resolution of the video data to a resolution of the liquid crystal display panel 100 and performing a signal interpolation process, Circuit, and a power supply circuit that generates a voltage (Vin) to be input to the power module IC 105, and the like.

The power module IC 105 generates analog driving voltages of the liquid crystal display panel 100 when the power supply voltage Vin is input from the system board 104. [ The analog driving voltages of the liquid crystal display panel 100 output from the power module IC 105 are divided into a high potential power supply voltage Vdd of 15V to 20V, a logic power supply voltage Vcc of 3.3V, V _GH ), a gate low voltage (V _GL ) of -3 V or lower, a common voltage (Vcom) between 7 V and 8 V, and the like. The high-potential power supply voltage Vdd is a maximum data voltage to be charged in the liquid crystal cells of the liquid crystal display panel 100. The logic power supply voltage Vcc is the driving voltage of the timing controller 101, the source drive ICs of the data drive circuit 102, the gate drive ICs of the gate drive circuit 103, and the P-GMA circuit 106. The gate high voltage V _GH is a high logic voltage of the gate pulse set above the threshold voltage of the TFTs formed in the pixel array and the gate low voltage V _GL is the gate voltage of the gate pulse Lt; / RTI > The gate high voltage V _GH and the gate low voltage V _GL are input to the gate drive ICs of the gate drive circuit 103. The common voltage Vcom is input to the common electrode 2 of the liquid crystal cells Clc. The high-potential power supply voltage (Vdd) is input to the P-GMA circuit 106.

The P-GMA circuit 106 adjusts the potentials of the positive / negative polarity in response to the bank selection signal SEL from the timing controller 101. P-GMA circuit 106 with positive polarity gamma reference voltage when the input is a specific pattern (V ~ V _{GMA1 GMAN / 2)} to lower the potential of the negative polarity gamma reference voltage _(GMA V _{(N / 2) +1} ~ V _GMAN ). Then, the source drive ICs have a smaller swing width of the output voltage when a specific pattern is input. The consumption current of the source drive ICs and the rise of the heat generation temperature can be suppressed when data of a specific pattern is inputted. P-GMA circuit 106 outputs the positive / negative gamma reference voltage when the normal data other than the specific pattern is input (V ~ V _{GMAN GMA1)} to normal values.

FIGS. 2 to 4 are diagrams showing examples of a specific pattern that causes power consumption and an exothermic temperature rise of the source drive ICs.

The specific pattern includes a pattern PTN1 in which white gradation and black gradation are alternated in the vertical direction as shown in Fig. 2, a pattern PTN2 in which white gradation and black gradation are alternated in the horizontal direction as shown in Fig. 3, And a pattern in which white gradation and black gradation are alternated in the horizontal direction. The specific pattern is not limited to those shown in FIG. 2 to FIG. 4, but data of a pattern causing the power consumption of the source drive ICs and the rise in the heat generation temperature may be defined as a specific pattern. The specific pattern is stored in the nonvolatile memory 107.

5 is a block diagram showing the P-GMA circuit 106 in detail. 6 is a diagram showing the output of a P-GMA circuit varying depending on whether or not a specific pattern is input.

5 and 6, the P-GMA circuit 106 includes first and second banks (banks 61A and 61B), a digital-to-analog conversion register (hereinafter referred to as a DAC register) 62, A control interface 63, and the like.

In the first bank 61A, gamma voltages for data of a specific pattern as shown in FIGS. 2 to 4 are stored as digital data. In the second bank 61A, normal gamma voltages for normal data other than the specific pattern are stored as digital data. If the logic of the bank selection signal SEL generated from the timing controller 101 is the first logic, the gamma data stored in the first bank 61A is input to the DAC register 62. [ When the logic of the bank selection signal SEL generated from the timing controller 101 is the second logic, the gamma data stored in the second bank 61B is input to the DAC register 62. [

DAC register 62 outputs the N s (N is a positive integer of 2 or more) of the gamma reference voltage (V _GMA1 ~ V _GMAN) to convert the gamma data to an analog voltage which is selected in accordance with the bank selection signal (SEL). DAC register 62 of the gamma reference voltage to the high-potential power supply voltage (Vdd) from the power module IC (105), the partial pressure (V _GMA1 ~ V _GMAN) generate, and the first and second banks (61A, 61B) adjusting the high-potential power supply voltage (Vdd) according to the data from the gamma may be adjusted by the voltage of the gamma reference voltage (V ~ V _{GMAN GMA1).} Furthermore, DAC register 62 is the gamma reference voltage by changing the resistance values of the voltage dividing circuit in accordance with the gamma data from the first and second banks (61A, 61B) by using a switch element connected to a voltage divider circuit (V _GMA1 ~ V _GMAN ) can be adjusted.

If the logic of the bank selection signal SEL generated from the timing controller 101 is the first logic, the DAC register 62 responds to the gamma data from the first bank 61A, lower than the low positive gamma reference voltage (V ~ V _{GMA9 GMA1),} it increases the negative of the top than the negative gamma reference voltage higher value (V _GMA10 ~ V _GMA18). Therefore, the DAC register 62 lowers the absolute value of the gamma reference voltages (V _GMA10 to V _GMA18 ) input to the source drive ICs when data of a specific pattern is input to the liquid crystal display device. At this time, the swing width of the data voltage output from the source drive ICs is reduced.

If the logic of the bank selection signal SEL generated from the timing controller 101 is the second logic, the DAC register 62 responds to the gamma data from the second bank 61B, restore to the positive polarity gamma reference voltage (V ~ V _{GMA9 GMA1),} and restore the negative gamma reference voltage with a negative top value (V _GMA10 ~ V _GMA18).

The control interface 63 receives the serial data SDA and the serial clock SCL input through the system board 104 and the user connector. The control interface 63 supplies the gamma data to the first and second banks 61A and 61B and controls the operation of the DAC register 62 in accordance with the serial data SDA and the serial clock SCL. The control interface 63 may modify the gamma data to be stored in the first and second banks 61A and 61B according to the serial data SDA and the serial clock SCL.

The inventors of the present application obtained experimental results shown in FIGS. 7 to 9 by repeating the experiment of inputting data of a specific pattern into a sample liquid crystal display and adjusting gamma voltages.

As the absolute value of the positive / negative polarity gamma voltages inputted to the source drive ICs is lowered when the specific pattern PTN1 shown in FIG. 2 and the specific pattern PTN2 shown in FIG. 3 are inputted to the liquid crystal display device, As a result of the experiment, we were able to lower the power consumption of the source drive ICs compared to the existing ones. However, when the absolute values of the positive / negative polarity gamma voltages inputted to the source drive ICs are reduced when the specific pattern PTN1 shown in FIG. 2 and the specific pattern PTN2 shown in FIG. 3 are inputted to the liquid crystal display device, The luminance measurement result and the luminance of the liquid crystal display panel are reduced. The data of the specific pattern includes approximately 50% of the black gradation as shown in FIGS. Therefore, although the luminance lowering measured by the luminance measuring device is relatively large as shown in FIG. 8, the observer does not noticeably notice a decrease in luminance when viewing a liquid crystal display device in which a specific pattern is displayed by black gradation portions.

As the absolute value of the positive / negative polarity gamma voltages inputted to the source drive ICs is lowered when the specific pattern PTN1 shown in FIG. 2 and the specific pattern PTN2 shown in FIG. 3 are inputted to the liquid crystal display device, As a result of the experiment, the temperature of the source drive ICs (D-IC), the power module IC (PWM IC, 105) and the P-GMA circuit (P-GMA, 106)

7 to 9, when the gamma voltage is lowered when a specific pattern is input, the power consumption and the heat generation temperature of the driving circuit portion can be reduced, but the luminance also decreases. In consideration of this, it is desirable to drop the gamma voltages within a range that the luminance of the observer is hardly sensed when the specific pattern is input. According to the experimental results shown in FIGS. 7 to 9, the optimal range of the gamma voltages should be lowered in the range of 2.5% to 10% of the conventional (normal value) range.

As another embodiment of the present invention, the gamma voltage drop can be made different depending on the form of the specific pattern. To this end, the present invention optimizes the gamma voltage drop across each of the specific patterns through experimentation. The timing controller 101 generates a bank selection signal SEL of 2 or more bits, and a bank is added to the P-GMA circuit 106.

Although the above embodiments have been described with reference to the liquid crystal display device, the present invention is not limited to the liquid crystal display device, but can be applied to any display device that converts digital data into a gamma voltage and supplies the gamma voltage to the display panel. For example, when the specific pattern as shown in FIGS. 2 to 4 is input to the organic light emitting diode (OLED), the present invention reduces the gamma voltages in the range of 2.5% to 10% The power consumption and the heat generation temperature of the data driving circuit for the data driving circuit can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIGS. 2 to 4 are diagrams showing examples of a specific pattern that causes power consumption and an exothermic temperature rise of the source drive ICs.

5 is a detailed block diagram of the P-GMA circuit.

6 is a diagram showing the output of a P-GMA circuit varying depending on whether or not a specific pattern is input.

FIGS. 7 to 9 are experimental results showing the effect of improving the power consumption and the exothermic temperature due to the gamma voltage drop.

Description of the Related Art

100: liquid crystal display panel 101: timing controller

102: Data driving circuit 103: Gate driving circuit

105: Power module IC 106: P-GMA circuit

107: Nonvolatile memory

Claims (8)

A display panel in which data lines and gate lines cross each other; A data driving circuit for converting digital data into gamma voltages and supplying the digital data to the data lines; A gate driving circuit for sequentially supplying gate pulses to the gate lines; A memory for storing a specific pattern; A comparator for comparing a specific pattern stored in the memory with an input image to generate a bank select signal of a first logic when substantially the same data as the specific pattern is input and when a data other than the specific pattern is inputted, A timing controller for generating a bank selection signal; And Generating a gamma voltage at a first voltage in response to a first logic of the bank selection signal and generating a gamma voltage at a second voltage different from the first voltage in response to a second logic of the bank selection signal, A voltage generating circuit, Wherein the output voltage swing width of the data driving circuit is reduced when substantially the same data as the specific pattern is input when data other than the specific pattern is input. The method according to claim 1, Wherein the first voltage is lower than the second voltage. The method according to claim 1, Wherein the first voltage comprises a positive first voltage and a negative first voltage, Wherein the second voltage comprises a second positive voltage and a second negative voltage, Wherein the gamma voltage includes a positive gamma voltage and a negative gamma voltage. The method of claim 3, Wherein the gamma voltage generating circuit generates the positive gamma voltage as the positive first voltage which is lower than the positive second voltage by 2.5% to 10% in response to the first logic of the bank selection signal, And generates the gamma voltage with the negative first voltage as high as 2.5% to 10% of the negative second voltage. (A) storing a specific pattern in a memory; (B) comparing and analyzing a specific pattern and an input image stored in the memory to generate a bank selection signal of a first logic when substantially the same data as the specific pattern is input, and Generating a bank select signal of two logic levels; And (C) generating a gamma voltage as a first voltage in response to a first logic of the bank selection signal, generating the gamma voltage to a second voltage different from the first voltage in response to a second logic of the bank selection signal And the output voltage swing width of the data driving circuit is reduced when substantially the same data as the specific pattern is input when data other than the specific pattern is input. 6. The method of claim 5, Wherein the first voltage is lower than the second voltage. 6. The method of claim 5, Wherein the first voltage comprises a positive first voltage and a negative first voltage, Wherein the second voltage comprises a second positive voltage and a second negative voltage, Wherein the gamma voltage includes a positive gamma voltage and a negative gamma voltage. 8. The method of claim 7, The step (C) When the bank selection signal is generated with the first logic, generates the positive polarity gamma voltage with the positive polarity first voltage as low as 2.5% to 10% of the positive polarity second voltage, Wherein the first negative voltage is generated by the negative first voltage as high as 2.5% to 10% of the second positive voltage.

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