CN204270290U - By the iic bus experimental provision of AccessPort - Google Patents

Abstract

The utility model relates to bus experimental provision, for overcoming prior art deficiency, realizing the visual commard editor window by host computer and checks or revise the data of certain register in peripheral hardware, and the rreturn value obtained can be presented at PC end intuitively.Operating personnel are made can more convenient, clearly to utilize IIC protocol debugging test chip.For this reason, the technical scheme that the present invention takes is, by the iic bus experimental provision of AccessPort, comprises host computer UART interface controller, conversion unit of protocol, iic bus interface controller and Clock Managing Unit; Clock Managing Unit respectively with host computer UART interface controller, conversion unit of protocol, iic bus interface controller be connected; Host computer UART interface controller is by serial ports sending and receiving data; Iic bus interface controller specifies peripheral hardware register data by iic bus transmitting-receiving.The utility model is mainly used in bus experiment.

Description

By the iic bus experimental provision of AccessPort

Technical field

The present invention relates to bus experimental provision, specifically a kind of iic bus experimental provision by AccessPort.

Technical background

IIC (Inter-Integrated Circuit, IC bus) bus is that the one of PHILIPS company exploitation is simple, two-way, two-wire system, synchronous serial bus, and it can solve passing through between each serial device.Be widely used in various electronic system at present, this bus physical only needs two signal line, serial data (SDA respectively, serial data) line carries out the transmission of the data-signal on iic bus and serial clock (SCL, serial clock) line carries out the clock signal transmission of iic bus in order to transmit and receive data.Because iic bus only needs two lines, decrease the space of circuit board, reduce the quantity of chip pin, save interconnected cost.Therefore iic bus is the bus of a kind of cheapness, high-quality, and it is applicable to the low speed devices in the fields such as consumer electronics, communication electronics, industrial electronic.

The major function of iic bus is the transmission realizing hardware device or intermodular data, can between equipment primary controller and controlled IIC equipment, carry out two-way transmission between IIC equipment and IIC equipment.Manufacturer is when production equipment simultaneously, each equipment has a unique Address Recognition, comprise microcontroller, LCD (Liquid Crystal Display, liquid crystal display) driver, storer or keyboard interface etc., therefore when system master controller and IIC are all connected in parallel on iic bus from equipment, master controller can carry out signal transmission by appropriate address to the arbitrary equipment in this bus, as shown in Figure 1.For the iic bus interface being integrated in chip internal, master controller normally microprocessor at a high speed, and the outside low-speed device of peripheral hardware normally some bands IIC interface.

Although iic bus is widely used, with low cost, because most of CPU does not have iic bus interface, some other chips are sometimes needed to adopt GPIO pin to do Simulation with I IC communication, its software and hardware combined debugging efforts very very complicated.Meanwhile, current PC generally has two serial ports COM1 and COM2, but most of low-speed device does not support serial ports UART protocol communication, therefore directly also cannot be realized by serial ports and chip communication for PC.

Summary of the invention

For overcoming the deficiencies in the prior art, solve current iic bus and debug complexity when data are transmitted and the shortcoming that can not ensure security and accuracy, the present invention proposes a kind of iic bus experimental provision by AccessPort, realize the visual commard editor window by host computer check or revise the data of certain register in peripheral hardware, the rreturn value obtained can be presented at PC end intuitively.It ensure that outside the original advantage of IIC, makes operating personnel can more convenient, clearly utilize IIC protocol debugging test chip.For this reason, the technical scheme that the present invention takes is, by the iic bus experimental provision of AccessPort, comprises host computer UART interface controller, conversion unit of protocol, iic bus interface controller and Clock Managing Unit; Clock Managing Unit respectively with host computer UART interface controller, conversion unit of protocol, iic bus interface controller be connected; Host computer UART interface controller is by serial ports sending and receiving data; Iic bus interface controller specifies peripheral hardware register data by iic bus transmitting-receiving.

Conversion unit of protocol comprises: state machine registers; The UART data receive register of 8, be used for temporary host computer UART interface controller send 8 bit data; The instruction storage register of 48; Comparator circuit, for judging that the instruction storage register of 48 receives the School Affairs of data; The UART data transmitter register of 8; The IIC director data transmitter register of 32, instruction and register address are kept in, next cycle is operated concrete peripheral hardware by IIC agreement, reads or writes.

Compared with the prior art, technical characterstic of the present invention and effect:

Traditional iic bus debug process is not only loaded down with trivial details but also easily make mistakes, iic bus interface controller of the present invention is when transmitting and receive data, directly instruction can be sent by host computer AccessPort software, operational order is easily understood, and make use of the general serial equipment of PC and unspecific IIC interface, save hardware resource, the application of non-specialized-technical personnel can be made simpler, convenient.

Accompanying drawing explanation

Fig. 1 is the applied environment schematic diagram of iic bus.

Fig. 2 is the iic bus interface control system general frame figure of band AccessPort function.

Fig. 3 is protocol conversion part Organization Chart provided by the invention.

Fig. 4 is the state transition diagram of protocol conversion module main control module of the present invention.

Fig. 5 is the application example schematic diagram that the present invention provides in conjunction with CH7301 chip.

Embodiment

Four parts are mainly comprised: a host computer UART interface controller, conversion unit of protocol, iic bus interface controller and Clock Managing Unit, as shown in Figure 2 by the structure of the iic bus experimental provision of AccessPort.

Wherein host computer UART interface controller is used for communicating with host computer, is responsible for receiving serial data that host computer imported into by UART agreement and is converted into parallel data, parallel data can also be dealt into host computer by the serial of UART agreement simultaneously; Conversion unit of protocol is responsible for the communicating of UART interface controller and iic bus interface controller, the transfer of coordination and system state machine controls; Iic bus interface controller is responsible for receiving instruction, peripheral hardware address, register address and data, if instruction is for writing, then by IIC agreement, data write is specified in the register of peripheral hardware, if instruction is for reading, is then read by IIC agreement and specify the value of the register of peripheral hardware and issue conversion unit of protocol; Clock Managing Unit is used for as iic bus interface controller and UART interface controller provide the clock frequency of standard.

In the present invention, conversion unit of protocol comprises: main control module, is responsible for the master control of whole conversion unit of protocol, state transfer judgement work; The UART data receive register of 8, be used for temporary host computer UART interface controller send 8 bit data; The instruction storage register of 48, whether correct in order to judge sending instruction by judging the last 8 bit check positions in 48 bit data; The UART data transmitter register of 8, be 8 bit data that read by IIC agreement when reading if be used for temporary instruction or represent that IIC write operation terminates the identification data FF sent, it can be dealt into the serial ports of host computer by next cycle by host computer UART interface controller module subsequently; The IIC director data transmitter register of 32, keeps in instruction and register address, and next cycle can send it to iic bus interface controller module, and is operated (reading or writing) concrete peripheral hardware by IIC agreement.As shown in Figure 3.

During work, each several part is initialization first, and UART interface controller module starts the data receiving host computer transmission; Conversion unit of protocol initialization, state machine state remains IDLE state; IIC interface control module does not receive commencing signal, SCL and SDA two signal wires are high level, and bus is in idle condition.

After host computer begins through UART agreement transmission signal, the serial data received turns and stored in the UART data receive register in conversion unit of protocol by UART interface controller, until data value is EF in register, then by its stored in instruction storage register last 8, main control module state machine enters next duty ready simultaneously, otherwise state machine state keeps IDLE constant.IIC interface control module does not receive commencing signal, SCL and SDA two signal wires are high level, and bus is in idle condition.

State machine state is after ready, represent that host computer starts to send correct instruction and data, first 8 is command bits, secondly 8 is the peripheral hardware address needing operation, 8 is the address of register in peripheral hardware again, last 8 is check bit in order to need to write the data of certain register in peripheral hardware to also have 8, wherein the value of check bit be before latter 8 of 48 bit data sums.Now send the Configuration of baud rate of data to the sample frequency of UART data receive register according to host computer serial ports, and by the data shifts in the data receive register that collects stored in instruction storage register, move to left 8 at every turn, circulation 5 times altogether, coexist in final injunction storage register storage 48 bit data.Temporary close UART data receive register receives data function and judges that whether the value of last 8 bit check positions is correct subsequently, namely comparator circuit is passed through, after judging 8 bit check positions value and front 48 bit data sums rear 8 whether equal, if equal, expression check bit is correct.If check bit is incorrect, comes back to IDLE state and empty all register values, opening UART data receive register simultaneously and again receive data; If check bit result is correct, state machine enters next duty trans and UART data receive register continues to keep closed condition.

State machine state is after trans, is sent to IIC interface controller by the 8th of instruction storage register the to the 39th bit data by IIC director data transmitter register, the next state work of the machine that simultaneously gets the hang of.

State machine is after work state, IIC interface controller is started working, i.e. first control SCL, SDA line sends commencing signal, afterwards according in 32 bit data that receive first 8 determine that instruction is for reading or writing, if instruction is for writing, then SDA line sends data sequence is first send 7 device addresses (first 7 in 8 device address data), R/W position is 0 afterwards, after receiving answer signal, send the register address of 8, send 8 after again receiving answer signal and need write data, finally send end signal, write settling signal to conversion unit of protocol feedback simultaneously, if instruction is for reading, then SDA line sends data sequence is first send 7 device addresses (first 7 in 8 device address data), R/W position is 0 afterwards, after receiving answer signal, send the readout register address of 8, send after receiving answer signal again and restart signal and send 7 device addresses, R/W position is 1 afterwards, 8 sense datas can be received and issued the UART data transmitter register of conversion unit of protocol after receiving answer signal, finally send response and end signal, run through signal to conversion unit of protocol feedback simultaneously.After conversion unit of protocol receives and writes settling signal, to UART data transmitter register stored in FF and state machine enters next state done; After conversion unit of protocol receives and runs through signal, state machine enters next state done.

State machine state is after done, serial ports data in UART data transmitter register in conversion unit of protocol being issued host computer of UART interface controller serial, stop after certain time sending, and start to receive host computer data simultaneously by it stored in the UART data receive register of conversion unit of protocol, if judge, its value is EF, then the ready that gets the hang of reworks; If its value does not change EF into, then the data before resending in UART data transmitter register in certain hour, again stop after certain time sending, start to receive data, so circulate.State machine state transition diagram as shown in Figure 4

Table 1 is order format code requirement provided by the invention

Table 1

For making the object, technical solutions and advantages of the present invention more clear, provide the specific descriptions of embodiment of the present invention below in conjunction with example.The software of host computer inside should support read operation, write operation, input data and record before the dialog box of operation.

Below in conjunction with Fig. 5, to the example of a CH7301 chip configuration, the invention will be further described: CH7301 is a display controller equipment, and its receives digital picture input signal, and is undertaken encoding and transmitting data by DVI.The working method of this chip first uses IIC agreement to be configured to select mode of operation and data-transmission mode, and next input data and number control signal in order to show in LCD display.Specifically, be exactly first change the value of 0x49 register into c0 by the process of IIC protocol configuration, the value that the value that the value of 0x21 register changes 09,0x33 register into changes 08,0x36 register into changes 60 into.Because the device address of CH7301 chip is 0x76.Therefore in conjunction with the present invention, utilize the serial debug software of host computer, after start, only need send 12 16 binary data just can complete 7301 chip registers rewritings or check work, first, send data EF and make system start to receive instruction, secondly instruction transmission 00 expression is carried out writing register manipulation, again send 7649c0 represent carry out write operation device address, register address and data, finally send check bit 8F.Open the receiving function of serial debug software afterwards, if receive ff, represent that write register is correct, next step operation can be carried out.When checking that if want whether write result correct simultaneously, only need by serial debug software write EF 01 76 49 00 C0, and open serial ports receive data function read result just can see Output rusults be whether before the C0 that writes.The writing mode of other registers all by that analogy, just can reach the object of debugging chip rapidly, accurately.

Claims (2)

1., by an iic bus experimental provision for AccessPort, it is characterized in that, comprise host computer UART interface controller, conversion unit of protocol, iic bus interface controller and Clock Managing Unit; Clock Managing Unit respectively with host computer UART interface controller, conversion unit of protocol, iic bus interface controller be connected; Host computer UART interface controller is by serial ports sending and receiving data; Iic bus interface controller specifies peripheral hardware register data by iic bus transmitting-receiving.

2. the iic bus experimental provision by AccessPort as claimed in claim 1, it is characterized in that, conversion unit of protocol comprises: state machine registers; The UART data receive register of 8, be used for temporary host computer UART interface controller send 8 bit data; The instruction storage register of 48; Comparator circuit, for judging that the instruction storage register of 48 receives the School Affairs of data; The UART data transmitter register of 8; The IIC director data transmitter register of 32, instruction and register address are kept in, next cycle is operated concrete peripheral hardware by IIC agreement, reads or writes.