CN115100996A - Display configuration circuit, method, micro display panel and electronic device - Google Patents
Display configuration circuit, method, micro display panel and electronic device Download PDFInfo
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- CN115100996A CN115100996A CN202210856386.0A CN202210856386A CN115100996A CN 115100996 A CN115100996 A CN 115100996A CN 202210856386 A CN202210856386 A CN 202210856386A CN 115100996 A CN115100996 A CN 115100996A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a display configuration circuit, a method, a micro display panel and an electronic device, wherein the display configuration circuit comprises: a first detection circuit, the input end of which is connected with the I2C bus, for detecting whether the communication is finished at the current time I2C; the second detection circuit is used for detecting whether the current moment is within the time of the display area; the first register is connected with the I2C bus and used for storing the configuration data transmitted by the I2C bus; a second register for storing configuration data for controlling a display circuit of the micro display panel; and the updating enabling circuit is arranged between the first register and the second register and is connected with the output ends of the first detection circuit and the second detection circuit, and when the I2C communication is finished and is in the non-display area time, the configuration data stored in the first register is updated into the second register.
Description
Technical Field
The invention relates to the field of electric digital data processing, in particular to a display configuration circuit and method for a micro display panel, the micro display panel and electronic equipment.
Background
Currently, microdisplay panels are configured using an I2C (Inter-Integrated Circuit) bus. In the I2C circuit, when a plurality of master devices and slave devices communicate with each other, only two wires are needed to be used for interconnection, namely a serial data line (SDA) and a Serial Clock Line (SCL), the SDA lines of all the master devices and the slave devices are connected to a common data line to occupy the common data line in a time-sharing manner to realize data transmission between two devices, and the SCL lines of all the master devices and the slave devices are connected to a common clock line to occupy the common clock line in a time-sharing manner to realize clocks transmission between two devices.
The inventor of the present invention has found that the I2C bus transmission speed of the micro display panel is slow and the time for configuring the register is random. In the case shown in fig. 1A, when the time for the I2C communication to configure the register is between two frames of video data, the display effect is not adversely affected; however, in the case shown in FIG. 1B, the time at which the I2C communication configures the register occurs in one frame of the display, e.g., in the ith frame of video data, at t 1 The register is configured at the beginning of time t 2 The configuration of the register is completed at a time, i.e. at t 2 Before the time the register is configuration A, at t 2 After time the register is configuration B, and t 2 The moment is in the ith frame, therefore, the video data of the ith frame is at t 2 Before the moment, the configuration A is adopted to display to obtain a display effect A, and the ith frame of video data is at t 2 And displaying by adopting the configuration B after the moment to obtain a display effect B, wherein the display of the frame is abnormal under the condition, and the sense of human eyes can jump, so that the user experience is not good.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a display configuration circuit and method for a micro display panel, and an electronic device, so as to solve the technical problem in the prior art that a display abnormality may occur in one frame of a display image.
According to a first aspect, embodiments of the present invention provide a display configuration circuit for a micro display panel, comprising:
a first detection circuit, an input end of which is connected with the I2C bus, and is used for detecting whether the communication is finished at the current time I2C;
the second detection circuit is used for detecting whether the current moment is within the time of the display area;
the first register is connected with the I2C bus and used for storing the configuration data transmitted by the I2C bus;
a second register for storing configuration data for controlling a display circuit of the micro display panel;
and the updating enabling circuit is arranged between the first register and the second register and is connected with the output ends of the first detection circuit and the second detection circuit, and when the first detection circuit and the second detection circuit detect that the I2C communication is finished and is in a non-display area time, the configuration data stored in the first register is updated into the second register.
Optionally, an input end of the second detection circuit is connected to a field sync signal, and is configured to detect whether the current time is in the display area time by detecting the field sync signal, and when the field sync signal changes, the second detection circuit detects that the current time is in the non-display area time.
Optionally, the first detection circuit comprises:
a first flip-flop, an input terminal of which is connected to an SDA line of the I2C bus, and configured to receive a current beat signal of an SDA signal and output a previous beat signal of the SDA signal;
the input end of the phase inverter is connected with the output end of the first trigger;
and the input end of the first AND gate is respectively connected with the SCL line and the SDA line of the I2C bus and the output end of the inverter, and the output end of the first AND gate is the output end of the first detection circuit.
Optionally, the second detection circuit comprises:
the input end of the second trigger is connected with the field synchronizing signal and is used for receiving the current beat signal of the field synchronizing signal and outputting the previous beat signal of the field synchronizing signal;
and the input end of the exclusive-or gate is respectively connected with the field synchronizing signal and the output end of the second D trigger, and the output end of the exclusive-or gate is the output end of the second detection circuit.
Optionally, the update enabling circuit comprises:
the input end of the second AND gate is respectively connected with the output ends of the first detection circuit and the second detection circuit;
a first input end of the selector is connected with the first register, a second input end of the selector is connected with the second register, a control end of the selector is connected with an output end of the second AND gate, and the selector selects to output the first input end when the control end receives a high level;
and the input end of the third trigger is connected with the output end of the selector, and the output end of the third trigger is connected with the second register and is used for receiving the current beat signal output by the selector and outputting the previous beat signal output by the selector.
Optionally, at least one of the first flip-flop, the second flip-flop, and the third flip-flop is a D flip-flop; or alternatively
When the first trigger is a D trigger, the D input end of the first trigger is connected with an SDA line of the I2C bus, and the clock input end is connected with a main clock signal of the micro display panel; or
When the second trigger is a D trigger, the D input end of the second trigger is connected with the field synchronizing signal, and the clock input end is connected with a main clock signal of the micro display panel; or
And when the third trigger is a D trigger, the D input end of the third trigger is connected with the output end of the selector, and the clock input end is connected with a main clock signal of the micro display panel.
According to a second aspect, an embodiment of the present invention provides a display configuration method for a micro display panel, including:
storing configuration data transmitted by the I2C bus through a first register;
detecting whether the communication is finished at the current time I2C and is within the display area time;
when I2C communication is detected to be finished and within the non-display area time, updating the configuration data stored in the first register into the second register;
and controlling the display circuit of the micro display panel by using the updated configuration data stored in the second register.
Optionally, the detecting whether the current time is within the display area time includes:
and when the field synchronizing signal change is detected, judging that the current moment is in the non-display area time.
According to a third aspect, an embodiment of the present invention provides a microdisplay panel, which includes the display configuration circuit of any one of the first aspect.
According to a fourth aspect, an embodiment of the present invention provides an electronic device, which includes the micro display panel according to the third aspect.
According to the display configuration circuit, the method, the micro display panel and the electronic device for the micro display panel of the embodiment of the invention, the configuration data transmitted by the I2C bus is temporarily stored in the first register 13, whether the I2C communication is finished and whether the communication is in the display area time is detected by the first detection circuit and the second detection circuit, when the I2C communication is finished and the communication is in the non-display area time, the configuration data stored in the first register is updated to the second register by the update enabling circuit, the display control circuit of the micro display panel can control the display circuit of the micro display panel by using the updated configuration data stored in the second register, because the time for updating the configuration data stored in the second register is between two frames of video data, the display effect is not adversely affected, and the phenomenon that one frame of display screen is abnormal, which may occur in the prior art, is avoided, the user experience is improved.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are schematic and are not to be understood as limiting the invention in any way, and in which:
FIG. 1A schematically illustrates a case where I2C communicates that the time to configure the register is between two frames of video data;
FIG. 1B schematically illustrates a case where the time at which the I2C communication configures the register occurs within a one-frame display;
FIG. 2 shows a schematic diagram of a display configuration circuit for a micro-display panel according to an embodiment of the invention;
FIG. 3 shows a schematic diagram of a display configuration circuit for a micro display panel according to another embodiment of the invention;
FIG. 4 illustrates a flow diagram of a display configuration method for a micro display panel according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
Fig. 2 illustrates a display configuration circuit for a micro display panel according to an embodiment of the present invention, which may include a first detection circuit 11, a second detection circuit 12, a first register 13, a second register 14, and an update enable circuit 15, as illustrated in fig. 2.
Specifically, an input terminal of the first detection circuit 11 is connected to the I2C bus, and is used for detecting whether the communication is finished at the current time I2C; the second detection circuit 12 is used for detecting whether the current time is within the display area time; the first register 13 is connected with the I2C bus and used for storing configuration data transmitted by the I2C bus; the second register 14 is used for storing configuration data for controlling the display circuit of the micro display panel; the update enable circuit 15 is disposed between the first register 13 and the second register 14 and connected to the output terminals of the first detection circuit 11 and the second detection circuit 12, and updates the configuration data stored in the first register 13 into the second register 14 when the first detection circuit 11 and the second detection circuit 12 detect that the I2C communication has ended and is within the non-display area time.
In the embodiment of the present invention, the first detection circuit 11 and the second detection circuit 12 can detect whether the communication at the current time I2C is finished or within the display area time in real time. In order to reduce power consumption, the first detection circuit 11 and the second detection circuit 12 may also intermittently detect whether the communication at the current time I2C is finished or is within the display area time, and the interval time may be periodic or aperiodic, which is not limited herein.
In the embodiment of the present invention, the second detection circuit 12 may detect whether the current time is in the display area time in various ways, for example, by detecting whether there is a valid video data frame transmission on a video data line. As a simplified detection manner, in an optional implementation manner of the embodiment of the present invention, as shown in fig. 2, an input end of the second detection circuit 12 is connected to a field synchronization signal, and whether the current time is within the display area time can be detected by detecting the field synchronization signal. This is because the field sync signal change occurs in the non-display time period, so that the second detection circuit 12 can detect whether the current time is within the display area time by detecting whether the field sync signal change, and when the field sync signal change, the second detection circuit 12 can determine that the current time is within the non-display area time. Therefore, whether the current time is in the display area time or not can be detected in a low-cost mode.
In the embodiment of the present invention, the first register 13 is not a register storing configuration data for controlling the display circuit of the microdisplay panel, the first register 13 is connected to the I2C bus, and since the display circuit is not controlled by the configuration data stored in the first register 13, the I2C bus can send the configuration data to the first register 13 at any time, and the first register 13 can store the configuration data immediately when receiving the configuration data sent by the I2C bus. Alternatively, the first register 13 temporarily stores the configuration data sent by the I2C bus, and when the first register 13 receives new configuration data, the previously stored configuration data may be cleared and only the newly received configuration data may be saved. The second register 14 is a register for storing configuration data for controlling the display circuit of the micro display panel, and the display control circuit (not shown) of the micro display panel controls the display circuit by using the configuration data stored in the second register 14. Alternatively, the second register 14 temporarily stores the configuration data sent by the first register 13 through the update enable circuit 15, and when the second register 14 receives new configuration data, the previously stored configuration data may be cleared and only the newly received configuration data may be saved.
When the I2C bus sends configuration data to the registers, in order to avoid the situation that the time for configuring the registers through I2C communication shown in fig. 1B occurs in one-frame display, the display configuration circuit for a micro display panel according to the embodiment of the present invention is configured with two registers, the first register 13 is connected with the I2C bus and is only used for storing the configuration data sent through the I2C bus, and the configuration data stored in the first register 13 cannot be directly used for controlling the display circuit of the micro display panel; the second register 14 stores configuration data for controlling the display circuit of the micro display panel, but the update enabling circuit 15 updates the configuration data stored in the first register 13 into the second register 14 only under a specific condition, that is, when the first detection circuit 11 and the second detection circuit 12 detect that the I2C communication has ended and is within the non-display area time, that is, the case shown in fig. 1A. In this case, the display control circuit of the micro display panel may control the display circuit of the micro display panel by using the updated configuration data stored in the second register 14, and since the time for updating the configuration data stored in the second register 14 is between two frames of video data, the display effect is not adversely affected, thereby avoiding a phenomenon that one frame of display image is abnormal, which may occur in the prior art, and improving user experience.
Fig. 3 shows a display configuration circuit for a micro display panel according to another embodiment of the present invention, which is further embodied with respect to the display configuration circuit for a micro display panel shown in fig. 2.
As shown in fig. 3, the first detection circuit 11 of the display configuration circuit may include a first flip-flop 111, an inverter 112, and a first and gate 113, wherein an input terminal of the first flip-flop 111 is connected to the SDA line of the I2C bus; the input end of the inverter 112 is connected to the output end of the first flip-flop 111, and is configured to receive the current beat signal of the SDA signal and output a previous beat signal of the SDA signal; the input terminals of the first and gate 113 are connected to the SCL line, the SDA line of the I2C bus and the output terminal of the inverter 112, respectively, and as a whole, the input terminal of the first detection circuit 11 is connected to the SDA line and the SCL line of the I2C bus, and the output terminal of the first detection circuit 11 is the output terminal of the first and gate 113. When the I2C communication is finished, the SCL line is at a high level, the level of the SDA line changes from low to high, that is, the SDA signal of the SDA line is at a low level before the SDA signal is at a low level and at a high level currently, at this time, the input end of the first and gate 113 connected to the SCL line and the SDA line receives a high level, the first flip-flop 111 outputs a low level, and the first and gate 113 changes to a high level after being inverted by the inverter 112, so that the first and gate 113 outputs a logic "1"; in other cases, first and gate 113 outputs a logic "0". That is, the first detection circuit 11 outputs a logic "1" at the end of the I2C communication and outputs a logic "0" in the other states, thereby achieving detection of whether or not the communication is ended at the current time I2C.
As an optional implementation manner of this embodiment, the first flip-flop 111 may be a D flip-flop, and when the first flip-flop 111 is a D flip-flop, a D input terminal of the first flip-flop 111 is connected to an SDA line of the I2C bus, and a clock input terminal is connected to a main clock signal of the micro display panel.
As further shown in fig. 3, the second detection circuit 12 of the display configuration circuit may include a second flip-flop 121 and an exclusive-or gate 122, wherein an input terminal of the second flip-flop 121 is connected to the field sync signal for receiving a current beat signal of the field sync signal and outputting a previous beat signal of the field sync signal; the input terminals of the xor gate 122 are respectively connected to the field sync signal and the output terminal of the second flip-flop 121, and as for the second detection circuit 12 as a whole, the input terminal of the second detection circuit 12 is connected to the field sync signal, and the output terminal of the second detection circuit 12 is the output terminal of the xor gate 122. Since the field sync signal changes in the non-display time interval, when the field sync signal changes, the current beat of the field sync signal is different from the previous beat, the input end of the xor gate 122 receives the current beat and the previous beat of the field sync signal, respectively, and the xor gate 122 outputs a logic "0" through the xor to output a logic "1" under other conditions. That is, the second detection circuit 12 outputs a logic "1" when the current time is within the non-display area time, and outputs a logic "0" in other states, thereby realizing the detection of whether the current time is within the display area time.
As an optional implementation manner of this embodiment, the second flip-flop 121 may be a D flip-flop, and when the second flip-flop 121 is a D flip-flop, the D input terminal of the first flip-flop 111 is connected to the field synchronization signal, and the clock input terminal is connected to the main clock signal of the micro display panel.
Continuing with FIG. 3, the input terminals of the first register 13 of the display configuration circuit are connected to the SDA line and SCL line of the I2C bus respectively to store the configuration data transmitted by the I2C bus. An input of the second register 14 is connected to an output of the update enable circuit 15.
Further, the update enabling circuit 15 of the display configuration circuit may include a second and gate 151, a selector 152 and a third flip-flop 153, wherein an input terminal of the second and gate 151 is connected to output terminals of the first detection circuit 11 and the second detection circuit 12, respectively, that is, an input terminal of the second and gate 151 is connected to output terminals of the first and gate 113 and the xor gate 122, respectively; a first input end of the selector 152 is connected with the first register 13, a second input end is connected with the second register 14, a control end of the selector 152 is connected with an output end of the second and gate 151, and the selector 152 selects and outputs the first input end when the control end receives a high level; the input terminal of the third flip-flop 153 is connected to the output terminal of the selector 152, and the output terminal is connected to the second register 14, and is configured to receive the current beat signal output by the selector 152 and output the previous beat signal output by the selector 152. In the case where the I2C communication has ended and is within the non-display area time, the first and gate 113 outputs logic "1", the xor gate 122 also outputs logic "1", so that the second and gate 151 outputs logic "1", and the second and gate 151 outputs logic "0" in other states. When the second and gate 151 outputs a logic "1", the selector 152 selectively outputs the first input terminal, so that the configuration data stored in the first register 13 is output to the second register 14 in the next beat, and the display control circuit of the microdisplay panel can control the display circuit by using the configuration data stored in the second register 14.
As an optional implementation manner of this embodiment, the third flip-flop 153 may be a D flip-flop, and when the third flip-flop 153 is a D flip-flop, a D input terminal of the third flip-flop 153 is connected to an output terminal of the selector 152, and a clock input terminal is connected to a main clock signal of the micro display panel.
In the display configuration circuit for a micro display panel of the present embodiment, the first and gate 113 outputs a logic "1" when the I2C communication has ended, the second and gate 151 outputs a logic "1" when in the non-display region time, the selector 152 selects to output the first input terminal in the case where the I2C communication has ended and is in the non-display region time, that is, the configuration data stored in the first register 13 is output to the second register 14, the display control circuit of the micro display panel can control the display circuit of the micro display panel by using the updated configuration data stored in the second register 14, since the time to update the configuration data stored by the second register 14 is between two frames of video data, the display effect is not adversely affected, the phenomenon that one frame of display image is abnormal, which may occur in the prior art, is avoided, and the user experience is improved.
Fig. 4 illustrates a display configuration method for a micro display panel according to an embodiment of the present invention, which may include the steps of:
s21, storing the configuration data transmitted by the I2C bus through a first register.
In this embodiment, the first register 13 is connected to the I2C bus and is only used for storing the configuration data transmitted by the I2C bus, and the configuration data stored in the first register 13 cannot be directly used for controlling the display circuit of the micro display panel. Therefore, the I2C bus can send configuration data to the first register 13 at any time, and the first register 13 can store the configuration data immediately when receiving the configuration data sent by the I2C bus.
S22, detecting whether the I2C communication is finished at the current time and whether the communication is in the display area time, executing the step S23 when detecting that the I2C communication is finished and is in the non-display area time, otherwise executing the step S22 again.
The method for detecting whether the communication is ended and within the display area time at the current time I2C can refer to the related description of the embodiments shown in fig. 2 and fig. 3, for example. In an alternative embodiment, it can be determined that the current time is in the non-display area time by detecting whether the field sync signal changes. Of course, in the embodiment of the method, the method of detecting whether the communication at the current time I2C is finished and whether the communication is in the display area time is not limited to the above-described detection method by the hardware detection circuit, and other methods such as software detection are also possible.
S23, the configuration data stored in the first register is updated to the second register.
When the I2C communication is finished and within the non-display area time, the time for updating the configuration data stored in the second register 14 is between two frames of video data, which does not cause adverse effect on the display effect, avoids the phenomenon that one frame of display image is abnormal, which may occur in the prior art, and improves the user experience.
When the communication is ended and the period of non-display area is within the time when the non-compliant I2C communication is ended, if the configuration data stored in the second register 14 is updated at this time, the situation shown in fig. 1B may occur, which may cause an abnormality in displaying a frame. Therefore, in this case, it is necessary to perform step S22 again until the condition that the I2C communication has ended and is within the non-display area time is satisfied. As an alternative embodiment, when the condition that the I2C communication has ended and is within the non-display area time is not met, step S22 may not be executed again immediately, but step S22 may be executed again after waiting for a predetermined time. The predetermined time required to wait can be set by those skilled in the art according to practical situations.
S24, controlling the display circuit of the micro display panel using the updated configuration data stored in the second register.
In the display configuration method for the micro display panel according to the embodiment of the present invention, the configuration data transmitted by the I2C bus is temporarily stored in the first register 13, and when the I2C communication is completed and the configuration data is within the non-display area time, the configuration data stored in the first register 13 is output to the second register 14, and the display control circuit of the micro display panel may control the display circuit of the micro display panel by using the updated configuration data stored in the second register 14, and since the time for updating the configuration data stored in the second register 14 is between two frames of video data, the display effect is not adversely affected, a phenomenon that one frame of display screen is abnormal, which may occur in the prior art, is avoided, and the user experience is improved.
Embodiments of the present invention also provide a microdisplay panel that can include the display configuration circuitry described in the embodiments illustrated in fig. 2 and 3 above. The display control circuit of the micro display panel of the embodiment can utilize the updated configuration data stored in the second register 14 in the display configuration circuit to control the display circuit of the micro display panel, and because the time for updating the configuration data stored in the second register 14 is between two frames of video data, the display effect is not adversely affected, the phenomenon that one frame of display image is abnormal, which may occur in the prior art, is avoided, and the user experience is improved.
Correspondingly, the embodiment of the invention also provides electronic equipment which comprises the micro display panel, so that the phenomenon that one frame of display image is abnormal, which may occur in the prior art, is avoided, and the user experience is improved.
The details of the micro display panel and the electronic device can be understood by referring to the corresponding related descriptions and effects in the embodiments shown in fig. 2 and fig. 3, which are not repeated herein.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (10)
1. A display configuration circuit for a microdisplay panel, comprising:
the input end of the first detection circuit is connected with the I2C bus and used for detecting whether the communication is finished at the current time I2C;
the second detection circuit is used for detecting whether the current moment is within the time of the display area;
the first register is connected with the I2C bus and used for storing the configuration data transmitted by the I2C bus;
a second register for storing configuration data for controlling a display circuit of the micro display panel;
and the updating enabling circuit is arranged between the first register and the second register and is connected with the output ends of the first detection circuit and the second detection circuit, and when the first detection circuit and the second detection circuit detect that the I2C communication is finished and is in the non-display area time, the configuration data stored in the first register is updated into the second register.
2. The display configuration circuit of claim 1, wherein the input terminal of the second detection circuit is connected to a field synchronization signal for detecting whether the current time is in the display region time by detecting the field synchronization signal, and the second detection circuit detects that the current time is in the non-display region time when the field synchronization signal changes.
3. The display configuration circuit of claim 1, wherein the first detection circuit comprises:
a first flip-flop, an input terminal of which is connected to an SDA line of the I2C bus, and configured to receive a current beat signal of an SDA signal and output a previous beat signal of the SDA signal;
the input end of the inverter is connected with the output end of the first trigger;
and the input end of the first AND gate is respectively connected with the SCL line, the SDA line and the output end of the inverter of the I2C bus, and the output end of the first AND gate is the output end of the first detection circuit.
4. A display configuration circuit according to any of claims 1-3, wherein the second detection circuit comprises:
the input end of the second trigger is connected with the field synchronizing signal and is used for receiving the current beat signal of the field synchronizing signal and outputting the previous beat signal of the field synchronizing signal;
and the input end of the exclusive-or gate is respectively connected with the field synchronizing signal and the output end of the second D trigger, and the output end of the exclusive-or gate is the output end of the second detection circuit.
5. The display configuration circuit according to any of claims 1-4, wherein the update enable circuit comprises:
the input end of the second AND gate is respectively connected with the output ends of the first detection circuit and the second detection circuit;
a first input end of the selector is connected with the first register, a second input end of the selector is connected with the second register, a control end of the selector is connected with an output end of the second AND gate, and the selector selects to output the first input end when the control end receives a high level;
and the input end of the third trigger is connected with the output end of the selector, and the output end of the third trigger is connected with the second register and is used for receiving the current beat signal output by the selector and outputting the previous beat signal output by the selector.
6. The display configuration circuit of any of claims 3-5, wherein at least one of the first flip-flop, the second flip-flop, and the third flip-flop is a D flip-flop.
7. A display configuration method for a microdisplay panel, comprising:
storing the configuration data transmitted by the I2C bus through a first register;
detecting whether the communication is finished at the current time I2C and is within the display area time;
when I2C communication is detected to be finished and within the non-display area time, updating the configuration data stored in the first register into the second register;
and controlling the display circuit of the micro display panel by using the updated configuration data stored in the second register.
8. The method according to claim 7, wherein the detecting whether the current time is within the display area time comprises:
and when the field synchronizing signal change is detected, judging that the current moment is in the non-display area time.
9. A microdisplay panel comprising the display arrangement circuit of any one of claims 1-6.
10. An electronic device comprising the micro display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210856386.0A CN115100996B (en) | 2022-07-21 | 2022-07-21 | Display configuration circuit, method, micro display panel and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210856386.0A CN115100996B (en) | 2022-07-21 | 2022-07-21 | Display configuration circuit, method, micro display panel and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115100996A true CN115100996A (en) | 2022-09-23 |
| CN115100996B CN115100996B (en) | 2022-12-13 |
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| CN115100996B (en) | 2022-12-13 |
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