KR20050001295A - Method for managing memory embedded in processor and device thereof - Google Patents

Abstract

PURPOSE: A method and a device for managing a memory embedded in a processor without a separate clock are provided to read/write data to the memory without the separate clock, as a read/write time point is synchronized by making a high or low condition with use of an SCL(Serial Clock line) signal or an SDA(Serial DAta Line) signal depending on an I¬2C method. CONSTITUTION: A clock controller(302) selects one from a clock signal of the processor or the SCL signal of an application device as the clock for managing the memory. Using the SCL signal and the SDA signal of an I¬2C bus protocol, a signal processor(301) receives information for managing the memory from the application device, changes a processor managing mode to an application device managing mode, writes or reads the data from the memory in case of a high condition on the application device managing mode, and changes the application device managing mode to the processor managing mode again in case of a low condition after reading or writing.

Description

Method for managing memory embedded in processor and device

The present invention relates to a memory, and more particularly, to a method and apparatus for managing a memory embedded in a processor.

Processors such as a CPU, a digital signal processor (DSP), or an application specific instruction processor (ASIP) are often embedded with memory for storing programs and data. This built-in memory is normally managed by the processor and receives management information from the processor for recording or reading the clock and data for synchronization of the system.

However, in order to initially load, test, or debug a program, it may be necessary to write or read a program or data to an internal memory in an external application. In particular, for debugging when the processor is in an error state, it is necessary to write or read data to an internal memory from an external application without receiving clock or management information from the processor.

As a method for satisfying such a need, there is a method of managing memory using a Joint Test Action Group (JTAG) method. 1 is a block diagram of a system to which a method of managing a memory by a conventional JTAG method is applied. Referring to FIG. 1, the JTAG application 101 writes / reads data to a memory 103 embedded in the processor 104. At this time, a separate clock 102 is required for synchronization, and a dedicated pin (TCK, TDL, DO, TMS, TRST) for transmitting management information is required. Through the dedicated pins, as management information for writing / reading the memory, information including an address, data, and a control command is transferred from the JTAG application device 101 to the memory 103.

In this case, however, as shown in FIG. 1, a separate clock 102 is required for memory management, and 4-5 separate dedicated pins are required to transfer management information to the memory. In addition, there is a problem that the JTAG method cannot be used as a bus for general memory writing / reading except for test or debugging purposes.

Accordingly, an object of the present invention is to provide a method and an apparatus for managing a memory embedded in a processor without a separate clock without receiving a clock or management information from the processor.

1 is a configuration diagram of a system to which a method of managing a memory by a conventional JTAG method is applied;

2 is a configuration diagram of a system to which a memory management method is applied according to the present invention;

3 is a block diagram of a memory management unit 201 according to the present invention;

4A and 4B illustrate memory management information according to the present invention. Diagram showing SCL signal, SDA signal and frame structure according to the scheme,

5A and 5B are diagrams showing HIGH and LOW signal conditions for memory write / read and management mode conversion in accordance with the present invention;

6A is a diagram illustrating a method of writing data to a memory in accordance with the present invention;

6B is a diagram illustrating a method of reading data from a memory in accordance with the present invention;

7 is a flowchart illustrating a memory management method according to the present invention.

The above object is, in accordance with the present invention, a method of managing a memory embedded in a processor, the method comprising: Receiving information for managing a memory from an application through an SCL signal and an SDA signal of a bus protocol; (b) changing the processor management mode to the application device management mode according to the control command information among the received information; (c) in the application device management mode, when the SCL signal and the SDA signal satisfy the HIGH condition, writing or reading data into the memory; And (d) if the SCL signal and the SDA signal satisfy the LOW condition after writing or reading, changing the application management mode back to the processor management mode.

Step (a) is information for managing the memory, and preferably receiving information including an address, data, or a control command for writing or reading data in the memory.

Step (b) comprises: (b1) setting a switch register indicating that writing or reading is being performed in the memory if the received control command information is an ACTIVE control command; And (b2) selecting a SCL signal received from an application as a clock for managing the memory.

The HIGH condition in step (c) is a signal condition that generates a clock for synchronizing the timing at which the application device writes / reads the memory. It is preferable that it is a signal condition in the case where the SDA signal level is kept as it is, and the SCL signal level is 1.

Step (d) may include: (d1) confirming whether the SCL signal and the SDA signal satisfy a LOW condition; (d2) selecting a clock signal received from a processor as a clock for managing the memory; (d3) resetting the switch register; And (d4) if the data has been read, transmitting the read data to an application device,

The LOW condition is a signal condition that generates a clock for synchronizing the timing at which the application device changes to the processor management mode after completing the writing / reading of the memory. The SDA signal level is changed when the SCL signal level is 0 after the STOP signal. It is preferable that it is a signal condition in the case where the SDA signal level is kept intact while changing from 1 to 0 and the SCL signal level is 1.

On the other hand, according to another field of the present invention, the above object is a clock for selecting any one of the clock signal of the processor or the SCL signal of the application device in the device for managing the memory embedded in the processor as a clock for managing the memory Control unit; And By using the SCL signal and the SDA signal of the bus protocol, it receives information for managing the memory from the application, changes the processor management mode to the application management mode, and when the HIGH condition is reached in the application management mode, the data is stored in the memory. It is also achieved by an apparatus comprising a signal processing section for recording or reading and for changing the application management mode back to the processor management mode when the LOW condition is reached after writing or reading.

On the other hand, according to another field of the present invention, the object is a processor with a built-in memory; And a system-on-chip equipped with a device for managing the memory.

The processor preferably includes at least one of a CPU, a DSP, and an ASIP.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a configuration diagram of a system to which a memory management method according to the present invention is applied.

Referring to FIG. 2, the memory manager 201 manages a memory 203 embedded in the processor 204. That is, from the application 202 Through the SCL signal and the SDA signal according to the bus method, management information for writing / reading a clock and a memory is received, and the memory is managed based on this. Usually, the memory is usually managed by receiving clock and management information from the processor (hereinafter referred to as a processor management mode). However, when a request from the application device 202 is requested, the application device (instead of the clock or management information from the processor) is used. The memory is managed by a clock or management information from 202 (hereinafter referred to as an 'application device management mode'). Herein, the management information is information necessary for recording / reading data in the memory, and refers to the address ADDR of the memory to be recorded / read, the data DATA to be recorded, and the control command (CONTROL) information. The control command information includes a write or read command (RW) and an ACTIVE command (also referred to as a CE (Enable Chip) command) to switch from the processor management mode to the application device management mode to execute memory write / read. The clock includes a clock CLK supplied from the processor 204 and a clock SCL supplied from the application device 202, and may select which clock to use in the memory manager 201. The bus method is a synchronous bidirectional two-wire bus method using two lines of clock (SCL) and data (SDA) as an IC-to-IC communication method proposed by Philips. The method of specifically communicating through this method will be described later.

Hereinafter, the memory manager 201 according to the present invention will be described in detail.

3 is a block diagram of the memory management unit 201 according to the present invention.

Referring to FIG. 3, the memory manager 201 includes a clock controller 302 and a signal processor 301.

When there is a request (ACTIVE instruction) from the application, the clock controller 302 supplies the clock SCL from the application 202 to the memory 203 instead of the clock CLK from the processor 204.

The signal processor 301 is provided from the application device 202. Memory management information is received through the SCL signal and the SDA signal according to the bus method. The memory management information includes the address of the memory to be written or read, data, control command information, and the like. The received information is provided to the memory 203 upon request from the application 202.

In addition, when the signal processing unit 301 receives the ACTIVE command from the application device 202, the signal processing unit 301 changes the processor management mode to the application device management mode. Or, if the condition is LOW after reading, change the application management mode back to the processor management mode.

In this case, the change of the processor management mode to the application device management mode means that the clock and memory management information from the application device 202 is written or read from the memory by the clock and memory management information from the processor 204. Memory is written / read by That is, upon receiving the ACTIVE control command, a switch register (SW) indicating that recording / reading is being performed is set in the memory, and the SCL signal received from the application device 202 is selected as a clock for managing the memory. The switch register SW serves to latch the memory manager so that the processor or another device does not attempt to write / read data while writing / read data to the memory. That is, when the switch register SW is set, memory writing / reading is impossible on another device, and this register must be reset to enable memory writing / reading from a processor or other device.

In addition, when the SCL signal and the SDA signal satisfy the HIGH condition in the application device management mode, data is stored in the memory according to the SCL clock and memory management information received from the application device 202, that is, address, data, and control command information. Write or read.

When the above-described writing / reading process is completed and the SCL signal and the SDA signal satisfy the LOW condition, the controller changes to the processor management mode again and writes data to the memory according to the clock and memory management information received from the processor 204. Will be read.

Below, A method of managing memory by receiving clock and memory management information from an application using the SCL signal and the SDA signal according to the scheme will be described.

4A and 4B illustrate memory management information according to the present invention. Diagram showing SCL signal and SDA signal and frame structure according to the scheme.

Referring to FIG. 4A, a START condition and a STOP condition are shown as signal conditions for transmitting management information from an application to a memory manager. This condition It follows the standard method and will not be described separately. According to the standard method, the memory manager corresponds to a slave, and the application device corresponds to a master. When the START condition is reached, the memory manager receives an address ADDRESS of the memory for writing / reading, an R / W control command indicating whether to write or read, and data to be read. The STOP condition indicates that the transmission of management information has ended.

4b shows the structure of the frame. Referring to FIG. 4B, not only one byte of data but also several bytes of data may be recorded / read.

5A and 5B are diagrams showing HIGH and LOW signal conditions for memory write / read and management mode conversion in accordance with the present invention.

Referring to FIG. 5A, it can be seen that the HIGH condition H and the LOW condition L are newly defined between the STOP condition P where the transmission of management information is terminated and the next START condition S. FIG. The HIGH condition indicates the clock signal to write / read data to memory in the application management mode. That is, the memory manager writes one byte of data into the memory in synchronization with the HIGH condition. On the other hand, the LOW condition indicates when to end the memory write / read and transition to the processor management mode. The memory manager resets the switch register SW in the LOW condition and changes to the processor management mode.

Specifically, the HIGH condition is a signal condition for generating a clock for synchronizing the time when the application device writes / reads the memory. The SDA signal level is changed from 0 to 1 while the SCL signal level is 0 after the STOP signal. It is defined as a signal condition when the SDA signal level is maintained while the signal level is 1. On the other hand, the LOW condition is a signal condition for generating a clock for synchronizing the time when the application device is changed to the processor management mode after finishing writing / reading the memory. The SDA signal with the SCL signal level 0 after the STOP signal is 0. It is defined as a signal condition when the level is changed from 1 to 0 and the SDA signal level is maintained while the SCL signal level is 1.

Accordingly, even though the clock management unit does not receive the clock CLK, the memory manager may write / read data in synchronization with the HIGH condition defined by the SCL signal and the SDA signal, thereby managing the memory without a separate clock. do.

Fig. 5B shows a signal condition in the case of recording / reading 4 bytes of data. One byte of data is written for each HIGH condition, and when the LOW condition is reached, the switch register SW is reset and the processor management mode is changed.

A method of managing a memory embedded in a processor according to a preferred embodiment of the present invention based on the configuration and communication method as described above is as follows.

6A is a diagram illustrating a method of writing data to a memory in accordance with the present invention.

Referring to FIG. 6A, the memory manager 201 receives memory address information, data to be recorded, and control command information to record data from the application device 202 (①, ②, and ③). The control command information may include a WRITE control command or an ACTIVE control command (CE command) for recording data in the memory.

Next, when the ACTIVE control command is received, the memory manager 201 sets the switch register SW indicating that recording / reading is being performed in the memory (4). Then, the application device management mode is changed to use the clock SCL of the application device instead of the clock CLK of the processor as the clock for writing / reading (5). Now, when the SCL signal and the SDA signal received from the application apparatus satisfy the HIGH condition, data is written to the memory 203 (6). When the above signal satisfies the LOW condition, the processor register mode is changed to the processor management mode so as to use the clock CLK of the processor instead of the clock SCL of the application device (7), and the switch register SW is reset (8). .

6B is a diagram illustrating a method of reading data from a memory in accordance with the present invention.

Referring to FIG. 6B, the memory manager 201 receives memory address information and control command information for reading data from the application device 202 (1 and 3). The control command information may include a READ control command or an ACTIVE control command for reading data into the memory.

Next, when the ACTIVE control command is received, the memory manager 201 sets the switch register SW indicating that recording / reading is being performed in the memory (4). Instead of the clock CLK of the processor, the application device management mode is changed to use the clock SCL of the application device (5). Now, when the SCL signal and the SDA signal received from the application satisfy the HIGH condition, the memory 203 is read (6). When the above signal satisfies the LOW condition, the processor register mode is changed to the processor management mode so as to use the clock CLK of the processor instead of the clock SCL of the application device (7), and the switch register SW is reset (8). . Finally, the read data is transmitted to the application device 202 (9).

7 is a flowchart illustrating a memory management method according to the present invention.

Referring to FIG. 7, when the SCL signal and the SDA signal received from the application device satisfy the START condition (step 701), the memory controller receives address, data, or control command information as memory management information (step 702). . If there is an ACTIVE control command among the received control command information (step 703), the switch register (SW) is set (step 704), and it is returned from the application device instead of the clock CLK received from the processor to change to the application device management mode. The clock SCL is supplied to the memory (step 705). If the SCL signal and the SDA signal received from the application satisfy the STOP condition (step 706), it is determined whether the aforementioned signal is a HIGH condition (step 707), and if the control command is WRITE (step 708), the data is written to the memory. If the control command is READ (step 709), data is read from the memory (709 '). If the above-described signal satisfies the LOW condition (step 710 or 710 '), the clock CLK from the processor is supplied to the memory instead of the clock SCL from the application device to change to the processor management mode ( Step 711 or step 711 '), the switch register SW is reset (step 712 or step 712'). In the case of the READ control command, the read data is transmitted to the application (step 713 ').

The above description is only one embodiment of the present invention, and those skilled in the art may implement the present invention in a modified form without departing from the essential characteristics of the present invention. Therefore, the scope of the present invention should not be limited to the above-described examples, but should be construed to include various embodiments within the scope equivalent to those described in the claims.

As described above, according to the present invention, the memory built in the processor can be managed without receiving a clock or management information from the processor. In other words, Depending on the method, the SCL signal and the SDA signal can be used to create a HIGH condition or a LOW condition to synchronize the write / read points of the memory, so that data can be written to or read from the memory without a separate clock.

In particular, the conventional JTAG method requires a separate clock and 4-5 dedicated pins, and is limited to test purposes only, and does not require a separate clock, and only two pins for the SCL signal and the SDA signal can be used. Can manage It can also be used as a regular bus after testing and debugging, which makes it more versatile than conventional methods.

Claims (9)

In the method of managing the memory embedded in the processor, (a) Receiving information for managing a memory from an application through an SCL signal and an SDA signal of a bus protocol; (b) changing the processor management mode to the application device management mode according to the received control command information; (c) in the application device management mode, when the SCL signal and the SDA signal satisfy the HIGH condition, writing or reading data into a memory; And (d) after the writing or reading, if the SCL signal and the SDA signal satisfy the LOW condition, changing the application device management mode back to the processor management mode. The method of claim 1, The step (a) is the information for managing the memory, characterized in that for receiving information including address, data, or control command for writing or reading data in the memory. The method of claim 1, Step (b) is (b1) if the received control command information is an ACTIVE control command, setting a switch register indicating that writing or reading is in memory; And (b2) a clock for managing the memory, comprising selecting an SCL signal received from the application. The method of claim 1, The HIGH condition of the step (c) is a signal condition for generating a clock for synchronizing the time when the application device writes / reads the memory, and the SDA signal level is set in the state where the SCL signal level is 0 after the STOP signal. And a signal condition when the SDA signal level is maintained in the state where the signal is changed from 0 to 1 and the SCL signal level is 1. The method of claim 1, Step (d) (d1) checking whether the SCL signal and the SDA signal satisfy a LOW condition; (d2) selecting a clock signal received from the processor as a clock for managing the memory; (d3) resetting the switch register; And (d4) if the data has been read, transmitting the read data to the application. The method of claim 1, The LOW condition of the step (d) is a signal condition for generating a clock for synchronizing the time when the application device is changed to the processor management mode after completing the writing / reading of the memory, the SCL signal level after the STOP signal And the SDA signal level is changed from 1 to 0 in the state of 0, and the SDA signal level is maintained in the state in which the SCL signal level is 1. A device for managing memory embedded in a processor, A clock control unit which selects one of a clock signal of the processor and an SCL signal of an application device as a clock for managing a memory; And By using the SCL signal and the SDA signal of the bus protocol, it receives information for managing the memory from the application, changes the processor management mode to the application management mode, and when the HIGH condition is reached in the application management mode, the data is stored in the memory. And a signal processor for recording or reading, and changing the application management mode back to the processor management mode when the LOW condition is reached after the recording or reading. A processor with a built-in memory; And a device according to claim 7 for managing the memory. The method of claim 8, The processor includes at least one of a CPU, DSP, and ASIP.