TWI470421B - Microprocessor and debugging method thereof - Google Patents

Description

Microprocessor and its debugging method

The present invention relates to a multi-core microprocessor, and more particularly to an instruction execution and debug method for monitoring a multi-core microprocessor.

The current microprocessor is very complex and debugging it is a very difficult task. Microprocessor developers often use a software functional model to simulate the architectural behavior of a microprocessor as a debugging tool. The software function module is more useful than other software modules such as the Verilog simulator, because it can more quickly simulate the execution of a large number of instructions. The software function module is defined according to the system architecture, and each time a single instruction is executed, the single core processor can be effectively debugged.

Software function modules can also be used to debug multi-core processors. Different examples of software function modules are used to simulate instruction execution on each core, as long as the cores do not interact with each other. It can be simulated very well. However, multi-core processors often generate some errors, and these errors usually only occur when memory accesses between multiple cores, or when cores share the same memory address, such as sharing a software signal (software) Semaphore). Each core will essentially access a shared memory address at different times, for example, the first core reads a semaphore and waits for the second core to write the signal. Unless the two examples of the software function module execute instructions, which is very similar to the order of the instructions executed by the actual processor when an error occurs, the software function module cannot effectively debug the multi-core processor. It is therefore desirable to have a sequence that controls the execution of instructions by the cores being simulated, which approximates the order of the multi-core processors of the post-silicon.

The invention discloses a debugging method of a microprocessor, wherein the microprocessor has a plurality of cores. The method includes: causing a microprocessor to perform an actual execution of the instruction, and obtaining a heartbeat information from the microprocessor, which clearly indicates an actual execution sequence of execution of the instructions between the cores (actual execution sequence) ). The method also includes commanding a plurality of related examples of the software function module to execute the instructions according to the actual execution order to generate a simulation result of the instruction execution. The method further includes comparing the simulation result with the actual result of the instruction execution to determine whether the two are in conformity.

The present invention discloses a microprocessor comprising a plurality of cores, each core outputting an instruction execution indicator for indicating the number of instructions executed by each core during each clock. The microprocessor further includes a heartbeat generator that receives an instruction execution indication from each core. The heartbeat generator is configured to generate a heartbeat indicator for each processing core on the external busbar in response to the instruction execution indication, and the heartbeat indication indicates each core of each clock in the external busbar. The number of instructions executed during the cycle.

The invention further discloses a microprocessor comprising a plurality of cores, each core generating an instruction execution indicator for indicating the number of instructions executed by each core during each clock cycle. The microprocessor further includes a memory array that stores instruction execution instructions generated by the cores during a clock cycle. The microprocessor further includes a bus interface unit coupled to the bus bar external to the microprocessor. The bus interface unit is used to write an instruction execution instruction stored in the storage array to the internal memory of the microprocessor.

The multi-core processor mentioned in the embodiment of the present invention is used to generate a heartbeat signal to indicate the execution instruction rate of each core. The processor developer can obtain the heartbeat signal as the processor operates, and use the obtained heartbeat information to dynamically control the rate at which each core software function module executes instructions for each core. In this way, the heartbeat signal provides a clear indicator to the software function module, so that it can glimpse the internal operations of the required multi-core processor to control the order in which the simulated cores execute instructions with each other. This sequence will approximate the actual occurrence. The order of execution instructions for the wrong multi-core processor. In some embodiments, the processor provides heartbeat information on the system processor bus, but this affects the timing of execution of the program on the multi-core processor, resulting in an enable heartbeat. When I missed some errors. Therefore, in the embodiment of the present invention, the processor non-invasively provides a heartbeat signal on the external sideband bus instead of providing a heartbeat signal on the system bus.

Please refer to the first figure, which is a functional block diagram of a computer system 100 having a dual core processor 102 disclosed in the present invention. A dual core processor 102 generates a heartbeat signal 106. The computing system 100 includes a dual core processor 102 that includes two cores, such as a first core 104A and a second core 104B, which may be collectively referred to as a core 104. In the embodiment of the present invention, each core 104 of the dual core processor 102 is a microprocessor core that conforms to the VIA NanoTM architecture designed by VIA Technologies, Inc. ). Although the present embodiment is exemplified by a dual core processor, other processors that use the heartbeat signal 106 to provide information to multiple cores are also within the scope of the present invention.

The dual core processor 102 further includes a heartbeat generator 103 coupled to each of the cores 104. Specifically, the first core 104A generates an instruction execution indicator 105A for indicating the number of instructions executed in a clock cycle; the second core 104B generates an instruction execution indicator 105B. Used to indicate the number of instructions executed in a clock cycle, the heartbeat generator 103 generates a heartbeat signal 106 to indicate that the core 104 has executed an instruction in response to the instruction execution indication 105. In an embodiment of the invention, core 104 performs the hypothetical execution of the instructions, and instruction execution indication 105 informs heartbeat generator 103 that the instructions have been completed, that is, unlike the hypothetical execution, it still updates the system state of core 104.

The computer system 100 further includes a memory 112 coupled to the dual core processor 102. Each core 104 of the dual core processor 102 can be programmed to periodically stop executing user program instructions and dump the current state. A predetermined address to the memory 112, and the contents of the cache memory itself are flushed to the memory 112, which is considered a checkpoint. The state of core 104 includes the state of its internal register, which is considered herein as a checkpoint state. More specifically, each core 104 can be programmed to continue executing a predetermined number of instructions (eg, 100,000 instructions), then stop executing instructions, store checkpoint status, read cache memory, and re- Execute instructions and other actions until the next time a predetermined number of instructions are accumulated, repeat the above actions, and so on.

Computer system 100 in turn includes a logic analyzer 108, which in one embodiment of the present invention includes one of cores 104 of dual core processor 102. The logic analyzer 108 monitors the processor bus 114 and retrieves the above transactions, including writing checkpoint status to the memory 112 and reading data from the cache. The logic analyzer 108 also monitors and retrieves the heartbeat signal 106, which stores the retrieved information into a file 116, such as a disk drive, and the folder 116 includes the retrieved processor sink. The transmission information 118 and the heartbeat signal information 122 are transmitted. In the embodiment of the present invention, the heartbeat signal 106 is provided to the dual core processor 102 on a sideband bus. For example, the sideband busbar is a JTAG busbar, which can be The dual core processor 102 is used internally by a separate service processor.

Computer system 100 further includes a software functional model simulation environment 124 that includes one or more analog computer systems that are distinct from computer system 100 that includes microprocessor 102. The software function module simulation environment 124 simulates the operation of the dual core processor 102 using the processor bus transmission information 118 and the heartbeat signal information 122 captured and stored in the folder 116, as will be described in more detail below.

Please refer to the second figure again, which is a functional block diagram of the software function module simulation environment 124 disclosed by the present invention. The software function module simulation environment 124 includes a simulated initial state generator 202, a rate controller 204, a first core software function module example 206A, and a second core software. A functional module example 206B, an actual result generator 208, and a comparison function 226. Although these components are made by software, some or all of the components can also be implemented by hardware to increase the execution speed.

The simulated initial state generator 202 receives the captured processor bus information 118 for generating a simulated initial memory image 212, a simulated initial state 214A of the first core, and a second The core's simulated initial state 214B. Subsequently, the simulated initial memory image 212 is copied as a simulated result memory image 232, and the simulated initial state 214A of the first core is copied to a first core simulation result state 234A, and The second core simulation initial state 214B is then copied to a second core simulation result state 234B. For convenience of explanation, it is assumed that each core 104 has stored a first checkpoint state (including the state of the internal scratchpad described above), and has flushed the contents of the cache memory itself, and re-executes the predetermined number of instructions. After that, a second checkpoint is stored and the contents of the cache memory are read. In addition, it is further assumed that the processor bus transmission information 118 includes bus transmissions of the first and second checkpoints and all transmissions between the two, which are generated by executing a predetermined number of instructions. See U.S. Provisional Patent Application No. 61/297,505, filed on January 22, 2010, which describes the method of synchronizing checkpoints between two cores 104.

According to an embodiment of the invention, the simulated initial state generator 202 generates the simulated initial memory map 212 by:
(1) Detecting the transmission of the address in the memory 112 between the first checkpoint and the second checkpoint in the dual core processor 102.
(2) It is judged whether the above-mentioned read transmission is the transmission of reading the address for the first time between the first and second checkpoints.
(3) If yes, a memory location record is generated for this transmission, which includes the memory address and the read data value. By the above method, the simulated initial state generator 202 produces a small amount of the simulated initial memory map 212. However, a small amount of memory image can meet the requirements of the software function module example 206, because between the first and second checkpoints, the software function module example 206 only needs to read the previously generated memory address, and if not, That is, an error is generated on the actual dual core processor 102.

The simulated initial state generator 202 can directly derive the first checkpoint state from the processor bus transfer information 118 to generate the simulated initial state 214A of the first core. In the embodiment of the present invention, as described above, at each checkpoint, each core 104 writes its own state information to a predetermined address in the memory 112 according to a predetermined format, which causes the simulated initial state to be generated. The device 202 can find the first checkpoint status of the first core 104A within the processor bus transfer information 118. Similarly, the simulated initial state generator 202 also generates the simulated initial state 214B of the second core directly from the first checkpoint state retrieved from the processor bus transfer information 118.

The actual result generator 208 receives the processor bus transfer information 118 in the first figure for generating a first core actual result state 224A, a second core actual result state 224B, and an actual result memory map 222. The actual result generator 208 generates the actual result state 224A of the first core directly from the second checkpoint state retrieved from the processor bus transfer information 118. According to an embodiment of the present invention, as described above, at each checkpoint, each core 104 writes its own checkpoint state to a predetermined address in the memory 112 according to a predetermined format, which enables The actual result generator 208 finds a second checkpoint state that can be found within the processor bus transfer information 118 to find the first core 104A. Similarly, the actual result generator 208 also generates the actual result state 224B of the second core directly from the second checkpoint state retrieved from the processor bus transfer information 118. The comparing unit 226 compares the actual result state 224A of the first core with the simulation result state 234A of the first core, and compares the actual result state 224B of the second core with the simulation result state 234B of the second core, Further discussion will be given later.

In the embodiment of the present invention, the actual result generator 208 generates the actual result memory map 222 by the following method:
(1) detecting transmission of an address in the memory 112 between the first checkpoint and the second checkpoint in the dual core processor 102, the transmission including each core 104 at the second checkpoint The self cache memory content is written to the memory 112.
(2) It is judged whether the above write transmission is between the first and second checkpoints, and the last write address transmission is performed on this address.
(3) If yes, a memory location record is generated for this transmission, which includes the memory address and the written data value. With the above method, the actual result generator 208 produces a small number of actual result memory maps 222. However, a small amount of memory image can satisfy the software function module example 206 requirement, because between the first and second checkpoints, the software function module example 206 only needs to write the previously generated memory address. If not, it indicates that an error has occurred on the actual dual core processor 102. The situation in which the comparison unit 226 will compare the actual result memory map 222 with a simulation result memory map 232 will be discussed further below.

The rate controller 204 receives the heartbeat signal information 122 captured in the first figure, and generates a command 218A to the first core software function module example 206A, and generates a command 218B to the second core software function module example. 206B. Command 218A Dynamic Control Software Function Module Example 206 The rate at which instructions are executed between each other. In the embodiment of the present invention, each command 218 controls the software function module example to execute N instructions, where N is defined in the command. In another embodiment, the software function module example 206 is multi-threaded and communicates with each other through, for example, a semaphore. In the embodiment of the present invention, the command controls a software function module instance 206 of a core 104 to execute X instructions until the software function module example 206 of the other core 104 executes Y instructions. The following illustration will detail how the rate controller 204 uses the heartbeat signal information 122 to issue commands 218 to dynamically control the rate at which the software function module instances 206 execute instructions with each other.

Each software function module example 206 simulates the system behavior of the core 104. The first core software function module example 206A accesses (read/write) the first core simulation result state 234A, and the second core software function module example 206B accesses (read/write) the second core simulation result State 234B. In addition, each software function module example 206 also reads and/or writes the simulation result memory map 232 in accordance with commands of the rate controller 204 when the memory access instruction is executed. In particular, when the data is written by the first core software function module example 206A to the simulation result memory image 232, the second core software function module example 206B will know, and vice versa, thus affecting the software function respectively. The simulation result state 234 of the module example 206. After each predetermined number (eg, 100,000) of instructions is executed by each software function module instance 206, the simulated initial state 214A of the first core copied to the first core simulation result state 234A will be updated to become the first The core simulation result state 234A, and the simulated initial state 214B of the second core copied to the second core simulation result state 234B, will also be updated to become the true second core simulation result state 234B. The comparison unit 226 compares the simulation result state 234A of the first core with the actual result state 224A of the first core, and compares the simulation result state 234B of the second core with the actual result state 224B of the second core to determine the true Whether the dual core processor 102 has an error between the first and second checkpoints is indicated by the pass/fail indicator 228. In addition, after each predetermined number (eg, 100,000) of instructions is executed by each software function module instance 206, the value of the simulated initial memory image 212 copied to the simulation result memory image 232 will be updated to become a true simulation. Result memory map 232. The comparison unit 226 compares the simulation result memory map 232 with the actual result memory map 222 to determine whether the true dual core processor 102 has an error between the first and second checkpoints, and the comparison result is taken from / No indicator indicated.

Thus, via the advantage of using rate controller 204 as an intermediary, heartbeat signal information 122 can be used to dynamically control the rate at which each software function module instance 206 executes instructions. That is, the rate controller 204 can control the order in which the software function module examples 206 execute instructions between each other, such that the instructions can be executed in an appropriate order in accordance with the proper order in which the core 104 accesses the memory, so that the instructions can be accurately The operational behavior of the actual dual core processor 102 is simulated from the actual initial state of each core 104 and memory 112, that is, the comparison unit 226 can compare the operational behavior of the actual dual core processor 102 with its simulated operational behavior. .

Please refer to the third figure, which is a flowchart of a method for operating the simulation environment 124 in the second diagram disclosed in the present invention. As shown in the third figure, the software function module simulation environment 124 first generates a simulation result memory map 232 and a simulation result state 234 according to step S1406 in FIG. 14 which will respectively correspond to the actual result memory map 222. And the actual result state 224 is compared (step S1408). The flow begins in step S302.

In step S302, the rate controller 204 receives the heartbeat signal information 122 from the folder 116. The flow then proceeds to step S304.
In step S304, the rate controller 204 checks the value of the heartbeat signal 106 of each core 104 in the next clock cycle of the heartbeat signal 106 indicated by the heartbeat signal information 122. The value of the heartbeat signal 106 will be further illustrated in the following embodiments and figures. The flow then proceeds to step S306.
In step S306, the rate controller 204 determines whether the core N (the first core 104A or the second core 104B) generates a heartbeat. If yes, go to step S308; otherwise, go back to step 304 to detect the next clock cycle.
In step S308, the rate controller 204 issues a command 218 to drive the software function module instance 206 of the core N to execute one or more instructions based on the determined heartbeat information, as will be described in more detail later. The flow then proceeds to step S312.
Next, in step S312, the software function module example 206 of the core N executes the next instruction or an instruction related to the simulation result memory map 232 and the simulation result state 234. If a memory read command is executed, the software function module instance 206 of core N will read the analog result memory map 232. If a memory write command is executed, the software function module example 206 updates the simulation result memory map 232 to the core N. Then, returning to step S304, the next clock cycle is continued.
The instruction execution instructions 105, the heartbeat generator 103, the heartbeat signal 106, and various embodiments used by the rate controller 204 are described below.
Please refer to the fourth figure, which is a functional block diagram of a specific embodiment of a dual core processor disclosed in the present invention. In the fourth and fifth figures, the core 104 has the same clock rate as the heartbeat signal 106. In addition, core 104 can execute one instruction per core clock cycle. As shown, the instruction execution indication 105 of each core 104 is a bit. If the core 104 completes an instruction within the core clock cycle, then the bit is true (true), otherwise false (false) . Similarly, the heartbeat generator 103 generates a one-bit heartbeat signal 106A, which is true if the first core 104A has completed an instruction within the core clock cycle, otherwise false; and the heartbeat generator 103 generates One-bit heartbeat signal 106B, if the second core 104B has completed an instruction in the core clock cycle, then the bit is true, otherwise it is false. However, it should be noted that there may be a delay time when the instruction execution instruction 105 and its associated heartbeat signal 106 are generated. In an embodiment, since the core 104 and the heartbeat signal 106 operate according to different clock sources, the heartbeat generator 103 includes synchronization logic for synchronizing the instruction execution indication 105 and the heartbeat signal 106.
Please refer to the fifth figure, which discloses an operation example table of the rate controller 204 in the fourth embodiment. The six clock cycles are included in the chart, labeled 0-5, which correspond to the six clocks in the heartbeat signal information 122 received by the rate controller 204 in the third step S302. The heartbeat signal 106A of the first core 104A and the heartbeat signal 106B of the second core 104B received by the rate controller 204 from the heartbeat signal information 122 are also as shown. In addition, in each clock cycle, according to the judgment of step S306 in the third figure, the graph indicates whether the rate controller 204 controls the first core software function module example 206A during the corresponding analog clock cycle. The instruction is executed, and whether the second core software function module example 206B is controlled to execute the instruction. In this example, the heartbeat signal 106A of the first core 106A at clocks 1, 3-5 is true, so the rate controller 204 will command the software function of the first core during the simulated clocks 1, 3-5. Group Example 206A executes the instructions. On the other hand, the second core 106B is true at the heartbeat signal 106B of the clock 0-2, 4, so the rate controller 204 will command the second core software function module during the simulated clock 0-2, 4. Example 206B executes the instructions.
Please refer to the sixth figure again, which is a functional block diagram of another embodiment of the dual core processor disclosed in the present invention. The sixth and seventh graphs are similar to the fourth and fifth graphs, and the core 104 has the same clock rate as the heartbeat signal 106. However, in this embodiment, the core 104 can execute multiple instructions in each core clock cycle, for example, three, or other numbers, not limited to the exposer. As shown, the instruction execution instructions 105 for each core 104 are two bits that indicate the number of instructions that the core 104 has executed during a core clock cycle. Similarly, the heartbeat generator 103 generates a two-element heartbeat signal 106A for indicating the number of instructions executed by the first core 104A during a core clock cycle and generating a two-element heartbeat signal 106B for indicating The number of instructions executed by the second core 104B during a core clock cycle.
Please refer to the seventh figure, which is an operation example of the rate controller according to the sixth embodiment, which is similar to the chart of the fifth figure. However, as shown, in each clock cycle, the value of the heartbeat signal 106A of the first core 104A received by the rate controller 204 from the heartbeat signal information 122 will include 0-3 instead of 0 (false). Or 1 (true). Similarly, in each clock cycle, according to the judgment of step S306 in the third figure, the graph indicates whether the rate controller 204 will follow the step S308 in the third figure during the corresponding analog clock cycle. Controlling the first core software function module example 206A to execute the instruction (if yes, indicating how many instructions are executed), and whether to control the second core software function module example 206B to execute the instruction (if yes, it will be marked with How many instructions are executed). In the present example, the first core 104A is 0 in the heartbeat 0, 2, 0 in the clock 4, 2 in the clock 3, and 3 in the clock 1, 5, therefore, The rate controller 204 will execute the first core software function module example 206A during the simulated clock 0, 2, executing 0 instructions; during the simulated clock 4, executing 1 instruction; in the simulated clock 3 During the execution, 2 instructions are executed; and during the simulated clock 1, 5, 3 instructions are executed. On the other hand, the second core 104B has a heartbeat signal 106B of 0 in clocks 3, 5, 1 in clocks 0, 4, and 2 in clocks 1, 2, and no heartbeat signal 106B in any of the clocks. 3, therefore, the rate controller 204 commands the second core software function module example 206B to execute 0 instructions during the simulated clocks 3, 5; during the simulated clocks 0, 4, one instruction is executed; During the simulated clock 1, 2, 2 instructions are executed; there is no clock to execute 3 instructions.
Please refer to the eighth figure, which is a functional block diagram of still another embodiment of the dual core processor disclosed in the present invention. The eighth and ninth diagrams are similar to the sixth and seventh diagrams, and each core 104 can complete multiple instructions per core clock cycle. However, in this embodiment, the clock rate of the core 104 is several times the clock rate of the heartbeat signal 106, for example, ten times, and may be other numbers, not limited by the exposer. In addition, the instruction execution instructions 105 of each core 104 are all one bit. When the core 104 completes a predetermined number of instructions, the bit is true (true), otherwise it is false. In an embodiment, the number of reservations is 32, but is not limited to the disclosure. In particular, the number of subscriptions must be at least as large as the product of the clock ratio and the maximum number of instructions that each core 104 can complete in a clock cycle. In one embodiment, the retire unit of the core 104 includes a counter for counting the number of instructions completed in each clock cycle, and the instruction execution indication 105 is an effective bit of the counter. M (M = log2N), where N is the product of the clock ratio and the maximum number of instructions that core 104 can complete in a clock cycle. Similarly, the heartbeat generator 103 generates a one-bit heartbeat signal 106A in accordance with the instruction execution instruction 105A, and generates a one-bit heartbeat signal 106B in accordance with the instruction execution instruction 105B.
Please refer to the ninth figure, which is an operation example of the operation rate controller according to the eighth embodiment of the present invention. The chart of this embodiment is similar to the fifth figure, but it should be noted that in the fifth and seventh figures, since the clock rate of the core 104 is the same as the clock rate of the heartbeat signal 106, the heartbeat signal information per clock cycle is the same. 122 indicates that one or more instructions are completed in the corresponding core clock cycle, and therefore, the clock cycles of the core and heartbeat signals 106 in the figure correspond to each other (clocks 0-5). However, in the ninth figure, the heartbeat signal information 122 per clock cycle indicates the number of instructions completed in a plurality of clock cycles, and therefore, the clock cycle shown in the figure corresponds to only the heartbeat signal 106. . Further, in each clock cycle, according to the judgment of step S306 in the third figure, the graph indicates whether the rate controller 204 is during the corresponding analog clock cycle, as described in step S308 of the third figure. Control passes the command 218A to instruct the first core software function module instance 206A to execute 32 instructions, and whether to control the second core software function module instance 206B to execute 32 instructions via the command 218B. In this example, the heartbeat signal 106A of the first core 106A at the clocks 1, 5 is true. Therefore, 32 clocks are simulated at the clocks 1 and 5 of the heartbeat signal 106, and the rate controller 204 simulates During the 32 clock periods, the first core software function module example 206A is instructed to execute 32 instructions via command 218A. On the other hand, since the heartbeat signal 106B of the second core 106B at the clocks 0, 2, 4 is true, 32 clocks are simulated at the clocks 0, 2, 4 of the heartbeat signal 106, and the rate control is performed. The device 204 instructs the first core software function module instance 206B to execute 32 instructions during the simulated 32 clocks via command 218B.
Please refer to the tenth figure, which is a functional block diagram of still another embodiment of the dual core processor disclosed in the present invention. The tenth and eleventh figures are similar to the eighth and ninth figures. The core 104 can complete a plurality of instructions in each core clock cycle, and when the core 104 completes a predetermined number of instructions (such as 32), the one-bit heartbeat Signal 106 is true, otherwise instruction execution indication 105 is false (false). However, in the present embodiment, similar to the sixth figure, each instruction execution instruction 105 is a two-bit element for indicating the number of instructions that the core 104 completes in each clock cycle. In this embodiment, once the core 104 completes a predetermined number of instructions, the heartbeat generator 103 generates a true value on the heartbeat signal 106. In an embodiment, the heartbeat generator 103 includes a counter for counting the number of instructions completed in each clock cycle, and the heartbeat signal 106 is the valid bit M of the counter (M = log2N).
Please refer to the eleventh figure, which is an operation example of the rate controller according to the tenth embodiment of the present invention. The diagram of this embodiment is similar to the ninth diagram, and the received heartbeat signal information 122 and the meanings of the diagrams are also the same, and will not be described herein.
Please refer to the twelfth figure, which is a functional block diagram of a further embodiment of the dual core processor disclosed in the present invention. The twelfth and thirteenth figures are similar to the tenth and eleventh views. The core 104 can complete a plurality of instructions in each core clock cycle, and the clock rate of the core 104 is several times the clock rate of the heartbeat signal 106. Each instruction execution indication 105 is a two-bit element that indicates the number of instructions that the core 104 has completed in each clock cycle. However, the embodiment further includes a debug memory array 1212, and the heartbeat generator 103 writes the heartbeat signal information 122 to the debug memory array 1212 according to the instruction execution instruction 105. In one embodiment, the heartbeat generator 103 writes an instruction execution indication 105 received for each clock cycle into the debug memory array 1212. The heartbeat generator 103 then reads the heartbeat signal information 122 from the debug memory array 1212 and writes it to the system memory 112 over the processor bus 114. When the heartbeat signal 122 is written into the system memory 112, the logic analyzer 108 retrieves the heartbeat signal information 122. The heartbeat generator 103 writes the heartbeat signal information 122 to a predetermined address of the system memory 112, so that the logic analyzer 108 can store it to the folder 116, and the heartbeat signal information 122 is written. It will then be used by the rate controller 204 as shown in the third figure. The heartbeat signal information 122 of the present embodiment is similar to the sixth and seventh figures, that is, the heartbeat signal information 122 of each clock is used to indicate the number of instructions that the core 104 has completed at the clock. The heartbeat generator 103 generates a request for a bus interface unit 1216 of the dual core processor 102, and the bus interface unit 1216 connects the dual core processor 102 to the interface of the processor bus 114. . According to an embodiment, the demand generated by the heartbeat generator 103 is the lowest priority requirement, which can be passed to the bus interface unit 1216, and when the processor bus 114 is idle, the bus interface unit 1216 is Attempts to generate a transmission on processor bus 114 to write heartbeat signal information 122 from debug memory array 1212 into system memory 112. It is thus possible to reduce the invasive write of the heartbeat signal information 122 in the processor bus 114 (relative to the non-invasive sideband busbars (relative to the fourth to eleventh and fifteenth to sixteenth figures). The sideband bus) writes the heartbeat signal information 122), thus affecting the possibility of the dual core processor 102 operating sequence, so that the error no longer occurs when the heartbeat feature is activated. The heartbeat generator 103 monitors the entire debug memory array 1212. When the debug memory array 1212 is found to be full, it communicates with the bus interface unit 1216 to increase the priority of the demand to write the heartbeat information 122 as soon as possible. . In an embodiment, the debug memory array 1212 is similar to the memory array of the L2 cache memory 1214 of the dual core processor 102, and is shared by the core 104. The dual core processor 102 can be better designed to design the debug memory array 1212 as an appendix backup of the L2 cache memory 1214, thereby sharing common control logic and circuit layout. In an embodiment, the capacity of the debug memory array 1212 is large enough that the interval between the two checkpoints is relatively small, so the heartbeat generator 103 does not need to write the heartbeat before the checkpoint arrives. Signal Info 122, the benefit is based on the use of a non-intrusive way to write heartbeat information.
Please refer to the thirteenth figure, which is an operation example of the rate controller according to the embodiment of the twelfth embodiment disclosed in the present invention. The diagram of this embodiment is similar to the seventh diagram, and the received heartbeat signal information 122 and the meanings of the diagrams are also the same, and will not be described herein. However, it should be noted that the present embodiment does not have a heartbeat signal 106 as compared to the twelfth figure. Therefore, the heartbeat signal information 122 per clock cycle indicates the number of instructions completed per clock, wherein the clock period shown in the figure is 0- The 5 series corresponds to the core clock cycle.
The relative advantages and disadvantages of the above embodiments will be described in detail below. The advantages of the fourth, fifth and eighth to thirteenth drawings are that only a small number of external pins need to be placed on the multi-core processor package, i.e. one pin per core 104. Therefore, these embodiments will be more scalable in terms of chip size than the sixth and seventh figures, because each of the cores 104 of the sixth and seventh figures requires multiple pins, and if the number of cores 104 is larger, the problem is even more obvious. However, in view of the fact that current microprocessors are superscalar and can execute multiple instructions per clock cycle, the fourth and fifth embodiments limit each core 104 to only per core. A single instruction is completed in the clock cycle. Conversely, an advantage of the sixth to thirteenth embodiment is that the core 104 can be supported to complete multiple instructions per clock cycle. In addition, the embodiments of the fourth to seventh embodiments limit the core cycle to the same cycle rate as the heartbeat signal 106 bus, but in view of the fact that the clock rate of many current microprocessors is high, the implementation cannot be performed with the core. The pulse rate is used to operate an external bus. Conversely, the eighth to thirteenth and fifteenth to sixteenth (described later) have the advantage of supporting an architecture in which the core period frequency is a multiple of the bus frequency of the heartbeat signal 106. As mentioned above, the disadvantages of the embodiments of the twelfth and thirteenth figures are that they are intrusive and may affect the timing of execution of programs of the multi-core processor, so that when the heartbeat is enabled, some errors may be missed. . However, the embodiment of the twelfth and thirteenth figures has the advantage that no additional external pins are required, and this advantage is necessary in some applications.
Please refer to FIG. 14 for a flow chart of a method for operating a simulation environment in the second diagram disclosed in the present invention. The software function module simulation environment 124 is used to determine whether an error has occurred between the first and second checkpoints, and may also be used after the system 100 has been operating for a period of time and generates a plurality of sets of checkpoints to determine storage. Whether there is an error between the plurality of sets of first and second check points in the folder 116 of the first figure. The flow starts in step S1402.
First, in step S1402, the actual result generator 208 uses the processor bus transfer information 118 to generate an actual result memory map 222 and an actual result state 224 that are executed by the dual core processor 102 between the two checkpoints for a predetermined number of instructions. , as shown in the second figure. The flow then proceeds to step S1404.
Next, in step S1404, the simulated initial state generator 202 uses the processor bus transfer information 118 to generate the simulated initial memory map 212 and the simulated initial state 214, as shown in the second figure. The flow then proceeds to step S1406.
In step S1406, the simulated initial memory image 212 is copied to the simulation result memory map 232, and the simulated initial state 214A of the first core is copied to the simulation result state 234A of the first core, and the simulated initial state 214B of the second core is copied to The second core simulation result state 234B. The rate controller 204 and the software function module example 206 then use the copied image to update the simulation result memory map 232 and the simulation result state 234, as shown in the third figure. It should be noted that in the operation of the third figure, in each core instruction execution, it may happen that one core 104 executes a memory write instruction and the other core 104 executes a memory read instruction, such as the above signal. Semaphore write and read. If the number of instructions between such read and write actions is less than the granularity of the heartbeat message information 122, during the actual execution of the dual core processor 102, there may be multiple sequences that may affect the actual memory access. Therefore, if the software function module simulation environment 124 detects this situation, it will assume the possible order of memory access, and then perform step S1406 according to the possible sequence, and record the operation situation. It should be noted that the heartbeat signal information 122 generated by the embodiment of the eighth to eleventh embodiments is greater than the sixth to seventh maps and the twelfth to thirteenth graphs; and the embodiments of the twelfth to thirteenth graphs The interval between heartbeat signal information 122 is greater than that of the fourth to fifth figures. Larger intervals will cause the software function module emulation environment 124 to take more time to complete the operation of Figure 14, because the number of memory access sequences may be many. The flow then proceeds to step S1408.
In step S1408, the comparison unit 226 compares the simulation result generated in step S1406 with the actual result generated in step S1402, and the flow proceeds to step S1412.
In step S1412, it is judged whether or not the comparison result coincides, and if so, step S1414 is performed, otherwise step S1416 is performed.
In step S1414, the comparison unit 226 generates a pass value on the take-off indicator 228, and the flow terminates in step S1414.
In step S1416, the software function module simulation environment 124 determines whether other possible memory access sequences are not executed, and if so, returns to step S1406 and operates using different memory access sequences; otherwise, Then, step S1418 is performed.
In step S1418, the comparison unit 226 generates a fail value on the take-off indicator 228. The flow is terminated in step S1418.
Please refer to the fifteenth figure, which is a functional block diagram of another embodiment of the dual core processor 102 disclosed in the first figure of the present invention. The fifteenth and sixteenth diagrams are similar to the tenth and eleventh diagrams. Each core 104 can complete multiple instructions in each core clock cycle, and the clock rate of the core 104 is the clock rate of the heartbeat signal 106. In times, each instruction execution instruction 105 is a two-bit element that indicates the number of instructions that the core 104 has completed per clock cycle. However, in the embodiment of the fifteenth embodiment, in each bus cycle, the heartbeat generator 103 generates two-bit heartbeat signals 106A, 106B indicating the first core 104A and the second core, respectively. The number of instructions executed by 104B is 0, 8, 16, or 32.
Please refer to the sixteenth figure, which is an operation example table of the rate controller 204 disclosed in the second figure of the present invention, in the fifteenth embodiment. The chart portion of this embodiment is similar to the seventh, ninth, and eleventh figures. As shown, the value of the heartbeat signal 106 received by the rate controller 204 from the heartbeat signal information 122 is from 0 to 3 per core clock. Similarly, in each clock cycle, according to the judgment of step S306 in the third figure, the graph indicates whether the rate controller 204 passes through the corresponding analog clock cycle according to step S308 in the third figure. The command 218A controls the first core software function module example 206A to execute the instruction (if yes, how many instructions are executed), and whether the second core software function module example 206B is used to execute the instruction through the command 218B. (If yes, it will indicate how many instructions are executed). In this illustration, the first core 104A has a heartbeat signal 106A of 0 in clocks 0, 2 in clocks 4, 2 in clocks 3, and 3 in clocks 1, 5. Thus, rate controller 204 instructs first core software function module instance 206A to execute 0 instructions during the simulated clock 0, 2 via command 218A; 8 instructions during the simulated clock 4; during the simulation 16 instructions are executed during pulse 3; and 32 instructions are executed during the simulated clock 1,5. On the other hand, the second core 104B has a heartbeat signal 106B of 0 in clocks 3, 5, 1 in clocks 0, 4, and 2 in clocks 1, 2, and no heartbeat signal in any of the clocks. 3. Therefore, the rate controller 204 controls the second core software function module example 206B via the command 218B to execute 0 instructions during the simulated clocks 3, 5; during the simulated clocks 0, 4, 8 instructions are executed; During the simulated clock 1, 2 instructions are executed; there is no clock to execute 32 instructions.
An advantage of the fifteenth and sixteenth embodiments is that under the operation of the fourteenth embodiment, the interval that can be provided is better than that of the eighth to eleventh embodiment. In addition, the heartbeat signal 106 in the embodiment of the present invention can also be used in the example with finer spacing, and the error mode in this case does not need to cause each core 104 to regenerate an error. For example, assume that there are eight heartbeat signals 106 on the sideband bus, and the multicore processor includes four cores 104, but only two cores 104 must be operated to regenerate the error. In this case, the heartbeat generator 103 is programmed to use only four of the eight heartbeat signals 106 bits to indicate the number of instructions completed by each core 104 (0, 2, 4, 6, 8, 10, 12, respectively). , 14, 16, 18, 20, 22, 24, 26, 28, or 32).
Although in the above embodiment, each core 104 executes a single thread, it can also be designed to execute multiple threads at the same time, and the heartbeat information indicates the instructions completed by the thread.
Moreover, although in the above embodiment, the two cores 104 have the same core clock cycle, but may have different core clock cycles, the heartbeat signal information 122 indicates the two core rates, and the rate controller 204 is generating the command 218. It can be taken into consideration.

Another embodiment is to use a Verilog simulator to emulate an actual processor that enables a debugger to access any communication link (net) of the processor at any time, including to indicate execution instructions and access per core. The number of times the memory is signaled. These signals enable the debugger to provide information to the software function module, so that the actual processor (or at least the Verilog analog of the stone processor) can execute instructions and access memory simultaneously. However, this has three drawbacks: First, depending on the number of clock cycles/instructions in the simulation, the Verilog simulator consumes a very large amount of system resources and time, making Verilog simulations less likely to be implemented. The way, and can't solve some types of errors. Second, the operational behavior of the Verilog simulator must be different from the actual processor behavior. Third, the Verilog simulator's solution requires the processor to be designed to have the ideal per-state-per-clock replay capability, which is difficult to achieve. In general, a microprocessor with an ideal per-cycle one-state reproduction function can be loaded with an input state that defines the state of the entire processor, meaning that there is no state of any processor. Initialization cannot be obtained by loading the input state. However, the embodiment of the present invention does not have the disadvantages of the above-described Verilog simulator.

While the present invention has been described in terms of various embodiments, the embodiments disclosed herein may be modified as required by those skilled in the art. In the scope of subsequent patents. For example, the software can be implemented as a function, architecture, module, simulation, and/or various devices and methods described above. The software of the present invention is implemented by using a general programming language (such as C, C++), hardware description languages (HDL), including a Verilog hardware description language, etc., or other available programs. Such software can be stored in any computer-usable storage medium, such as magnetic tape, semiconductor, magnetic disk, or optical disc (such as CD-ROM, DVD-ROM, etc.), network, Wired/wireless or other communication media. The device and method embodiments of the present invention may be included in a semiconductor intellectual property core, such as a processor core (for example, embedded in a hardware description language), and may be converted into a hardware form to Produced on integrated circuits. In addition, the device and method of the present invention may also be a combination of a hardware and a soft body, and are not limited to those disclosed.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the claims of the present invention; any other equivalent changes or modifications made without departing from the spirit of the invention, such as the application of the present invention The processor device of a general-purpose computer, etc., should be included in the scope of the following patent application.

100‧‧‧Computer system
102‧‧‧Dual core processor
103‧‧‧Heartbeat Generator
104A‧‧‧First Core
104B‧‧‧Second core
105, 105A, 105B‧‧‧ instruction execution instructions
106, 106A, 106B‧‧ ‧ heartbeat signal
108‧‧‧Logical Analyzer
112‧‧‧ memory
114‧‧‧Processor bus
116‧‧‧ Folders
118‧‧‧Processor Bus Transfer Information
122‧‧‧ heartbeat information
124‧‧‧Software function module simulation environment
202‧‧‧Simulated initial state generator
204‧‧‧ rate controller
206A‧‧‧First core software function module example
206B‧‧‧Example of the second core software function module
208‧‧‧ Actual result generator
226‧‧‧Comparative unit
212‧‧‧ Simulated initial memory image
214A‧‧‧First core simulation initial state
214B‧‧‧Second core simulation initial state
222‧‧‧ Actual result memory image
224A‧‧‧The actual result status of the first core
224B‧‧‧The actual result status of the second core
232‧‧‧simulation result memory image
234A‧‧‧First core simulation result status
234B‧‧‧Second core simulation result status
218A, 218B‧‧‧ Order
228‧‧‧No indicator
1212‧‧‧Debug Memory Array
1214‧‧‧L2 cache memory
1216‧‧‧ bus interface unit
S302-S312‧‧‧Steps
S1402-S1418‧‧‧Steps

The first figure is a functional block diagram of a computer system having a dual core processor disclosed herein.
The second figure is a functional block diagram of the software functional module simulation environment disclosed by the present invention.
The third figure is a flow chart of the method for operating the simulation environment of the second figure disclosed in the present invention.
The fourth figure is a functional block diagram of one embodiment of a dual core processor disclosed in the present invention.
The fifth figure is an operation example of the rate controller according to the fourth embodiment of the present invention.
Figure 6 is a functional block diagram of another embodiment of a dual core processor disclosed herein.
The seventh figure is an operation example of the rate controller according to the sixth embodiment of the present invention.
The eighth figure is a functional block diagram of still another embodiment of the dual core processor disclosed in the present invention.
The ninth figure is an operation example of the rate controller according to the eighth embodiment of the present invention.
The tenth figure is a functional block diagram of still another embodiment of the dual core processor disclosed in the present invention.
The eleventh figure is an operation example table of the rate controller according to the tenth embodiment of the present invention.
The twelfth figure is a functional block diagram of a further embodiment of the dual core processor disclosed in the present invention.
Figure 13 is a diagram showing the operation of the rate controller according to the embodiment of the twelfth embodiment disclosed in the present invention.
Figure 14 is a flow chart showing the method of operating the simulation environment of the second diagram disclosed in the present invention.
The fifteenth figure is a functional block diagram of a further embodiment of the dual core processor disclosed in the present invention.
Figure 16 is a diagram showing the operation of the rate controller according to the fifteenth embodiment of the present invention.

S1402-S1418‧‧‧Steps

Claims (26)

A microprocessor debugging method, the microprocessor has a plurality of cores, including:
Causing the microprocessor to perform an actual execution of the instruction;
Obtaining a heartbeat information from the microprocessor indicating an actual execution sequence in which the cores execute instructions with each other;
The plurality of related examples of the command-software function module execute the instructions according to the actual execution order to generate a simulation result of the execution instructions; and compare the simulation results with an actual result of the execution instructions to determine whether the two are in conformity.

The method of claim 1, wherein the actual result and the simulation result include a state in which the cores are executed.

The method of claim 2, wherein the actual result and the simulation result further comprise a memory state after execution.

For example, the method described in claim 1 further includes:
If the simulation result does not match the actual result, an error is indicated.

The method of claim 1, wherein the number of instructions executed between a memory write command and a memory read command on the same memory address is less than a granularity of the heartbeat information. a plurality of possible execution sequences that may affect the memory access, wherein the step of instructing the plurality of related examples of the software function module to execute the instruction is to command the software function module according to the possible execution orders Some related examples execute instructions until the simulation results match the actual results.

For example, the method described in claim 5 of the patent scope further includes:
If all of the simulation results of the execution sequences do not match the actual results, an error is indicated.

The method of claim 1, wherein the heartbeat information comprises a plurality of records, which are a plurality of heartbeats during the actual execution of the instructions, wherein each of the records indicates the number of instructions actually executed by the cores, The steps of executing the instruction of the plurality of related examples of the software function module include:
For each of these records, each of the relevant examples of the software function module is commanded to actually execute the number of instructions recorded in the records.

The method of claim 1, wherein the step of obtaining the heartbeat information from the microprocessor comprises extracting a heartbeat signal generated by the microprocessor during an actual execution of an instruction on an external bus.

A microprocessor comprising:
a plurality of cores, each of the core outputs an instruction execution indicator for indicating the number of instructions executed by the core in each clock cycle; and a heartbeat generator Each of the cores receives the instruction execution instruction and generates a heartbeat indicator for each of the cores on an external bus, wherein the heartbeat indication indicates that each of the cores is in the external bus The number of instructions executed in each clock.

The microprocessor of claim 9, wherein the core clock cycle rate is the same as the clock cycle rate of the external bus.

The microprocessor of claim 9, wherein the core clock cycle rate is greater than a clock cycle rate of the external bus, wherein each of the heartbeat indications indicates an instruction execution number ratio The maximum number of achievable instructions indicated by the instruction execution indication is still large.

The microprocessor of claim 11, wherein a ratio of a clock cycle rate of the cores to a clock cycle rate of the external bus is J, each of the instructions executing the instructions indicating the completion of the instructions The maximum number is K, and each of the heartbeat indications indicates that the number of instructions executed is L, where L is greater than or equal to the product of J and K.

The microprocessor of claim 11, wherein each of the heartbeat indications comprises a single bit.

The microprocessor of claim 9, wherein each of the cores includes a counter for counting the number of instructions executed in each clock cycle, wherein the instruction execution indication is the counter value of the counter. An output bit.

The microprocessor of claim 14, wherein the output bit of the count value of the counter is a bit M, and M = log2N, where N is the clock of the core and the time of the external bus The ratio of the pulse and the product of the maximum number of instructions that the core can complete per clock cycle.

The microprocessor of claim 9, wherein the heartbeat generator includes a counter associated with each of the cores for counting the number of instructions executed in each clock cycle, wherein the instruction execution indication Is an output bit of the counter value of the counter.

The microprocessor of claim 16, wherein the output bit of the count value of the counter is a bit M, and M = log2N, where N is the clock of the core and the time of the external bus The ratio of the pulse and the product of the maximum number of instructions that the core can complete per clock cycle.

The microprocessor of claim 17, wherein each of the instruction execution instructions is a one-bit element, and each of the heartbeat indications comprises a single bit.

The microprocessor of claim 9, wherein the external bus bar comprises a sideband bus coupled to the microprocessor, the sideband busbar being different from the coupling The main processor bus of the microprocessor.

The microprocessor of claim 19, wherein at least a portion of the sideband busbars are a JTAG bus.

The microprocessor of claim 19, wherein the sideband bus is a service processor bus coupled to a service processor internal to the microprocessor.

A microprocessor comprising:
a plurality of cores, each core generating an instruction execution indicator for indicating the number of instructions executed by each core during each clock;
a memory array stored in a clock period, an instruction execution instruction generated by the cores; and a bus interface unit coupled to the microprocessor An external bus, wherein the bus interface unit is configured to write the instruction execution instruction stored in the storage array to an external memory of the microprocessor.

The microprocessor of claim 22, wherein the bus interface unit writes the instruction execution instruction to the external memory in accordance with a lowest priority of other transmissions on the external bus. in.

The microprocessor described in claim 19, further comprising:
a heartbeat generator coupled to the storage array and the bus interface unit for receiving the instruction execution indication from each of the cores, wherein the heartbeat generator writes the instruction execution during the segment clock period Instructing to the storage array and reading the instruction execution indication from the storage array to cause the bus interface unit to write to the external memory.

The microprocessor of claim 24, wherein the heartbeat generator waits to read the instruction execution indication from the storage array, and after the segment clock period ends, the bus interface unit will The instruction execution instruction is written to the external memory.

The microprocessor of claim 24, wherein the heartbeat generator periodically reads the instruction execution indication from the storage array to cause the bus interface unit to write to the external memory.