CN102252827A - Automatic focimeter control device and automatic focimeter system - Google Patents
Automatic focimeter control device and automatic focimeter system Download PDFInfo
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- CN102252827A CN102252827A CN2011100968983A CN201110096898A CN102252827A CN 102252827 A CN102252827 A CN 102252827A CN 2011100968983 A CN2011100968983 A CN 2011100968983A CN 201110096898 A CN201110096898 A CN 201110096898A CN 102252827 A CN102252827 A CN 102252827A
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Abstract
The embodiment discloses an automatic focimeter control device and an automatic focimeter system. An FPGA (Field programmable gate array) used as a carrier is embedded in an SOPC (system on programmable chip); a soft-core NIOSII (national institute of open schooling II) is integrated in the SOPC and used for processing the image information collected by a CMOS (complementary metal oxide semiconductor) camera; the device has the functions of binarization, low-pass filtering, edge detection and the like for the image; and the device can be used for measuring the spherical diopter, cylinder diopter, cylinder lens shaft position angle and the like of the glasses lens fast and accurately; an MCU (micro control unit) is used as a coprocessor, thus the cost of the control device can be saved; the embedded SOPC can solve the SOC (system on chip) scheme, the design cycle is short, and the cost is low; and by combining the embedded soft-core NIOSII technology, the technical effects of fast processing the image data and saving the cost can be realized.
Description
Technical field
The present invention relates to optometry and join the mirror technical field, more particularly, relate to a kind of automatic lensometer opertaing device and a kind of automatic focal power meter systems.
Background technology
Automatic lensometer is to be used for the small-sized semi-intelligent surveying instrument that mirror is joined in optometry, and it is used widely in spectacles industry as a kind of senior surveying instrument.
The control core requirement volume of described automatic lensometer is little and processing speed is fast, to adapt to the user demand of light and fast, the control core that existing automatic lensometer uses small-sized MCU and DSP to form mostly, though it is cheap, but data processing speed is undesirable and measuring accuracy is low, and system is can degree of expansion little; Though and satisfied data processing requirement fast with the embedded system of ARM, with high costs.
Summary of the invention
In view of this, the invention provides a kind of automatic lensometer opertaing device and a kind of automatic focal power meter systems, based on the FPGA/SOPC/NIOSII control system, to realize data processing purpose quick and with low cost.
A kind of automatic lensometer opertaing device comprises: programmable device FPGA, the micro-control unit MCU as coprocessor, flash memory FLASH and complementary metal oxide semiconductor (CMOS) cmos image sensor are wherein on the sheet:
Described FPGA embeds programmable system on chip SOPC, and in described SOPC the soft nuclear of integrated little processing NIOSII, described FPGA is connected with described MCU;
Described FPGA is connected with described FLASH with address wire and data line respectively;
Described cmos image sensor is connected with described FPGA.
Opertaing device in this embodiment embeds SOPC in FPGA, and integrated therein NIOSII, because described FPGA can carry out parallel processing and high-speed image data processing, threshold segmentation, binaryzation and the functions such as airspace filter and rim detection of image have been realized, the SOPC that embeds can solve the SOC scheme, design cycle is short and cost is low and the technology of the soft nuclear of NIOSII that combination embeds, and has reached fast processing view data and cost-effective technique effect.
Preferably, described FPGA is connected the realization serial communication by described Serial Peripheral Interface SPI with described MCU.
Realize serial communication with SPI between MCU in this by way of example and the described FPGA, the processing speed height makes the instruction interaction rapid and convenient between master, the coprocessor.
Preferably, described FPGA is connected with described FLASH with address wire and data line respectively and is specially: FPGA is connected with described FLASH with 8 data lines with 23 address wires respectively.
Described 23 address wires and 8 data line conducts are preferably selected for use in this embodiment, and are not limited to this kind form.
Preferably, described equipment also comprises: complex programmable logic device (CPLD), described CPLD loads configuration and receives the interrupt manipulation instruction that described MCU sends described FPGA, is connected with described FLASH with 8 data lines with 23 address wires respectively.
Described CPLD is connected between described MCU and the described FLASH, and the second passage to the FLASH read-write is provided, and makes the effect of lower-cost MCU performance coprocessor, and the divergence of system improves.
Preferably, described cmos image sensor is connected with described FPGA and is specially: described cmos image sensor is connected with described FPGA by LVDS.
Be connected with LVDS high-speed-differential transmission line between described FPGA and the cmos image sensor, guaranteed the real-time high-quality transmission of view data.
Preferably, described equipment also comprises: Thin Film Transistor-LCD TFT-LCD is connected by LVDS with described FPGA.
The TFT-LCD conduct is preferably selected for use in this embodiment, and is not limited to the above-mentioned form of enumerating.
A kind of automatic focal power meter systems, comprise: automatic focal power is taken into account the automatic lensometer opertaing device of the described automatic lensometer work of control, and described opertaing device comprises: programmable device FPGA, the micro-control unit MCU as coprocessor, flash memory FLASH and complementary metal oxide semiconductor (CMOS) cmos image sensor are wherein on the sheet:
Described FPGA embeds programmable system on chip SOPC, and in described SOPC the soft nuclear of integrated little processing NIOSII, described FPGA is connected with described MCU;
Described FPGA is connected with described FLASH with address wire and data line respectively;
Described cmos image sensor is connected with described FPGA.
Preferably, described NIOSII is specially the NIOSII/f type.
Preferably, described equipment also comprises: complex programmable logic device (CPLD), described CPLD loads configuration and receives the interrupt manipulation instruction that described MCU sends described FPGA, is connected with described FLASH with 8 data lines with 23 address wires respectively.
Preferably, the pixel of described cmos image sensor is 1,300,000.
Native system is corresponding with the said equipment, include opertaing device and automatic lensometer in the system, described opertaing device embeds FPGA by the SOPC technology, and in the SOPC system integrated NIOSII, realized handling technique effect quick and that cost reduces, described NIOSII/f belongs to quick type processor, has further improved processing power.And, be the second channel of FLASH read-write as preferably complex programmable logic device (CPLD) being connected between described MCU and the described FLASH.
From above-mentioned technical scheme as can be seen, the embodiment of the invention is that carrier is that carrier has embedded the SOPC system with FPGA with the fpga core processor, and in described SOPC system integrated soft nuclear NIOSII, possesses binaryzation at image, function such as low-pass filtering and rim detection, and to the diopter of correction of eyeglass, post mirror degree, the measurement quick and precisely of post mirror axle parallactic angle etc., and with MCU as coprocessor, saved the cost of this opertaing device, the SOPC that embeds can solve the SOC scheme, design cycle is short and cost is low and the technology of the soft nuclear of NIOSII that combination embeds, and has reached fast processing view data and cost-effective technique effect.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 a is the disclosed a kind of automatic lensometer opertaing device structural representation of the embodiment of the invention;
Fig. 1 b is the method flow diagram of the disclosed a kind of automatic lensometer opertaing device correspondence of the embodiment of the invention;
Fig. 2 is the disclosed a kind of automatic lensometer opertaing device structural representation of the embodiment of the invention;
Fig. 3 is the disclosed a kind of automatic lensometer system architecture synoptic diagram of the embodiment of the invention.
Embodiment
For quote and know for the purpose of, hereinafter the technical term of Shi Yonging, write a Chinese character in simplified form or abridge and be summarized as follows:
FPGA:Field-Programmable Gate Array, field programmable gate array;
SPI:Serial Peripheral Interface, Serial Peripheral Interface;
MCU:Micro Control Unit, micro-control unit;
CPLD:Complex Programmable Logic Device, CPLD;
LVDS: a digital signal interface, can carry out video output, generally in industrial circle or the inner use of industry.
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
The embodiment of the invention discloses a kind of automatic lensometer opertaing device and a kind of automatic focal power meter systems, based on the FPGA/SOPC/NIOSII control system, to realize data processing purpose quick and with low cost.
Fig. 1 a shows a kind of automatic lensometer opertaing device, comprising:
Described FPGA11 embedding programmable system on chip SOPC and embedding decline and handle soft nuclear NIOSII, and are connected with described MCU12;
Described FPGA11 is connected with described FLASH13 with address wire and data line respectively;
Described cmos image sensor 14 is connected with described FPGA11.
Described FPGA can carry out parallel processing and matrix operation, it receives the image information of cmos image sensor, realization is at the functions such as threshold segmentation, binaryzation, airspace filter and rim detection of image, in order to improve its floating-point processing power, use the floating-point custom instruction IP kernel of Altera, the outer NOR FLASH of its intrinsic memory device and 4M or 8M sheet is as storer, described FPGA11 is connected with 23 address wires and 8 data lines respectively with described FLASH, can realize the read-write storage of described FPGA to the FLASH storer easily.
Described NIOSII is that the embedding of Altera declines and handles soft nuclear, it is a kind of RISC32 position embedded microprocessor that adopts single instruction stream, most instructions can be finished in a clock period, easy to use flexible, as preferably, the NIOSII processor that present embodiment uses has further been accelerated image processing speed as the quick type processor of NIOSII/f type.
Described SOPC is a programmable system on chip, and it is based on the reconfigurable SOC of programmable logic device (PLD), and integrated stone or soft nucleus CPU, and this system can solve the SOC scheme flexible and efficiently, and the design cycle, short design cost was low.
More specifically, utilize described SOPC technology that view data is handled, shown in Fig. 1 b:
Step 11: carry out statistics with histogram to stating the original image that CMOS gathers, determine the separatrix of main warp and background in the image, i.e. partition threshold;
Step 12: the original image that described CMOS is gathered utilizes the low-pass filtering operator in the airspace filter algorithm, and image information is carried out Filtering Processing, makes image become level and smooth to remove high frequency noise as far as possible; Filtered image is divided into two-way to be handled, and is respectively step 121 and step 122;
Step 121:, be partitioned into the zone at each hot spot place by the projection figure of hot spot on the X-Y direction;
Step 122: utilize the partition threshold that obtains in the abovementioned steps 12 that image is carried out binary conversion treatment, then bianry image is carried out Laplce's rim detection, obtain single pixel edge image of each hot spot;
Step 13: utilize the result of above-mentioned steps 121 and step 122 liang paths, extract the center that each has determined the hot spot in zone, finally form the spot center coordinates matrix;
Step 14: utilize described spot center coordinates matrix can calculate optical parametrics such as the diopter of correction of eyeglass, post mirror degree, prism degree and post mirror axle position direction.
Make full use of the parallel processing characteristics of FPGA, avoided the defective of its floating-point processing power difference, make the time of entire image processing flow process significantly reduce, system's operation is smooth more.
Described MCU is a coprocessor, and communication interfaces such as SPI, I2C, USB and UART are provided for system, and when start to TFT-LCD, and CMOS carries out initialization.
Preferably:
Described FPGA is connected the realization serial communication by described Serial Peripheral Interface SPI with described MCU, realize serial communication with SPI between MCU among this embodiment and the described FPGA, and the processing speed height makes the instruction interaction rapid and convenient between master, the coprocessor;
Be connected with LVDS high-speed-differential transmission line between described FPGA and the cmos image sensor, guaranteed the real-time high-quality transmission of view data.
Among this embodiment, opertaing device is integrated NIOSII in FPGA, because described FPGA can carry out parallel processing and high-speed image data processing, threshold segmentation, binaryzation and the functions such as airspace filter and rim detection of image have been realized, the SOPC that embeds can solve the SOC scheme, design cycle is short and cost is low and the technology of the soft nuclear of NIOSII that combination embeds, and has reached fast processing view data and cost-effective technique effect.
Fig. 2 shows another automatic lensometer opertaing device, something in common repeats no more referring to Fig. 1 diagram and explanation thereof, now be described with regard to different parts, based on Fig. 1, Fig. 2 also comprises: complex programmable logic device (CPLD) 21, described CPLD loads configuration and receives the interrupt manipulation instruction that described MCU sends described FPGA, is connected with described FLASH with 8 data lines with 23 address wires respectively.
Public 23 address wires of described FPGA and described CPLD and 8 data lines can not only can be transferred to FPGA among the SDRAM the data among the FLASH when working, also can carry out data transmission by USB, the interruption association that receives described MCU handles, and fast FLASH is carried out read-write operation; Described CPLD is connected between described MCU and the described FLASH, and the second passage to the FLASH read-write is provided, and lower-cost MCU performance coprocessor high-performance is worth, and the divergence of system improves;
And Thin Film Transistor-LCD TFT-LCD22 is connected by LVDS with described FPGA.
The use of described LVDS makes in the lensmeter use and can show in real time that operation interface is more humane, and the TFT-LCD conduct is preferably selected for use in this embodiment, and is not limited to the above-mentioned form of enumerating.
Fig. 3 shows a kind of automatic focal power meter systems, comprising:
Described FPGA321 embeds programmable system on chip SOPC, and in described SOPC the soft nuclear of integrated little processing NIOSII, described FPGA321 is connected with described MCU322;
Described FPGA321 is connected with described FLASH323 with address wire and data line respectively;
Described cmos image sensor 324 is connected with described FPGA321;
Complex programmable logic device (CPLD) 325, described CPLD loads configuration and receives the interrupt manipulation instruction that described MCU sends described FPGA, is connected with described FLASH with 8 data lines with 23 address wires respectively.
Thin Film Transistor-LCD TFT-LCD326 is connected by LVDS with described FPGA.
Need to prove that described FPGA is connected with described FLASH with address wire and data line respectively and is specially: FPGA is connected with described FLASH with 8 data lines with 23 address wires respectively; Described NIOSII is specially the NIOSII/f type; The pixel of described cmos image sensor is 1,300,000.
Native system is corresponding with the said equipment, detailed description for equipment components illustrates and explanation referring to Fig. 1, repeat no more, include opertaing device and automatic lensometer in the described system, described opertaing device embeds SOPC and integrated NIOSII, realized handling technique effect quick and that cost reduces, described NIOSII/f belongs to quick type processor, has further improved processing power.And, be the second channel of FLASH read-write as preferably complex programmable logic device (CPLD) being connected between described MCU and the described FLASH.
In sum:
The embodiment of the invention is that carrier is that carrier has embedded the SOPC system with FPGA with the fpga core processor, and in described SOPC system integrated soft nuclear NIOS II, possesses binaryzation at image, function such as low-pass filtering and rim detection, and to the diopter of correction of eyeglass, post mirror degree, the measurement quick and precisely of post mirror axle parallactic angle etc., and with MCU as coprocessor, saved the cost of this opertaing device, the SOPC that embeds can solve the SOC scheme, design cycle is short and cost is low and the technology of the soft nuclear of NIOSII that combination embeds, and has reached fast processing view data and cost-effective technique effect;
In addition, in the embodiments of the invention, described CPLD is connected between described MCU and the described FLASH, second passage to the FLASH read-write is provided, lower-cost MCU performance coprocessor high-performance is worth, and the divergence of system improves, and has guaranteed the convenience of subsequent software upgrading;
Each embodiment adopts the mode of going forward one by one to describe in this instructions, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.The professional can also further recognize, the unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein, can realize with electronic hardware, computer software or the combination of the two, for the interchangeability of hardware and software clearly is described, the composition and the step of each example described prevailingly according to function in the above description.These functions still are that software mode is carried out with hardware actually, depend on the application-specific and the design constraint of technical scheme.The professional and technical personnel can use distinct methods to realize described function to each specific should being used for, but this realization should not thought and exceeds scope of the present invention.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can directly use the software module of hardware, processor execution, and perhaps the combination of the two is implemented.Software module can place the storage medium of any other form known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined herein General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (10)
1. an automatic lensometer opertaing device is characterized in that, comprising: programmable device FPGA, the micro-control unit MCU as coprocessor, flash memory FLASH and complementary metal oxide semiconductor (CMOS) cmos image sensor are wherein on the sheet:
Described FPGA embeds programmable system on chip SOPC, and in described SOPC the soft nuclear of integrated little processing NIOSII, described FPGA is connected with described MCU;
Described FPGA is connected with described FLASH with address wire and data line respectively;
Described cmos image sensor is connected with described FPGA.
2. equipment according to claim 1 is characterized in that, described FPGA is connected the realization serial communication by described Serial Peripheral Interface SPI with described MCU.
3. equipment according to claim 1 is characterized in that, described FPGA is connected with described FLASH with address wire and data line respectively and is specially: FPGA is connected with described FLASH with 8 data lines with 23 address wires respectively.
4. equipment according to claim 1, it is characterized in that, also comprise: complex programmable logic device (CPLD), described CPLD loads configuration and receives the interrupt manipulation instruction that described MCU sends described FPGA, is connected with described FLASH with 8 data lines with 23 address wires respectively.
5. equipment according to claim 1 is characterized in that, described cmos image sensor is connected with described FPGA and is specially: described cmos image sensor is connected with described FPGA by LVDS.
6. equipment according to claim 1 is characterized in that, also comprises: Thin Film Transistor-LCD TFT-LCD is connected by LVDS with described FPGA.
7. automatic focal power meter systems, it is characterized in that, comprise: automatic focal power is taken into account the automatic lensometer opertaing device of the described automatic lensometer work of control, and described opertaing device comprises: programmable device FPGA, the micro-control unit MCU as coprocessor, flash memory FLASH and complementary metal oxide semiconductor (CMOS) cmos image sensor are wherein on the sheet:
Described FPGA embeds programmable system on chip SOPC, and in described SOPC the soft nuclear of integrated little processing NIOSII, described FPGA is connected with described MCU;
Described FPGA is connected with described FLASH with address wire and data line respectively;
Described cmos image sensor is connected with described FPGA.
8. system according to claim 7 is characterized in that described NIOSII is specially the NIOSII/f type.
9. system according to claim 7, it is characterized in that, described opertaing device also comprises: complex programmable logic device (CPLD), described CPLD loads configuration and receives the interrupt manipulation instruction that described MCU sends described FPGA, is connected with described FLASH with 8 data lines with 23 address wires respectively.
10. system according to claim 7 is characterized in that, the pixel of described cmos image sensor is 1,300,000.
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| CN102789728A (en) * | 2012-07-02 | 2012-11-21 | 江苏大学 | Computer composition principle testing platform |
| CN102928889A (en) * | 2012-11-08 | 2013-02-13 | 中国矿业大学 | Integrative radio wave perspective exploration instrument |
| CN103414854A (en) * | 2013-08-13 | 2013-11-27 | 三星半导体(中国)研究开发有限公司 | System-on-chip with image processing function and operation method thereof |
| CN107390394A (en) * | 2017-08-07 | 2017-11-24 | 武汉精测电子技术股份有限公司 | A kind of liquid crystal module test system based on SOPC |
| CN110008172A (en) * | 2019-04-02 | 2019-07-12 | 广东高云半导体科技股份有限公司 | A kind of system on chip |
| CN113489913A (en) * | 2021-09-06 | 2021-10-08 | 杭州惠航科技有限公司 | Snapshot identification method, device and system and computer storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102789728A (en) * | 2012-07-02 | 2012-11-21 | 江苏大学 | Computer composition principle testing platform |
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| CN107390394A (en) * | 2017-08-07 | 2017-11-24 | 武汉精测电子技术股份有限公司 | A kind of liquid crystal module test system based on SOPC |
| CN107390394B (en) * | 2017-08-07 | 2020-04-28 | 武汉精测电子集团股份有限公司 | Liquid crystal module testing system based on SOPC |
| CN110008172A (en) * | 2019-04-02 | 2019-07-12 | 广东高云半导体科技股份有限公司 | A kind of system on chip |
| CN113489913A (en) * | 2021-09-06 | 2021-10-08 | 杭州惠航科技有限公司 | Snapshot identification method, device and system and computer storage medium |
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Application publication date: 20111123 |