CN117009270A - Bus switching circuit and control method - Google Patents

Bus switching circuit and control method Download PDF

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Publication number
CN117009270A
CN117009270A CN202310393916.7A CN202310393916A CN117009270A CN 117009270 A CN117009270 A CN 117009270A CN 202310393916 A CN202310393916 A CN 202310393916A CN 117009270 A CN117009270 A CN 117009270A
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CN
China
Prior art keywords
bus
pxi
pxie
pci
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310393916.7A
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Chinese (zh)
Inventor
王小龙
刘晓坤
罗雅
张明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunxin Guoyi Technology Jiangsu Co ltd
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Kunxin Guoyi Technology Jiangsu Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunxin Guoyi Technology Jiangsu Co ltd filed Critical Kunxin Guoyi Technology Jiangsu Co ltd
Priority to CN202310393916.7A priority Critical patent/CN117009270A/en
Publication of CN117009270A publication Critical patent/CN117009270A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)

Abstract

The present application relates to the field of computer technologies, and in particular, to a bus switching circuit and a control method. The PCI/PCIe bus on the computer motherboard is converted into an instrument-specific PXI/PXIe bus by using a standard computer motherboard to replace an original independent main controller, the digital logic unit U1 is connected with the PCI/PCIe bus slot of the motherboard through the golden finger F1, and the digital logic unit U1 converts PCI/PCIe signals into PXI/PXIe signals and sends the PXI/PXIe signals to the connector L1. The whole cost is reduced, the whole volume and weight are reduced, and the power consumption of the whole machine is reduced.

Description

Bus switching circuit and control method
Technical Field
The present application relates to the field of computer technologies, and in particular, to a bus switching circuit and a control method.
Background
The PXI/PXIe bus is a bus specifically designed for test and measurement instrument applications. A standard complete PXI/PXIe system is generally composed of a PXI/PXIe controller module, a PXI/PXIe slot backboard and an expansion module. Compared with a common PCI/PCIe bus, the PXI/PXIe bus improves the physical structure and the electrical signals of the PCI/PCIe bus aiming at test measurement application, so that the PCI/PCIe bus is more suitable for being used in the test measurement application, and particularly improves the physical interface between an expansion module (comprising a controller module) and a PXI/PXIe back plate, so that the PCI/PCIe bus is easier to plug and replace, is convenient for quick replacement of the module in industrial test, and improves the overall test efficiency.
A standard PXI/PXIe bus structure coordination diagram is shown in FIG. 1, wherein a PXI/PXIe controller module and an expansion module are parallel to each other and are in a vertical relation with a PXI/PXIe backboard; the PXI/PXIe controller module is connected with the zero number slot (i.e. the controller slot) of the backboard through a special connector; the PXI/PXIe expansion module can be connected with the No. 1-7 expansion slot position (which can be inserted in any expansion slot position and can have a plurality of expansion slot positions with the same or similar functions according to the expansion capability of the back plate) through a special connector. The PXI/PXIe controller module and the PXI/PXIe extension module communicate through a PXI/PXIe bus on the back plate. The three components are combined together to form a complete PXI/PXIe bus instrument system.
Standard PXI/PXIe controller modules are self-contained modular designs that require design and production according to specialized standards and are therefore very costly
And the whole machine of standard PXI/PXIe structural design consumes more power, needs independent power, generally increases whole machine and volume and weight and integrates the built-in power or external power module in the trade.
The bus is a common communication trunk line for transmitting information among various functional components of the computer, and is an internal structure, and is a common channel for transmitting information by CPU, memory, input and output devices. The transfer of signals is first accomplished from PCI/PCIe bus to PXI/PXIe bus.
Accordingly, a bus transfer circuit and a control method are needed by those skilled in the art to solve the above-mentioned problems in the background art and implement the PCI/PCIe bus to PXI/PXIe bus transfer.
Disclosure of Invention
In order to solve the technical problems, the application provides: a bus switching circuit and a control method.
The application provides a hardware circuit for bus switching, which comprises a power supply control unit PU1, a power supply control unit PU2, a digital logic unit U1, a clock control unit U2, a programmable memory U3, a golden finger F1 and a connector L1.
The pin VIN of the power control unit PU1 is connected with the PV5A pin of the PCI/PCIe bus slot on the main board to obtain a 5V power supply, and the power control unit U1 can provide a stable 5V power supply after rectification.
The pin VIN of the power control unit PU2 is connected with the PV3V3A pin of the PCI/PCIe bus slot on the main board to obtain a 3.3V power supply, and the power control unit U1 can provide a stable 3.3V power supply after rectification.
Pin 4 and pin 4 of the clock control unit U2 are connected with PU1 to obtain a 5V power supply. Clock control unit U2 ensures time synchronization of PCI/PCIe bus to PXI/PXIe bus transitions.
The digital logic unit U1 is a core component for realizing the transfer from PCI/PCIe bus to PXI/PXIe bus, the digital logic unit U1 is connected with a PCI/PCIe bus slot of a main board through a golden finger, the digital logic unit U1 converts PCI/PCIe signals into PXI/PXIe signals and then sends the PXI/PXIe signals to the connector L1, and the programmable memory U3 stores relevant information such as addresses and the like. The digital logic unit U1 loads the relevant information such as the memory address from the programmable memory U3.
The programmable memory U3 is used for storing data of the digital logic unit U1 and the clock control unit U2 and assisting the system to complete bus transfer.
The connector L1 is usually designed as a male connector and can be externally connected with an expansion card, so that conversion and control of 2-8 paths of unequal PXI buses are realized.
The technical principle of the application is mainly as follows: the standard computer main board is used for replacing the original independent main controller, the PCI/PCIe bus on the computer main board is skillfully converted into the instrument-specific PXI/PXIe bus, and the PXI/PXIe bus slot positions are expanded on the main board with the PCI/PCIe slot positions.
The computer main board is a control core of the whole system and is used for replacing an independent controller module in a standard PXI/PXIe bus, the computer main board is provided with a PCI/PCIe bus slot, and the golden finger F1 can be inserted into the PCI/PCIe bus slot of the main board. The digital logic unit U1 is used for leading out PCI/PCIe signals from a computer main board, and is used for carrying out processing such as filtering, signal amplification and the like so as to transmit effective communication signals, thereby finally realizing the signal communication from the PXI/PXIe expansion module to the main board.
The buses have a shared nature. If the bus is idle at a given time, some devices on the bus must drive some signals to steady state. These signals are address/data lines, command/byte enable functions, and valid parity. If no device requests use of the bus. The digital logic unit U1 allocates ownership of the bus so that the bus signal never floats in the idle state.
The digital logic unit U1 defaults to 6 bus clock outputs and one PCI bus clock input, and the M66EN of the digital logic unit U1 and the PIN PIN are connected with the M66EN of the slot through a golden finger. The bus clock state depends on the level of M66EN of slot.
When the bus load is more, an external digital logic unit U2 is needed, and the external digital logic unit U2 is used for four different PCI clock frequencies: 25 MHZ 33 MHZ 50 MHZ and 66MHz. Meets the requirements of different PXI/PXIe.
The digital logic unit U1 has two modes of assigning ownership. The default mode is that the last bus host asserts GNT. In this mode, once one PCI/PCIe or PXI/PXIe device has completed its transaction, digital logic unit U1 maintains the bus master as GNT until another device requests use of the bus, causing the arbiter to delete GNT from the current bus owner and grant it to the new requester.
The digital logic unit U1 may be configured in the second mode to be an automatic mode. In this mode, if there is no REQ from another device, digital logic unit U1 will remove GNT from the current bus owner and drive a stable mode onto the desired line.
The transfer from the PCI/PCIe bus to the PXI/PXIe bus is mainly the transfer of control signals, timing signals and address signals.
Because PXI inherits PCI control signals, PXI is an architecture based on PCI (Peripheral Component Interconnect) and compactPCI and combined with some PXI specific signals. At the same time, the addresses are preset in advance, so that the synchronization of the time sequence signals is critical.
Specific implementation process method referring to fig. 1, the digital logic unit U1 implements bus transfer and clock synchronization functions.
The digital logic unit U1 obtains PCI/PCIe signals and time sequence signals, generates PXI/PXIe signals through logic operation, and realizes the transfer from PCI/PCIe buses to PXI/PXIe buses.
The application has the technical effects and advantages that:
the PCI/PCIe slot of the original self-contained main board is realized, and the transfer from the PCI/PCIe bus to the PXI/PXIe bus is realized through signal conversion, so that the following beneficial effects are realized:
1. a lower cost PXI/PXIe instrumentation system is achieved. Because the application, the original computer motherboard with PCI/PCIe slot only, which is provided with CPU/chipset, memory hard disk and the like, can also form complete control function, and can replace the relatively expensive PXI/PXIe modularized controller necessary in the standard PXI/PXIe system. Through the circuit and the control method for switching from the PCI/PCIe bus to the PXI/PXIe bus, the original PCI/PCIe slot of the main board is converted into the PXI/PXIe slot, and the function of the backboard in the standard PXI/PXIe system is realized. Thus, a lower cost PXI/PXIe instrumentation system may be implemented.
2. The portable integrated PXI/PXIe instrument system with simpler and more reliable structure and stronger reliability and environmental adaptability can be realized. Because the independent PXI/PXIe controller module in the traditional architecture is replaced by the main board, the structure limit of the original PXI/PXIe instrument system is greatly released.
Drawings
FIG. 1 is a schematic diagram of bus transfer triggering;
FIG. 2 is a PCI/PCIe bus slot circuit diagram of a computer motherboard;
FIG. 3 is a circuit diagram of the upper half of the digital logic unit U1 according to the first embodiment of the present application;
FIG. 4 is a circuit diagram of a lower half of a digital logic unit U1 according to an embodiment of the present application;
FIG. 5 is a circuit diagram of a clock control unit U2 according to a first embodiment of the application;
FIG. 6 is a circuit diagram of a programmable memory U3 according to a first embodiment of the application;
FIG. 7 is a circuit diagram of a connector of the present application;
fig. 8 is a circuit diagram of the power supply control unit PU1 and the power supply control unit PU2 of the present application;
fig. 9 is a device diagram of the present application.
In the figure:
1. a power supply control unit PU1; 2. a power supply control unit PU2; 3. a digital logic unit U1; 4. a clock control unit U2; 5. a programmable memory U3; 6. a golden finger F1; 7. connector L1.
Detailed Description
The application will be described in further detail with reference to the drawings and the detailed description. The embodiments of the application have been presented for purposes of illustration and description, and are not intended to be exhaustive or limited to the application in the form disclosed, as the male and female ends may be interchanged in various circumstances. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, and to enable others of ordinary skill in the art to understand the application for various embodiments with various modifications as are suited to the particular use contemplated.
Example 1
Referring to fig. 1 to 7, in the present embodiment, a bus switching circuit and a control method are provided,
the power supply control device comprises a power supply control unit PU1, a power supply control unit PU2, a digital logic unit U1, a clock control unit U2, a programmable memory U3, a golden finger F1 and a connector L1.
Referring to fig. 6, the VIN pin of the power control unit PU1 is connected to the A1 pin of the PCI/PCIe bus slot through the golden finger F1 to obtain a 5V power, and the stable 5V current is output through the rectifying power control unit PU 1. The power control unit PU2 outputs a stable 3.3V current in the same way. Clock control unit U2 the pin 4 and pin 4 of clock control unit U2 are connected with PU1 to obtain 5V power. .
The power supply control unit PU1 is connected to the VDD pin of the digital logic unit U1 by the power supply control unit PU2, and provides power for the digital logic unit U1. The clock control unit U2 is connected to the PXICLK pin of the digital logic unit U1 to ensure the time synchronization from the PCI/PCIe bus to the PXI/PXIe bus, and the clock control unit U2 adopts a pi49fct807t chip in the embodiment.
The digital logic unit U1 is a core component for realizing the transfer from PCI/PCIe bus to PXI/PXIe bus, the digital logic unit U1 is connected with a PCI/PCIe bus slot of a main board through a golden finger F1, the digital logic unit U1 converts PCI/PCIe signals into PXI/PXIe signals and then sends the PXI/PXIe signals to the connector L1, and the programmable memory U3 stores relevant information such as addresses and the like. The digital logic unit U1 loads the relevant information such as the memory address from the programmable memory U3.
Referring to fig. 3, the digital logic unit U1 according to the embodiment of the application employs an XIO2001 chip.
When other components are normal, the AD1-AD31 pins of the digital logic unit U1 are connected to the corresponding pins of the PCI/PCIe bus slot through the golden finger F1, so that the reading and writing of PCI/PCIe signals are realized, and the RXN, RXP, TXN, TXP pins of the digital logic unit U1 are communicated with the corresponding pins of the connector L1, so that the reading and writing of PXI/PXIe signals are realized.
It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art and which are included in the embodiments of the present application without the inventive step, are intended to be within the scope of the present application. Structures, devices and methods of operation not specifically described and illustrated herein, unless otherwise indicated and limited, are implemented according to conventional means in the art.

Claims (7)

1. The utility model provides a bus switching circuit, its characterized in that includes power supply control unit (PU 1), power supply control unit (PU 2) and digital logic unit (U1), clock control unit (U2) and programmable memory (U3), golden finger (F1), connector (L1), power supply control unit (PU 1) with power supply control unit (PU 2) is digital logic unit (U1), clock control unit (U2) with programmable memory (U3), golden finger (F1), connector (L1) power supply.
2. A bus transfer circuit according to claim 1, wherein the power control unit (PU 1) provides a voltage of 5V.
3. A bus transfer circuit according to claim 1, wherein the power control unit (PU 2) provides a voltage of 3.3V.
4. The bus transfer circuit as recited in claim 1, wherein the digital logic unit (U1) implements PCI/PCIe bus to PXI/PXIe bus transfer with a die of XIO2001.
5. The bus transfer circuit of claim 1, wherein the clock control unit (U2) ensures time synchronization of PCI/PCIe bus to PXI/PXIe bus transfers, with pi49fct807 t.
6. The bus switching circuit according to claim 1, wherein the golden finger (F1) is a male connector, and is externally connected with an expansion card.
7. The method according to any one of claims 1 to 6, wherein the digital logic unit U1 is connected to the PCI/PCIe bus slot of the motherboard via the golden finger F1 when the connector (L1) is in a normal condition, and the digital logic unit U1 converts the PCI/PCIe signal to a PXI/PXIe signal and sends the PXI/PXIe signal to the connector L1.
CN202310393916.7A 2023-04-13 2023-04-13 Bus switching circuit and control method Pending CN117009270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310393916.7A CN117009270A (en) 2023-04-13 2023-04-13 Bus switching circuit and control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310393916.7A CN117009270A (en) 2023-04-13 2023-04-13 Bus switching circuit and control method

Publications (1)

Publication Number Publication Date
CN117009270A true CN117009270A (en) 2023-11-07

Family

ID=88564288

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310393916.7A Pending CN117009270A (en) 2023-04-13 2023-04-13 Bus switching circuit and control method

Country Status (1)

Country Link
CN (1) CN117009270A (en)

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