CN202978980U - 4 M 1553 board - Google Patents
4 M 1553 board Download PDFInfo
- Publication number
- CN202978980U CN202978980U CN 201220291012 CN201220291012U CN202978980U CN 202978980 U CN202978980 U CN 202978980U CN 201220291012 CN201220291012 CN 201220291012 CN 201220291012 U CN201220291012 U CN 201220291012U CN 202978980 U CN202978980 U CN 202978980U
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- 4mhz
- circuit board
- data
- pci bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 230000005540 biological transmission Effects 0.000 abstract description 6
- 230000006870 function Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Abstract
The utility model relates to a data transmission control field, and specially relates to a 4 M 1553 board. A 4 M 1553 board includes the components as following: a PCI bus; an FPGA which is connected with the PCI bus and used for data coding and decoding; an SRAM connected with the FPGA and used for storing data; and a 4 Mb/s interface circuit connected with the FPGA and used for data emission and reception. Preferably, the 4 Mb/s interface circuit includes a 4 MHz transmitter and a 4 MHz receiver which are respectively independent. According to the 4 M 1553 board provided in the utility model, the throughput of the bus is raised.
Description
Technical field
The utility model relates to the Data Transmission Controlling field, is specifically related to a kind of 4M1553 integrated circuit board.
Background technology
The 1553B bus claims again MIL STD1553B bus, is that US military aims at a kind of information transmission bus standard that on aircraft, equipment is formulated, the agreement of namely equipment room transmission.MIL STD1553B data/address bus has two-way output characteristic, and real-time and reliability are high, is widely used on the transporter and a considerable amount of airline carriers of passengers and military aircraft in the present age, and aerospace system is also used this bus widely.
The 1553B bus system mainly is comprised of 3 parts: bus control unit B C, remote terminal RT and optional bus monitor MT.Operating frequency is 1Mb/s.But along with transfer of data is more and more higher to the requirement of speed, the frequency of 1Mb/s can not satisfy the demand of work.
The utility model content
The purpose of this utility model is traditional 1Mb/s bus 4Mb/s that raises speed is improved bus throughput.
For this reason, the applicant has developed the 1553B interface based on 4Mb/s speed, satisfies international 1553B standard on agreement.
The application's 4M1553 integrated circuit board just is based on the transmission rate development that improves the 1553B bus.Its groundwork principle is to utilize the 4M1553 transceiver that data-signal is received, and in FPGA inside, data-signal is decoded, and then data is stored in SRAM.
Particularly, for realizing above purpose, the application adopts following scheme.
A kind of 4M1553 integrated circuit board, it comprises: pci bus; Be connected and be used for data are carried out the FPGA of Code And Decode with described pci bus; Be connected and be used for storing the SRAM of data with described FPGA; And the 4Mb/s interface circuit that is connected and is used for data input and data output with described FPGA.
Preferably, described 4Mb/s interface circuit comprises 4MHz transmitter independent of each other and 4MHz receiver.
Preferably, described pci bus is connected with described FPGA via the PCI bridge.
Preferably, described FPGA comprises the 1553B IP kernel.
Preferably, described 4MHz transmitter is connected the 4MHz transformer and is connected with bus with the 4MHz receiver.
Preferably, described integrated circuit board comprises two groups of described 4MHz transmitters and 4MHz receiver.
Preferably, described integrated circuit board comprises two described 4MHz transformers, and each 4MHz transformer is connected with the 4MHz receiver with one group of described 4MHz transmitter.
Preferably, described integrated circuit board is connected with host computer via described pci bus.
Preferably, described integrated circuit board meets the 1553B standard.
Preferably, described pci bus is the 33MHz/32b pci bus.
Improved the throughput of bus according to integrated circuit board of the present utility model.
Description of drawings
Fig. 1 is circuit principle structure schematic diagram of the present utility model.
Embodiment
Below with reference to Fig. 1, principle of the present utility model and illustrative embodiments are described.
The utility model is based on following thought: keep original 1553B bus data host-host protocol, change original physical layer circuit, design brand-new high-speed transceiver circuit.Allow the legacy data host-host protocol move on new physical layer.
In existing design, the 1553B transceiver circuit all adopts integrated chip, and running frequency is 1MHz.In the utility model, transceiver adopts separating component to form, and running frequency is 4MHz, by independently transtation mission circuit, receiving circuit consist of.
With reference to Fig. 1,4M1553 integrated circuit board of the present utility model comprises: pci bus 1; Be connected and be used for data are carried out the FPGA2 of Code And Decode with pci bus 1, this FPGA2 is connected with pci bus 1 via PCI bridge 3; FPGA2 connects and is used for storing the SRAM4 of data; And the 4Mb/s interface circuit 51,52 that is connected and is used for data input and data output with FPGA2.
Preferably, 4Mb/s interface circuit 51,52 comprises 4MHz transmitter independent of each other and 4MHz receiver.
Preferably, FPGA2 comprises 1553B IP kernel 21.
Preferably, described 4MHz transmitter is connected 4MHz transformer 61,62 and is connected with bus A, B with the 4MHz receiver.
Preferably, described integrated circuit board comprises two groups of described 4MHz transmitters and 4MHz receiver.
Preferably, described integrated circuit board comprises two 4MHz transformers 61,62, and each 4MHz transformer is connected with the 4MHz receiver with one group of described 4MHz transmitter.
Preferably, described integrated circuit board is connected with host computer via pci bus 1.
Preferably, described integrated circuit board meets the 1553B standard.
Preferably, pci bus 1 is the 33MHz/32b pci bus.
The following describes the function mode of integrated circuit board of the present utility model.
For the traffic spike of 4Mb/s, need then by FP GA2, the data flow that receives to be decoded, and store in SRAM4 by 4MHz receiver receiving data stream, read from pci interface 1 for host computer.
Simultaneously, the data that host computer sends can be written in the transmission buffer memory, FPGA2 is converted to data the 4Mb/s data flow that meets the 1553B agreement, sends by the 4MHz transmitter circuit.
Alternatively, bus interface comprises BC, a 0-31 RT, reaches three kinds of mode of operations of MT.
Alternatively, integrated circuit board is with the time tag function.
Alternatively, integrated circuit board is with the RTC function.
The above still, should be appreciated that above-mentioned explanation is only exemplary with reference to the accompanying drawings of preferred implementation of the present utility model.Those skilled in the art can under the prerequisite that does not break away from spirit and scope of the present utility model, make various modifications and variations to the utility model.Protection range of the present utility model is limited by the accompanying claims.
Claims (10)
1. 4M 1553 integrated circuit boards, is characterized in that, described integrated circuit board comprises: pci bus; Be connected and be used for data are carried out the FPGA of Code And Decode with described pci bus; Be connected and be used for storing the SRAM of data with described FPGA; And the 4Mb/s interface circuit that is connected and is used for data input and data output with described FPGA.
2. 4M 1553 integrated circuit boards according to claim 1, is characterized in that,
Described 4Mb/s interface circuit comprises 4MHz transmitter independent of each other and 4MHz receiver.
3. 4M 1553 integrated circuit boards according to claim 2, is characterized in that,
Described pci bus is connected with described FPGA via the PCI bridge.
4. 4M 1553 integrated circuit boards according to claim 2, is characterized in that,
Described FPGA comprises the 1553B IP kernel.
5. 4M 1553 integrated circuit boards according to claim 2, is characterized in that,
Described 4MHz transmitter is connected the 4MHz transformer and is connected with bus with the 4MHz receiver.
6. 4M 1553 integrated circuit boards according to claim 2, is characterized in that,
Described integrated circuit board comprises two groups of described 4MHz transmitters and 4MHz receiver.
7. according to claim 6 4M 1553 integrated circuit boards, is characterized in that,
Integrated circuit board comprises two 4MHz transformers, and each 4MHz transformer is connected with the 4MHz receiver with one group of 4MHz transmitter.
8. described 4M 1553 integrated circuit boards of any one according to claim 1 to 7, is characterized in that,
Described integrated circuit board is connected with host computer via described pci bus.
9. the described 4M1553 integrated circuit board of any one according to claim 1 to 7, is characterized in that,
Described integrated circuit board meets the 1553B standard.
10. the described 4M1553 integrated circuit board of any one according to claim 1 to 7, is characterized in that,
Described pci bus is the 33MHz/32b pci bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220291012 CN202978980U (en) | 2012-06-20 | 2012-06-20 | 4 M 1553 board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220291012 CN202978980U (en) | 2012-06-20 | 2012-06-20 | 4 M 1553 board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202978980U true CN202978980U (en) | 2013-06-05 |
Family
ID=48519996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220291012 Expired - Lifetime CN202978980U (en) | 2012-06-20 | 2012-06-20 | 4 M 1553 board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202978980U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104346315A (en) * | 2014-11-15 | 2015-02-11 | 中国航天科工集团第三研究院第八三五七研究所 | Device for relaying and switching branch of 1553 bus |
| CN107786235A (en) * | 2016-08-22 | 2018-03-09 | 北京计算机技术及应用研究所 | The 1553B transmission circuits of 4MHz working frequencies |
-
2012
- 2012-06-20 CN CN 201220291012 patent/CN202978980U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104346315A (en) * | 2014-11-15 | 2015-02-11 | 中国航天科工集团第三研究院第八三五七研究所 | Device for relaying and switching branch of 1553 bus |
| CN107786235A (en) * | 2016-08-22 | 2018-03-09 | 北京计算机技术及应用研究所 | The 1553B transmission circuits of 4MHz working frequencies |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130605 |
|
| CX01 | Expiry of patent term | ||
| DD01 | Delivery of document by public notice |
Addressee: Mao Panpan Document name: Notice of expiration and termination of patent right |
|
| DD01 | Delivery of document by public notice |