CN109344099A - FPGA application system wirelessly debugs download apparatus - Google Patents
FPGA application system wirelessly debugs download apparatus Download PDFInfo
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- CN109344099A CN109344099A CN201810878637.9A CN201810878637A CN109344099A CN 109344099 A CN109344099 A CN 109344099A CN 201810878637 A CN201810878637 A CN 201810878637A CN 109344099 A CN109344099 A CN 109344099A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/04—Modulator circuits; Transmitter circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transceivers (AREA)
Abstract
The invention discloses a kind of FPGA application systems wirelessly to debug download apparatus, it include: debugging computer end, for turning the conversion that multi-functional UART/FIFO chip realizes USB to JTAG by single channel high speed USB, and convert output general JTAG signal TMS, TCK, TDO and TDI, JTAG signal TMS, TCK and TDO pass through hyperfrequency carrier wave, and be modulated in a manner of ASK, it is sent and is exported by microstrip antenna after enhanced processing；FPGA system main control end, FPGA system main control end and debugging computer end wirelessly communicate, wherein, the modulation of signal is completed in a manner of ASK by different carrier frequencies and is sent in real time in each road of transmitting terminal, and receiving end completes the signal behavior of corresponding channel by bandpass filter, and completes demodulation, amplification and Shape correction.The device has been effectively ensured the real-time of JTAG signal and has had the same effect with wired connection debugging.
Description
Technical field
The present invention relates to FPGA (Field-Programmable Gate Array, field programmable gate array) phases
Technical field is closed, in particular to a kind of FPGA application system wirelessly debugs download apparatus.
Background technique
In the related technology, (1) FPGA downloader, independent downloading debugging module, one end pass through USB (Universal
Serial Bus, universal serial bus) cable and debugging computer interconnect, and the other end passes through cable and JTAG (Joint Test
Action Group, joint test behavior tissue) interface inter-link, at present using very universal, relatively more suitable veneer development process
In debugging, FPGA application system download debugging when module need to individually be taken out or module front panel reserve jtag interface.
(2) USB interface chip+association's controller or USB are turned serial interface chip and directly done by onboard USB-JTAG downloader
Onto module board, a USB interface is externally only reserved, is interconnected by USB cable and debugging computer when debugging.
(3) wireless USB transmission technology is based on wireless function, enables new standard, realizes using existing USB infrastructure
Wireless transmission meets USB specification, and wireless device and docking station is allowed to communicate under usb protocol.
However, (1) FPGA downloader using when need to connect USB cable and JTAG end line cable, FPGA application system module
Module need to individually be taken out and individually power when debugging downloading, single-ended power has that power supply is reversed, the risks such as short-circuit；Before module
Panel has reserved jtag interface, JTAG cable directly can be connected to panel spare interface and debugged, debugging interface need to be carried out
Electrostatic protection design, avoids long-term swapping process damage control device, and the application of panel debugging interface is not able to satisfy the electromagnetism of system
Compatible design requirement.
(2) onboard USB-JTAG downloader needs each board card module to be designed on plate, and commissioning staff is without included
FPGA downloader is directly adjustable downloading by USB cable interconnection, and use is more convenient, but needs on each board card module
USB-JTAG downloader is designed, certain space can be occupied, increases board power consumption, results in waste of resources simultaneously, USB interface is same
Shi Zhanyong panel space.
(3) download online debugging module is realized based on wireless USB transmission technology, needs to pass through USB interface protocol data
Wireless mode is sent, and which includes many usb protocol information, can have very high want to transmission carrier frequency and bandwidth
It asks, while long delay can be brought, cause debugging tool that can not find equipment or cannot be responded in time；Receiving end needs
Usb protocol information is parsed, and is converted into JTAG information, increases difficulty to design；The method can only realize two nothings
Transmission between the end line USB need to connect multiple Wireless USB ends on debugging computer, occupy if you need to connect multiple equipment simultaneously
More USB port such as uses MA-USB technology, needs to obtain MA-USB certification, while needing the driving of operating system to update and supporting.
The relevant technologies mainly realize downloading debugging by the way of wired, and wireless USB transmission technology does not obtain also very at present
Good support and application.
Summary of the invention
The application is to be made based on inventor to the understanding of following problems and discovery:
In the integrated environment that multiple FPGA and more boards cooperate, on-line debugging is directed to per a piece of FPGA
Download and solidify with code, each download link requires to interconnect by USB cable and debugging computer, be just able to achieve computer with
Data between debugged apparatus are transmitted, and also need ceaselessly to plug the different download links of switching in debugging.In some special applications
Occasion use is very inconvenient, and as higher after system chassis restocking, plug USB cable can be very inconvenient, while increasing the length of cable
Degree causes to transmit signal decaying seriously, causes long-time on-line debugging and mass data to download unstable；As system chassis designs
It is inserted to be rear, cabinet is mobile inconvenient, and plug cable can seem very inconvenient；Pass through the debugging mutual joint conference of cable between equipment simultaneously
It causes between xegregating unit altogether, to lead to equipment operation irregularity.
It is related to multiple FPGA collaborative work in FPGA application system and multimode works at the same time, if passes through switching cable
FPGA in debugging downloading single module is removed, debugging efficiency can be reduced, if existing simultaneously the module of multiple same models, be easy to cause
Equipment is not easily distinguishable, and brings very big inconvenience to debugging.
In conjunction with system integration technology and general VPX, CPCI (Compact Peripheral Component
Interconnect, compact PCI) etc. system specifications, increase system debug download link in the present invention and connect automatically and JTAG
Signal wireless transmission, realizes the more equipment debugging download apparatus of not physically connected system.
FPGA passes through code load and the on-line debugging that jtag interface agreement completes device, mode in standard JTAG
Select TMS and clock TCK that can drive with one more, the data of the data output TDO access next stage of upper level equipment input TDI, with
The mode of daisy chain realizes the series connection of more equipment, is finally aggregated into a jtag interface, passes through wireless transmission and debugging computer
Interconnection.The jtag interface of multiple FPGA, the bottom plate jtag interface that externally reserved jtag interface and general specification define on single module
Intelligent management is carried out by CPLD (Complex Programmable Logic Device, Complex Programmable Logic Devices), from
Dynamic to judge whether wireless USB apparatus accesses, whether module is system master, the adaptive series connection of JTAG link.
The present invention is directed to solve at least some of the technical problems in related technologies.
For this purpose, the device is effective it is an object of the invention to propose that a kind of FPGA application system wirelessly debugs download apparatus
It ensure that the real-time of JTAG signal, response has the same effect with wired connection debugging in time in debugging.
In order to achieve the above objectives, the embodiment of the present invention proposes a kind of FPGA application system and wirelessly debugs download apparatus, wraps
Include: turning for USB to JTAG is realized for turning multi-functional UART/FIFO chip by single channel high speed USB in debugging computer end
It changes, and converts output general JTAG signal TMS, TCK, TDO and TDI, described JTAG signal TMS, TCK and TDO pass through superelevation
Frequency carrier wave, and be modulated in a manner of ASK, it is sent and is exported by microstrip antenna after enhanced processing；FPGA system main control end, institute
It states FPGA system main control end and the debugging computer end wirelessly communicates, wherein each road of transmitting terminal passes through different carrier frequencies
The modulation of signal is completed in a manner of ASK and is sent in real time, and receiving end is selected by the signal that bandpass filter completes corresponding channel
It selects, and completes demodulation, amplification and Shape correction.
The FPGA application system of the embodiment of the present invention wirelessly debugs download apparatus, has by wireless transmission JTAG signal solution
Line connects bring inconvenience in use and problem, in debugging computer end and the wireless transmission of system master end JTAG signal,
Each road of transmitting terminal is completed the modulation of signal in a manner of ASK by different carrier frequencies and sent in real time, and receiving end is filtered by band logical
Wave device completes the signal behavior of corresponding channel, and completes demodulation, amplification and Shape correction, is not related to during entire wireless transmission
The parsing of communication between devices agreement responds timely and wired connection so that the real-time of JTAG signal be effectively ensured in debugging
Debugging has the same effect.
In addition, FPGA application system according to the above embodiment of the present invention wirelessly debug download apparatus can also have it is following
Additional technical characteristic:
Further, in one embodiment of the invention, the debugging computer end is powered by USB port, and
Under default operating condition, pass through external power supply mode power.
Further, in one embodiment of the invention, the JTAG signal at the debugging computer end uses different loads
Wave frequency rate carries out signal real-time Transmission, and carrier frequency includes 315MHz, 1200MHz, 433MHz and 868.3MHz.
Further, in one embodiment of the invention, further includes: more FPGA device backboards are connected, and are for passing through
The JTAG signal that system each module slot position of backboard defines, and pass through the series connection of TDO and TDI series connection realization data channel, TMS and TCK
It is connected by the way of more than being driven using one.
Further, in one embodiment of the invention, further includes: more FPGA device wireless serials, system Nei Gemo
Block all designs JTAG wireless transmission function, is received by the local frequency and TDI hyperfrequency that select TDO hyperfrequency sendaisle logical
Road bandpass filter parameter realizes the wireless connection between two modules TDO and TDI.
Further, in one embodiment of the invention, using the modulation principle of ASK, carrier amplitude is with modulation
JTAG signal and change, to generate communication in the debugging computer end and the FPGA system main control end.
Further, in one embodiment of the invention, pass through the different carrier frequencies of increase TDO signal and TDI signal
Rate completes the JTAG link wireless serial of more equipment.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, in which:
Fig. 1 is the structural schematic diagram that download apparatus is wirelessly debugged according to the FPGA application system of one embodiment of the invention；
Fig. 2 is the structural schematic diagram according to more FPGA device wireless serials of one embodiment of the invention；
Fig. 3 is the schematic diagram applied according to the wireless downloading device FPGA system of one embodiment of the invention.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
The FPGA application system for describing to propose according to embodiments of the present invention with reference to the accompanying drawings wirelessly debugs download apparatus.
Fig. 1 is that the FPGA application system of one embodiment of the invention wirelessly debugs the structural schematic diagram of download apparatus.
As shown in Figure 1, it includes: debugging computer end 100 and FPGA that the FPGA application system, which wirelessly debugs download apparatus 10,
System master end 200.
Wherein, debugging computer end 100 is used to turn multi-functional UART/FIFO chip by single channel high speed USB to realize USB
To the conversion of JTAG, and output general JTAG signal TMS, TCK, TDO and TDI are converted, JTAG signal TMS, TCK and TDO are logical
Hyperfrequency carrier wave is crossed, and is modulated in a manner of ASK, is sent and is exported by microstrip antenna after enhanced processing.FPGA system master
It controls end 200FPGA system master end and debugging computer end to wirelessly communicate, wherein each road of transmitting terminal passes through different carrier frequencies
The modulation of signal is completed in a manner of ASK and is sent in real time, and receiving end is selected by the signal that bandpass filter completes corresponding channel
It selects, and completes demodulation, amplification and Shape correction.Entirely wireless transmission is not related to equipment to the device 10 of the embodiment of the present invention in the process
Between communication protocol parsing, be effectively ensured the real-time of JTAG signal, response has with wired connection debugging in time in debugging
Identical effect.
Specifically, debugging computer end 100, which turns multi-functional UART/FIFO chip by single channel high speed USB, realizes USB
To the conversion of JTAG, conversion exports general JTAG signal TMS, TCK, TDO and TDI；JTAG signal TMS, TCK and TDO pass through super
High frequency carrier is modulated in a manner of ASK, is sent and is exported by microstrip antenna after amplification.FPGA system main control end 200 is set
It is placed in master control groove position control panel in FPGA application system, wireless receiving and dispatching transmission can be carried out by hyperfrequency and debugging computer end,
JTAG signal after demodulation, amplification, shaping is connected in system equipment.Wherein, TCK is for test clock input；TDI is used to survey
Data input is tried, data input JTAG mouthfuls by TDI；TDO is exported by TDO from JTAG mouthfuls for test data output, data；
For TMS for test pattern selection, TMS is used to be arranged JTAG mouthfuls in certain specific test pattern.
Further, in one embodiment of the invention, debugging computer end 100 is powered by USB port, and pre-
If under operating condition, passing through external power supply mode power.
In one embodiment of the invention, the JTAG signal at debugging computer end carries out signal using different carrier frequencies
Real-time Transmission, carrier frequency include 315MHz, 1200MHz, 433MHz and 868.3MHz.
Specifically, debugging computer end 100 is powered by USB port, for example, being needed using remote downloading debugging
Increase transmitting terminal power, external power supply mode can be used；The JTAG signal at debugging computer end 100 is using four kinds of different carrier frequencies
Rate carries out signal real-time Transmission, and carrier frequency f1 is 315MHz, f2 1200MHz, f3 433MHz, f4 868.3MHz.
Further, in one embodiment of the invention, the device 10 of the embodiment of the present invention is former using the modulation of ASK
Reason, carrier amplitude are changed with modulation JTAG signal, are produced at debugging computer end 100 and FPGA system main control end 200
Raw communication.
The embodiment of the present invention passes through the JTAG link of FPGA system main control end 200, in conjunction with the JTAG link in System Backplane
Series connection, the final JTAG link series connection for realizing FPGA in all modules in FPGA application system are completed eventually by wireless transmission
The downloading of system all devices is debugged, this mode compares in the FPGA application system more suitable for number of devices.
Further, in one embodiment of the invention, pass through the different carrier frequencies of increase TDO signal and TDI signal
Rate completes the JTAG link wireless serial of more equipment.
Specifically, the embodiment of the present invention completes more equipment by the different carrier frequencies of increase TDO and TDI signal
JTAG link wireless serial, in order to reduce the interference between frequency range, this mode compares the FPGA application less suitable for number of devices
In system.
Wireless downloading device FPGA system is applied as shown in Fig. 2, one piece of board in equipment cabinets is as FPGA system master
End 200 is controlled, is responsible for the transmitting-receiving of wireless JTAG signal, wireless debugging download apparatus is accessed by USB in debugging computer end 100, real
The on-line debugging and download function of the FPGA of existing FPGA application system.
Further, in one embodiment of the invention, as shown in Figure 1, the device 10 of the embodiment of the present invention further include:
More FPGA device backboard series connection 300.Wherein, more FPGA device backboard series connection 300 are for fixed by each module slot position of System Backplane
The JTAG signal of justice, and connected in such a way that a drive is more by the series connection of TDO and TDI series connection realization data channel, TMS and TCK
It connects.
Further, in one embodiment of the invention, as shown in figure 3, the device 10 of the embodiment of the present invention further include:
More FPGA device wireless serials.Wherein, more FPGA device wireless serials, each module all designs JTAG wireless transmission function in system
Can, by selecting the local frequency and TDI hyperfrequency receiving channel bandpass filter parameter of TDO hyperfrequency sendaisle, realize
Wireless connection between two modules TDO and TDI.
In addition, the automatic detection of module insertion in FPGA application system, by monitoring automatic series connection backboard respective modules
JTAG link.Each master/slave mode detection signal of module design JTAG in system, system master end JTAG are holotype, main control end
Controlling other slot position modules is all slave pattern, and is together in series by backboard.
The embodiment of the present invention has the advantages that
(1) wired debugging bring inconvenience and limitation are solved.
(2) only need to design wireless JTAG in main control end in application system can be to FPGA should entirely carrying out in system module
Debugging downloading.
(3) do not consider further that JTAG access when whether electrical level match, no longer because level mismatch due to damage device link.
(4) selection frequency range will not impact general-purpose wireless device.
(5) it can choose when not in use and turn off JTAG wireless transmission function, reduce power consumption.
(6) it may be located remotely from the brings noise such as system radiating fan when commissioning device, improve debugging efficiency.
The FPGA application system proposed according to embodiments of the present invention wirelessly debugs download apparatus, passes through wireless transmission JTAG letter
Number solve the problems, such as wired connection bring in use it is inconvenient and, it is wireless at debugging computer end and system master end JTAG signal
In transmission, each road of transmitting terminal is completed the modulation of signal in a manner of ASK by different carrier frequencies and sent in real time, and receiving end passes through
Bandpass filter completes the signal behavior of corresponding channel, and completes demodulation, amplification and Shape correction, during entire wireless transmission
It is not related to the parsing of communication between devices agreement, so that the real-time of JTAG signal be effectively ensured, is responded in time in debugging, and have
Line connection debugging has the same effect.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (7)
1. a kind of FPGA application system wirelessly debugs download apparatus characterized by comprising
Turning for USB to JTAG is realized for turning multi-functional UART/FIFO chip by single channel high speed USB in debugging computer end
It changes, and converts output general JTAG signal TMS, TCK, TDO and TDI, described JTAG signal TMS, TCK and TDO pass through superelevation
Frequency carrier wave, and be modulated in a manner of ASK, it is sent and is exported by microstrip antenna after enhanced processing；
FPGA system main control end, the FPGA system main control end and the debugging computer end wirelessly communicate, wherein transmitting terminal
Each road is completed the modulation of signal in a manner of ASK by different carrier frequencies and sent in real time, and receiving end passes through bandpass filter
The signal behavior of corresponding channel is completed, and completes demodulation, amplification and Shape correction.
2. FPGA application system according to claim 1 wirelessly debugs download apparatus, which is characterized in that the debugging calculates
Generator terminal is powered by USB port, and under default operating condition, passes through external power supply mode power.
3. FPGA application system according to claim 2 wirelessly debugs download apparatus, which is characterized in that the debugging calculates
The JTAG signal of generator terminal using different carrier frequencies carry out signal real-time Transmission, carrier frequency include 315MHz, 1200MHz,
433MHz and 868.3MHz.
4. FPGA application system according to claim 1 wirelessly debugs download apparatus, which is characterized in that further include:
The series connection of more FPGA device backboards, the JTAG signal for being defined by each module slot position of System Backplane, and by TDO with
TDI series connection realizes that the series connection of data channel, TMS and TCK are connected in such a way that a drive is more.
5. FPGA application system according to claim 4 wirelessly debugs download apparatus, which is characterized in that further include:
More FPGA device wireless serials, each module all designs JTAG wireless transmission function in system, by selecting TDO superelevation to take place frequently
The local frequency and TDI hyperfrequency receiving channel bandpass filter parameter for sending channel, are realized between two modules TDO and TDI
It is wirelessly connected.
6. FPGA application system according to claim 1 wirelessly debugs download apparatus, which is characterized in that using the tune of ASK
Principle processed, carrier amplitude changes with modulation JTAG signal, at the debugging computer end and the FPGA system master control
End generates communication.
7. FPGA application system according to claim 1 wirelessly debugs download apparatus, which is characterized in that by increasing TDO
The different carrier frequencies of signal and TDI signal complete the JTAG link wireless serial of more equipment.
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| CN201810878637.9A CN109344099B (en) | 2018-08-03 | 2018-08-03 | Wireless debugging and downloading device for FPGA application system |
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| CN116679994A (en) * | 2023-07-21 | 2023-09-01 | 北京汤谷软件技术有限公司 | High-efficiency interface configuration method for FPGA prototype verification platform |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110888046A (en) * | 2019-11-25 | 2020-03-17 | 展讯通信（上海）有限公司 | System-on-chip and test method, storage medium and terminal thereof |
| CN112255598A (en) * | 2020-10-14 | 2021-01-22 | 四川九洲空管科技有限责任公司 | FPGA remote online debugging method, device and system based on optical fiber communication |
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| CN116679994A (en) * | 2023-07-21 | 2023-09-01 | 北京汤谷软件技术有限公司 | High-efficiency interface configuration method for FPGA prototype verification platform |
| CN116679994B (en) * | 2023-07-21 | 2023-10-31 | 北京汤谷软件技术有限公司 | High-efficiency interface configuration method for FPGA prototype verification platform |
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| CN109344099B (en) | 2020-06-19 |
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