CN103091626B - Joint test action group (JTAG) test link and diasonograph thereof - Google Patents
Joint test action group (JTAG) test link and diasonograph thereof Download PDFInfo
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- CN103091626B CN103091626B CN201110346014.5A CN201110346014A CN103091626B CN 103091626 B CN103091626 B CN 103091626B CN 201110346014 A CN201110346014 A CN 201110346014A CN 103091626 B CN103091626 B CN 103091626B
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Abstract
The invention discloses a joint test action group (JTAG) test link. The JTAG test link comprises a partial board card test interface and a complete machine test interface, and is characterized by further comprising a multipath input selection switch and a multipath output selection switch, wherein a signal input interface in the partial board card test interface is connected to a high potential end in the multipath input selection switch; a signal output interface in the partial board card test interface is connected to a high potential end in the multipath output selection switch; a signal input interface in the complete machine test interface is connected to a low potential end in the multipath input selection switch; a signal output interface of the complete machine test interface is connected to a low potential end in the multipath output selection switch; and the multipath input selection switch and the multipath output selection switch simultaneously choose the high potential ends or simultaneously choose the low potential ends. According to the JTAG test link, partial board card test signals and complete machine test signals can be protected from being switched in at the same time.
Description
[technical field]
The present invention relates to JTAG (Joint Test Action Group, joint test behavior tissue) test, especially relate to a kind of jtag test link and diasonograph thereof.
[background technology]
In each stage of product development, if jtag port can be passed through easily, device is tested and function debugging, development efficiency and development quality can be improved greatly.Therefore, in diasonograph, except connecting the connector of JTAG cable on board, also back panel connector can be passed through, so no matter by the JTAG link of machine system, be also connected on board, be the local board debug phase, or after the complete machine cabinet of board loading diasonograph (interface of complete machine JTAG link can draw cabinet), JTAG instrument can be convenient to use.
Local board JTAG link on traditional board and machine system JTAG link are be connected directly between together by signal, as shown in Figure 1.Together with local board JTAG is connected directly between with machine system JTAG signal, in this case, a drive source can only be there is, if when using the JTAG link of machine system, accidentally also being connected to the cable of local board JTAG, all there is the risk of damage in that device and jtag interface circuit.
[summary of the invention]
Based on this, be necessary to provide a kind of jtag test link can avoiding simultaneously accessing local board test signal and system test signal.
A kind of jtag test link, comprises local board test interface and system test interface, it is characterized in that, also comprise multichannel input selector switch and multiple-channel output selector switch; Local board test data input line interface in the board test interface of described local, local board test clock input interface and local board test pattern selection input interface are connected to the hot end in multichannel input selector switch; Local board test data output line interface in the board test interface of described local is connected to the hot end in multiple-channel output selector switch; System test Data In-Line interface in described system test interface, system test clock input interface and system test model selection input interface are connected to the cold end in multichannel input selector switch; System test DOL Data Output Line interface in described system test interface is connected to the cold end in multiple-channel output selector switch; Described multichannel input selector switch and multiple-channel output selector switch comprise control of Electric potentials end, when the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch is noble potential, described local board test interface is by multichannel input selector switch and the input and output respectively of multiple-channel output selector switch; When the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch is electronegative potential, described system test interface is by multichannel input selector switch and the input and output respectively of multiple-channel output selector switch.
Preferably, described local board test interface also comprises current potential option interface, and described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch; Described jtag test link also comprises jtag test plug, and described jtag test plug has the calibrating terminal corresponding with described local board test interface, and wherein corresponding with described current potential option interface calibrating terminal is connected to noble potential.
Preferably, described local board test interface also comprises noble potential interface, described noble potential interface is connected to power supply, and described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch, and passes through resistance eutral grounding; Described jtag test link also comprises jtag test plug, described jtag test plug has the calibrating terminal corresponding with described local board test interface, wherein corresponding with described noble potential interface calibrating terminal and the calibrating terminal short circuit corresponding with described current potential option interface.
Preferably, described local board test interface also comprises ground interface, described ground interface is connected to ground, described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch by phase inverter, and is connected to power supply by resistance between described phase inverter and described current potential option interface; Described jtag test plug has the calibrating terminal corresponding with described local board test interface, wherein corresponding with described ground interface calibrating terminal and the calibrating terminal short circuit corresponding with described current potential option interface.
A kind of jtag test link, comprises local board test interface and system test interface, also comprises multichannel input selector switch and multiple-channel output selector switch; Local board test data input line interface in the board test interface of described local, local board test clock input interface and local board test pattern selection input interface are connected to the cold end in multichannel input selector switch; Local board test data output line interface in the board test interface of described local is connected to the cold end in multiple-channel output selector switch; System test Data In-Line interface in described system test interface, system test clock input interface and system test model selection input interface are connected to the hot end in multichannel input selector switch; System test DOL Data Output Line interface in described system test interface is connected to the hot end in multiple-channel output selector switch; Described multichannel input selector switch and multiple-channel output selector switch comprise control of Electric potentials end, when the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch is electronegative potential, described local board test interface is by multichannel input selector switch and the input and output respectively of multiple-channel output selector switch; When the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch is noble potential, described system test interface is by multichannel input selector switch and the input and output respectively of multiple-channel output selector switch.
Preferably, described local board test interface also comprises current potential option interface, and described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch; Described jtag test link also comprises jtag test plug, and described jtag test plug has the calibrating terminal corresponding with described local board test interface, and wherein corresponding with described current potential option interface calibrating terminal is connected to electronegative potential.
Preferably, described local board test interface also comprises noble potential interface, described noble potential interface is connected to power supply, described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch by phase inverter, and passes through resistance eutral grounding between described phase inverter and described current potential option interface; Described jtag test link also comprises jtag test plug, described jtag test plug has the calibrating terminal corresponding with described local board test interface, wherein corresponding with described noble potential interface calibrating terminal and the calibrating terminal short circuit corresponding with described current potential option interface.
Preferably, described local board test interface also comprises local board test reset input line interface, described system test interface also comprises system test reset input line interface, and described local board test reset input line interface and system test reset input line interface are connected to cold end and the hot end of described multichannel input selector switch respectively.
Preferably, described local board test interface also comprises ground interface, described ground interface is connected to ground, and described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch, and is connected to power supply by resistance; Described jtag test plug has the calibrating terminal corresponding with described local board test interface, wherein corresponding with described ground interface calibrating terminal and the calibrating terminal short circuit corresponding with described current potential option interface.
A kind of diasonograph, comprises above-mentioned jtag test link.
Because multichannel input selector switch and multiple-channel output selector switch can only be in a kind of state at every turn, therefore can only introduce a kind of test signal at every turn, be local board test signal, or be system test signal, can avoid accessing local board test signal and system test signal simultaneously.
Further, the current potential option interface of the control of Electric potentials end being connected to multichannel input selector switch and multiple-channel output selector switch is provided with on the board test interface of local, and the calibrating terminal corresponding with this current potential option interface is provided with on jtag test plug, noble potential or electronegative potential should be connected to by the calibrating terminal corresponding with current potential option interface, therefore when jtag test plug inserts local board test interface, the calibrating terminal corresponding with current potential option interface of this jtag test plug and this current potential option interface electrical contact, thus this current potential option interface is connected to noble potential or electronegative potential, like this, the control of Electric potentials end of multichannel input selector switch and multiple-channel output selector switch is made automatically to be connected to noble potential or electronegative potential, thus automatic gating local board test interface, avoid manual control switch and select the noble potential of current potential option interface or the step of electronegative potential, handled easily.
[accompanying drawing explanation]
Fig. 1 is traditional jtag test link schematic diagram;
Fig. 2 is the jtag test link schematic diagram of the first embodiment;
Fig. 3 is the control of Electric potentials mode schematic diagram of the jtag test link of the first embodiment;
Fig. 4 is the control of Electric potentials mode schematic diagram of the jtag test link of another embodiment.
[embodiment]
As shown in Figure 2, be the jtag test link of the first embodiment.This test link 100 is for providing test signal and receiving the output signal of feedback to device under test 200, the test signal provided can be local board test signal, also can be system test signal.TMS_DEVICE, TCK_DEVICE and TDI_DEVICE in device under test 200 represent the mode select signal, clock signal and the input signal of test data that input device under test 200 respectively, these signals can come from local board test interface or system test interface, TDO_DEVICE represents the output signal fed back from device under test 200, can output to local board test interface or system test interface.By input test signal, check that the output signal of feedback just can be carried out testing and function debugging by device under test.
The test link structure 100 of the present embodiment comprises local board test interface 110, system test interface 120, multichannel input selector switch 130 and multiple-channel output selector switch 140.
Local board test data input line interface (TDI_BOARD) in local board test interface 110, local board test clock input interface (TCK_BOARD) and local board test pattern selection input interface (TMS_BOARD) are connected to the hot end in multichannel input selector switch 130.Local board test data output line interface (TDO_BOARD) in local board test interface 110 is connected to the hot end in multiple-channel output selector switch 140.
System test Data In-Line interface (TDI_SYSTEM) in system test interface 120, system test clock input interface (TCK_SYSTEM) and system test model selection input interface (TMS_SYSTEM) are connected to the cold end in multichannel input selector switch 130.System test DOL Data Output Line interface (TDO_SYSTEM) in system test interface 120 is connected to the cold end in multiple-channel output selector switch 140.
Multichannel input selector switch 130 and multiple-channel output selector switch 140 are equipped with control of Electric potentials end, different circuit can be communicated with by the selection of the high electronegative potential of this control of Electric potentials end, can be set to when control of Electric potentials end is connected to noble potential, gating local board test interface 110; When control of Electric potentials end is connected to electronegative potential, gating system test interface 120.Certainly, those skilled in that art's easy understand, also can be set to when control of Electric potentials end is connected to electronegative potential, gating local board test interface 110; When control of Electric potentials end is connected to noble potential, gating system test interface 120.Be described for the former in the present embodiment.The control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 can be set to be connected to noble potential simultaneously or be connected to electronegative potential simultaneously.
In the present embodiment, when the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 is noble potential, gating local board test interface 110, now local board test interface 110 is by multichannel input selector switch 130 and multiple-channel output selector switch 140 input and output respectively.
In the present embodiment, when the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 is electronegative potential, gating system test interface 120.Now system test interface 120 is by multichannel input selector switch 130 and multiple-channel output selector switch 140 input and output respectively.
In the present embodiment, by the control to multichannel input selector switch 130 and multiple-channel output selector switch 140, from the test signal of local board test interface 110 input with a kind of test signal can only be had to input device under test 200 from the test signal that system test interface 120 inputs at every turn, thus avoid input local board test signal and system test signal simultaneously.
In the present embodiment, the mode controlling multichannel input selector switch 130 and multiple-channel output selector switch 140 is the current potential selecting side input high level or the low level that make multichannel input selector switch 130 and multiple-channel output selector switch 140.Make the current potential selecting side input high level of multichannel input selector switch 130 and multiple-channel output selector switch 140 or low level that various ways can be adopted to realize.
In the present embodiment, as shown in Figure 3, local board test interface 110, except comprising local board test data input line interface (TDI_BOARD), local board test clock input interface (TCK_BOARD), local board test pattern selection input interface (TMS_BOARD) and local board test data output line interface (TDO_BOARD), also comprises noble potential interface (VDD2) and current potential option interface (SEL).Noble potential interface (VDD2) is connected power supply (VDD) with the power interface (VDD1) in local board test interface 110 simultaneously.Current potential option interface (SEL) is connected to the control of Electric potentials end (SEL) of multichannel input selector switch 130 and multiple-channel output selector switch 140, and simultaneously also by resistance R ground connection.
Jtag test link 100 also comprises jtag test plug 300, jtag test plug 300 is corresponding with local board test interface 110 has calibrating terminal, wherein with local board test data input line interface (TDI_BOARD), local board test clock input interface (TCK_BOARD), local board test pattern selects input interface (TMS_BOARD), local board test data output line interface (TDO_BOARD), the calibrating terminal of ground interface (GND) and power interface (VDD1) correspondence is all connected to outside test signal interface by cable 400.And two the calibrating terminal short circuits corresponding with noble potential interface (VDD2) and current potential option interface (SEL).
Herein, the terminal being described as " correspondence " refers to when jtag test plug accesses in the board test interface of local and the terminal of certain interface electrical contact in the board test interface of local.
Therefore, when jtag test plug 300 does not access local board test interface 110, the control of Electric potentials end (SEL) of multichannel input selector switch 130 and multiple-channel output selector switch 140 is by resistance R ground connection, for electronegative potential, therefore multichannel input selector switch 130 and multiple-channel output selector switch 140 gating system test interface 120.Now system test interface 120 can by multichannel input selector switch 130 and multiple-channel output selector switch 140 input and output respectively.
And when jtag test plug 300 accesses local board test interface 110, current potential option interface (SEL) is electrically connected with terminal corresponding with this current potential option interface (SEL) in jtag test plug 300, due to two calibrating terminal short circuits corresponding with noble potential interface (VDD2) and this current potential option interface (SEL) in jtag test plug 300, now current potential option interface (SEL) is connected to the power supply VDD on noble potential interface (VDD2) by two calibrating terminals of short circuit, thus the control of Electric potentials end (SEL) of multichannel input selector switch 130 and multiple-channel output selector switch 140 is noble potential, gating local board test interface 110.Now system test interface 120 is not by multichannel input selector switch 130 and multiple-channel output selector switch 140 input and output respectively.Local board test interface 110 is then by multichannel input selector switch 130 and multiple-channel output selector switch 140 input and output respectively.
On the basis of above-described embodiment, local board test interface 110 can also comprise local board test reset input line interface (TRST_BOARD), system test interface 120 can also comprise system test reset input line interface (TRST_SYSTEM), and local board test reset input line interface (TRST_BOARD) and system test reset input line interface (TRST_SYSTEM) are connected to hot end and the cold end of multichannel input selector switch 130 respectively.In addition, more test signal kind can also be increased to enrich test function.
As mentioned before, also can be set to when control of Electric potentials end is connected to electronegative potential, gating local board test interface 110; When control of Electric potentials end is connected to noble potential, gating system test interface 120.Such as, in other embodiments, also the corresponding cold end of the test interface 110 of local board to multichannel input selector switch 130 and multiple-channel output selector switch 140 can be connected.The corresponding hot end of system test interface 120 to multichannel input selector switch 130 and multiple-channel output selector switch 140 is connected simultaneously.Current potential option interface (SEL) is connected to the control of Electric potentials end (SEL) of multichannel input selector switch 130 and multiple-channel output selector switch 140 by phase inverter, and by resistance R ground connection between this phase inverter and this current potential option interface.Like this, when jtag test plug 300 does not access local board test interface 110, control of Electric potentials end is by phase inverter ground connection, and therefore control of Electric potentials end is noble potential, now multichannel input selector switch 130 and multiple-channel output selector switch 140 gating system test interface 120, when jtag test plug 300 accesses local board test interface 110, current potential option interface (SEL) is electrically connected with terminal corresponding with this current potential option interface (SEL) in jtag test plug 300, due to two calibrating terminal short circuits corresponding with noble potential interface (VDD2) and this current potential option interface (SEL) in jtag test plug 300, therefore current potential option interface (SEL) is connected to the power supply VDD on noble potential interface (VDD2) by two calibrating terminals of short circuit, because this current potential option interface (SEL) to be connected to the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 by phase inverter, therefore now this control of Electric potentials end (SEL) is electronegative potential, gating local board test interface 110.
In another embodiment, also the corresponding cold end of local board test interface 110 to multichannel input selector switch 130 and multiple-channel output selector switch 140 can be connected.The corresponding hot end of system test interface 120 to multichannel input selector switch 130 and multiple-channel output selector switch 140 is connected simultaneously.Local board test interface 110 comprises ground interface and current potential option interface.Wherein ground interface ground connection, current potential option interface is connected to the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140, and is also connected to power supply VDD by resistance R simultaneously.Further, in jtag test plug 300, corresponding to the terminal short circuit of ground interface and current potential option interface.Like this, when jtag test plug 300 is not linked into local board test interface 110, the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 is connected to power supply VDD by resistance R, is noble potential, now gating system test interface 120; When jtag test plug 300 is linked into local board test interface 110, the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 receives ground by the connecting terminals corresponding to ground interface and current potential option interface of short circuit on jtag test plug 300, therefore now the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 is electronegative potential, gating local board test interface 110.
In another embodiment, also the corresponding hot end of local board test interface 110 to multichannel input selector switch 130 and multiple-channel output selector switch 140 can be connected.The corresponding cold end of system test interface 120 to multichannel input selector switch 130 and multiple-channel output selector switch 140 is connected simultaneously.Local board test interface 110 comprises ground interface and current potential option interface.Wherein ground interface ground connection, current potential option interface is connected to the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 by phase inverter, and is connected to power supply VDD by resistance R between current potential option interface and phase inverter.Further, in jtag test plug 300, corresponding to the terminal short circuit of ground interface and current potential option interface.Like this, when jtag test plug 300 is not linked into local board test interface 110, the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 is connected to power supply VDD by phase inverter and resistance R, therefore now this control of Electric potentials end is electronegative potential, now gating system test interface 120; When jtag test plug 300 is linked into local board test interface 110, the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 receives ground by the connecting terminals corresponding to ground interface and current potential option interface of short circuit on phase inverter and jtag test plug 300, therefore now the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 is noble potential, gating local board test interface 110.
On this basis, local board test interface 110 can also comprise local board test reset input line interface (TRST_BOARD), system test interface 120 can also comprise system test reset input line interface (TRST_SYSTEM), and local board test reset input line interface (TRST_BOARD) and system test reset input line interface (TRST_SYSTEM) are connected to cold end and the hot end of multichannel input selector switch 130 respectively.In addition, more test signal kind can also be increased to enrich test function.
In another embodiment, as shown in Figure 4, local board test interface 710, except comprising local board test data input line interface (TDI_BOARD), local board test clock input interface (TCK_BOARD), local board test pattern selection input interface (TMS_BOARD) and local board test data output line interface (TDO_BOARD), also comprises current potential option interface (SEL).Wherein local board test data input line interface (TDI_BOARD), local board test clock input interface (TCK_BOARD), local board test pattern select the connected mode of input interface (TMS_BOARD) and local board test data output line interface (TDO_BOARD) same as the previously described embodiments.
Jtag test plug 810 is connected with local board test interface 710, and jtag test plug 810 is corresponding with local board test interface 710 has calibrating terminal, and calibrating terminal is connected to another jtag test plug 830 by signal cable 820.In this jtag test plug 830, current potential option interface (SEL) can be drawn and be connected to noble potential or electronegative potential, like this, when jtag test plug 810 accesses in local board test interface 710, the control of Electric potentials end of multichannel input selector switch 130 and multiple-channel output selector switch 140 can be made to be connected to noble potential or electronegative potential, thus this local board test interface 710 of gating.Like this, the current potential of multi-way switch can be controlled at the other end, handled easily.
In previous embodiment, describe the method that several current potential option interface (SEL) by local board test interface 110 is connected to noble potential or electronegative potential, should be appreciated that, current potential option interface (SEL) can also be made for noble potential or electronegative potential by other mode, such as be directly connected to power supply or be connected to the circuit position or ground connection with noble potential or be connected to circuit position with electronegative potential etc., this is no longer going to repeat them.
In the embodiment that the present invention is other, can above-mentioned jtag test link be applied in diasonograph, to ensure the security of test and to improve testing efficiency.
In the embodiment of the present invention, the current potential option interface of the control of Electric potentials end being connected to multichannel input selector switch and multiple-channel output selector switch is provided with on the board test interface of local, and the calibrating terminal corresponding with this current potential option interface is provided with on jtag test plug, noble potential or electronegative potential should be connected to by the calibrating terminal corresponding with current potential option interface, therefore when jtag test plug inserts local board test interface, the calibrating terminal corresponding with current potential option interface of this jtag test plug and this current potential option interface electrical contact, thus this current potential option interface is connected to noble potential or electronegative potential, like this, the control of Electric potentials end of multichannel input selector switch and multiple-channel output selector switch is made automatically to be connected to noble potential or electronegative potential, thus automatic gating local board test interface, avoid manual control switch and select the noble potential of current potential option interface or the step of electronegative potential, handled easily.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a jtag test link, comprises local board test interface and system test interface, it is characterized in that, also comprise multichannel input selector switch and multiple-channel output selector switch;
Local board test data input line interface in the board test interface of described local, local board test clock input interface and local board test pattern selection input interface are connected to the hot end in multichannel input selector switch; Local board test data output line interface in the board test interface of described local is connected to the hot end in multiple-channel output selector switch;
System test Data In-Line interface in described system test interface, system test clock input interface and system test model selection input interface are connected to the cold end in multichannel input selector switch; System test DOL Data Output Line interface in described system test interface is connected to the cold end in multiple-channel output selector switch;
Described multichannel input selector switch and multiple-channel output selector switch comprise control of Electric potentials end, when the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch is noble potential, described local board test interface is by multichannel input selector switch and the input and output respectively of multiple-channel output selector switch; When the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch is electronegative potential, described system test interface is by multichannel input selector switch and the input and output respectively of multiple-channel output selector switch.
2. jtag test link as claimed in claim 1, it is characterized in that, described local board test interface also comprises current potential option interface, and described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch;
Described jtag test link also comprises jtag test plug, and described jtag test plug has the calibrating terminal corresponding with described local board test interface, and wherein corresponding with described current potential option interface calibrating terminal is connected to noble potential.
3. jtag test link as claimed in claim 2, it is characterized in that, described local board test interface also comprises noble potential interface, and described noble potential interface is connected to power supply, and described current potential option interface passes through resistance eutral grounding;
Described jtag test plug has the calibrating terminal corresponding with described local board test interface, wherein corresponding with described noble potential interface calibrating terminal and the calibrating terminal short circuit corresponding with described current potential option interface.
4. jtag test link as claimed in claim 2, it is characterized in that, described local board test interface also comprises ground interface, described ground interface is connected to ground, described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch by phase inverter, and is connected to power supply by resistance between described phase inverter and described current potential option interface;
Described jtag test plug has the calibrating terminal corresponding with described local board test interface, wherein corresponding with described ground interface calibrating terminal and the calibrating terminal short circuit corresponding with described current potential option interface.
5. a jtag test link, comprises local board test interface and system test interface, it is characterized in that, also comprise multichannel input selector switch and multiple-channel output selector switch;
Local board test data input line interface in the board test interface of described local, local board test clock input interface and local board test pattern selection input interface are connected to the cold end in multichannel input selector switch; Local board test data output line interface in the board test interface of described local is connected to the cold end in multiple-channel output selector switch;
System test Data In-Line interface in described system test interface, system test clock input interface and system test model selection input interface are connected to the hot end in multichannel input selector switch; System test DOL Data Output Line interface in described system test interface is connected to the hot end in multiple-channel output selector switch;
Described multichannel input selector switch and multiple-channel output selector switch comprise control of Electric potentials end, when the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch is electronegative potential, described local board test interface is by multichannel input selector switch and the input and output respectively of multiple-channel output selector switch; When the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch is noble potential, described system test interface is by multichannel input selector switch and the input and output respectively of multiple-channel output selector switch.
6. jtag test link as claimed in claim 5, it is characterized in that, described local board test interface also comprises current potential option interface, and described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch;
Described jtag test link also comprises jtag test plug, and described jtag test plug has the calibrating terminal corresponding with described local board test interface, and wherein corresponding with described current potential option interface calibrating terminal is connected to electronegative potential.
7. jtag test link as claimed in claim 6, it is characterized in that, described local board test interface also comprises noble potential interface, described noble potential interface is connected to power supply, described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch by phase inverter, and passes through resistance eutral grounding between described phase inverter and described current potential option interface;
Described jtag test plug has the calibrating terminal corresponding with described local board test interface, wherein corresponding with described noble potential interface calibrating terminal and the calibrating terminal short circuit corresponding with described current potential option interface.
8. jtag test link as claimed in claim 5, it is characterized in that, described local board test interface also comprises local board test reset input line interface, described system test interface also comprises system test reset input line interface, and described local board test reset input line interface and system test reset input line interface are connected to cold end and the hot end of described multichannel input selector switch respectively.
9. jtag test link as claimed in claim 6, it is characterized in that, described local board test interface also comprises ground interface, described ground interface is connected to ground, described current potential option interface is connected to the control of Electric potentials end of described multichannel input selector switch and multiple-channel output selector switch, and is connected to power supply by resistance;
Described jtag test plug has the calibrating terminal corresponding with described local board test interface, wherein corresponding with described ground interface calibrating terminal and the calibrating terminal short circuit corresponding with described current potential option interface.
10. a diasonograph, is characterized in that: comprise the jtag test link as described in any one of claim 1 ~ 9.
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| CN201110346014.5A CN103091626B (en) | 2011-11-04 | 2011-11-04 | Joint test action group (JTAG) test link and diasonograph thereof |
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| CN201110346014.5A CN103091626B (en) | 2011-11-04 | 2011-11-04 | Joint test action group (JTAG) test link and diasonograph thereof |
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| CN103091626A (en) | 2013-05-08 |
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