CN203705599U - Semiconductor device detector - Google Patents
Semiconductor device detector Download PDFInfo
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- CN203705599U CN203705599U CN201420009043.1U CN201420009043U CN203705599U CN 203705599 U CN203705599 U CN 203705599U CN 201420009043 U CN201420009043 U CN 201420009043U CN 203705599 U CN203705599 U CN 203705599U
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- sptt
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- pole triple
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000012360 testing method Methods 0.000 claims abstract description 106
- 238000009434 installation Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 230000004807 localization Effects 0.000 description 6
- 102100021934 Cyclin-D1-binding protein 1 Human genes 0.000 description 4
- 101000897488 Homo sapiens Cyclin-D1-binding protein 1 Proteins 0.000 description 4
- 101000651236 Homo sapiens NCK-interacting protein with SH3 domain Proteins 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 102100037922 Disco-interacting protein 2 homolog A Human genes 0.000 description 3
- 101000805876 Homo sapiens Disco-interacting protein 2 homolog A Proteins 0.000 description 3
- 101000955093 Homo sapiens WD repeat-containing protein 3 Proteins 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 206010037660 Pyrexia Diseases 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Abstract
The utility model discloses a semiconductor device detector which comprises a testing plate and a semiconductor device socket into which a semiconductor device is inserted. The semiconductor device socket comprises multiple jacks. The testing plate comprises multiple single-pole triple-throw switches in one to one correspondence with the jacks and high-level input ports in one to one correspondence with the singe-pole triple-throw switches. The fixed ends of the singe-pole triple-throw switches are respectively connected with the jacks of the semiconductor device socket in one to one correspondence, the first switching end of each single-pole triple-throw switch is connected with a power supply of the device, the third switching end of each single-pole triple-throw switch is grounded, the second switching end of each single-pole triple-throw switch is hung in the air, and the fixed ends of the singe-pole triple-throw switches are also respectively connected with the high-level input ports in one to one correspondence. The semiconductor device detector greatly simplifies the testing process of the semiconductor device, and improves the detection efficiency and accuracy.
Description
Technical field
The utility model relates to electron device testing technical field, refers to especially a kind of semiconductor device testing apparatus.
Background technology
Along with SIC (semiconductor integrated circuit) integrated level or scale sharply increase, integrated circuit is to the future development of hachure, Miltilayer wiring structure.Chip metallization lines are more and more thinner, and spacing is more and more narrow, and density is more and more higher.Meanwhile, in device use procedure, due to reasons such as current density increase, electric field enhancings, cause the inefficacy of integrated circuit often to occur in the active area of inner sandwich construction lower floor.
For the failure analysis of chip, be main mainly with optical microscope; And electric leakage was lost efficacy for fever type, can adopt liquid crystal hot spot detecting method locate failure point.In the time that temperature rising exceedes liquid crystal material phase transition temperature, liquid crystal becomes isotropic liquid from anisotropy, carrys out heat generating spot in detection chip by observing liquid crystal phase height under crossed polarized light, and then definite failure site.
But, in the time utilizing liquid crystal phase transition to carry out failpoint detection and localization, need to power up measured device relevant pins.For example, in the time that cmos device is added to electrical testing, its idle input pin can not be unsettled,, or connects high level (as " power supply ") that is, otherwise connect low level (as " "); Meanwhile, its output pin needs unsettled.For described cmos device feature, when cmos device is carried out to failpoint detection and localization, need to carry out wiring to relevant pins, and test site is because wire is messy too much and very, in addition, frequent wiring is also easy to occur wiring error.
Utility model content
In view of this, the purpose of this utility model is to propose a kind of semiconductor device testing apparatus, has greatly simplified device detection process, has improved detection efficiency and accuracy rate.
The semiconductor device testing apparatus providing based on above-mentioned purpose the utility model, comprises test board and the semiconductor devices socket for the device under test of pegging graft; Described semiconductor devices socket comprises multiple jacks; Described test board comprises and described jack multiple single-pole triple-throw (SPTT) switches one to one, and with described multiple single-pole triple-throw (SPTT) switches high level input port one to one; Connect one to one the respectively jack of described semiconductor devices socket of the stiff end of described each single-pole triple-throw (SPTT) switch, the first switch terminal of described each single-pole triple-throw (SPTT) switch is connected with device power supply, the 3rd switch terminal ground connection of described each single-pole triple-throw (SPTT) switch; Wherein:
The second switch terminal of described each single-pole triple-throw (SPTT) switch is unsettled, and the stiff end of described each single-pole triple-throw (SPTT) switch connects and its described high level input port one to one;
Or the second switch terminal of described each single-pole triple-throw (SPTT) switch connects and its described high level input port one to one.
In some embodiments, described test board comprises test panel; On described test panel, be provided with the plug-in strip of power supply socket, ground connection socket, described high level input port, described each single-pole triple-throw (SPTT) switch; The first switch terminal of described each single-pole triple-throw (SPTT) switch is connected with device power supply by described power supply socket; The 3rd switch terminal of described each single-pole triple-throw (SPTT) switch is by described ground connection socket ground connection; Described high level input port is for selectivity access test high level; The plug-in strip of described each single-pole triple-throw (SPTT) switch connects different switch terminal for switching as required.
In some embodiments, described proving installation also comprises test adapter; The described semiconductor devices socket for the device under test of pegging graft is arranged at described test adapter, and described test adapter also comprises the first connector socket; Connect one to one each jack of described semiconductor devices socket of each jack of described the first connector socket; On described test board, be provided with the second connector socket, described and semiconductor devices receptacle sockets be connect one to one each jack of described the second connector socket of the stiff end of multiple single-pole triple-throw (SPTT) switches one to one; Described the first connector socket is electrically connected by connecting line with described the second connector socket; Make connect one to one the respectively jack of described semiconductor devices socket of the stiff end of described each single-pole triple-throw (SPTT) switch.
In some embodiments, described semiconductor devices socket comprises 28 jacks, and described test board comprises 28 single-pole triple-throw (SPTT) switches.
As can be seen from above, described device testing apparatus, by designing semiconductor device socket and test circuit, make its pass through single-pole triple-throw (SPTT) switch can be selectively with power supply, be connected, or select centre tap unsettled or connect other power supplys, while making to utilize liquid crystal phase transition to carry out failpoint detection and localization, no longer need interim connection line, but directly measured device is inserted to test adapter.And, in the time that the pin of device can not be unsettled, as long as toggle switch, be placed on and connect the switch terminal of power supply or the switch terminal of ground connection, and in the time that needs are unsettled, toggle switch, be placed on unsettled switch terminal, it is convenient especially to use, and controls also convenient, flexible especially, can select at any time the powering state of the each pin of device under test; Test site is cleaner and tidier, is also not easy to occur wiring error.
Described device testing apparatus, for the specific demand of semiconductor device failure point liquid crystal detection and localization, multichannel control loop is integrated in a pick-up unit, simultaneously, by unique test circuit design, use single-pole triple-throw (SPTT) switch, to the independent control of each pin powering state, realization and power supply, or input end be connected (unsettled or input high level).
Further, described device testing apparatus has configured 28 control channels, by connecting line, two 28 line DIP sockets is connected; The jack of described DIP socket is corresponding one by one with the single-pole triple-throw (SPTT) switch on described test panel, and arrangement mode is consistent.Utilize the single-pole triple-throw (SPTT) switch on test panel, each road port on DIP socket can realization with power supply, or input end be connected (unsettled or input high level).
Accompanying drawing explanation
The semiconductor device testing apparatus circuit theory schematic diagram that Fig. 1 provides for embodiment of the utility model;
The test board circuit theory schematic diagram of the semiconductor device testing apparatus that Fig. 2 provides for another embodiment of the utility model;
The test adapter schematic diagram of the semiconductor device testing apparatus that Fig. 3 provides for another embodiment of the utility model;
The test panel schematic diagram of the semiconductor device testing apparatus that Fig. 4 provides for another embodiment of the utility model.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the utility model is further described.
An embodiment of the present utility model provides a kind of semiconductor device testing apparatus, comprises test board and the semiconductor devices socket for the device under test of pegging graft; Described semiconductor devices socket comprises multiple jacks; Described test board comprises and described jack multiple single-pole triple-throw (SPTT) switches one to one, and with described multiple single-pole triple-throw (SPTT) switches high level input port one to one; Connect one to one the respectively jack of described semiconductor devices socket of the stiff end of described each single-pole triple-throw (SPTT) switch, the first switch terminal of described each single-pole triple-throw (SPTT) switch is connected with device power supply, the 3rd switch terminal ground connection of described each single-pole triple-throw (SPTT) switch; Wherein:
The second switch terminal of described each single-pole triple-throw (SPTT) switch is unsettled, and the stiff end of described each single-pole triple-throw (SPTT) switch connects and its described high level input port one to one;
Or the second switch terminal of described each single-pole triple-throw (SPTT) switch connects and its described high level input port one to one.
It should be noted that, in the utility model embodiment, the statement of all uses " first " and " second " is all in order to distinguish two non-identical entities of same names or non-identical parameter, visible " first " " second " only convenience in order to explain, should not be construed as the restriction to the utility model embodiment, subsequent embodiment is explanation no longer one by one to this.
With reference to accompanying drawing 1, the semiconductor device testing apparatus circuit theory schematic diagram providing for embodiment of the utility model.
Described semiconductor device testing apparatus, comprises test board and the semiconductor devices socket for the device under test of pegging graft; Described semiconductor devices socket comprises multiple jacks; Described test board comprises and described jack multiple single-pole triple-throw (SPTT) switch (K1, K2, K3, K4 one to one ... K27, K28), and with described multiple single-pole triple-throw (SPTT) switches high level input port (IN1, IN2, IN3, IN4 one to one ... IN27, IN28); Described each single-pole triple-throw (SPTT) switch (K1, K2, K3, K4 ... K27, K28) connect one to one the respectively jack of described semiconductor devices socket of stiff end, described each single-pole triple-throw (SPTT) switch (K1, K2, K3, K4 ... K27, K28) the first switch terminal be connected with device power supply, described each single-pole triple-throw (SPTT) switch (K1, K2, K3, K4 ... K27, K28) the 3rd switch terminal ground connection; Wherein:
Described each single-pole triple-throw (SPTT) switch (K1, K2, K3, K4 ... K27, K28) the second switch terminal unsettled, and described each single-pole triple-throw (SPTT) switch (K1, K2, K3, K4 ... K27, K28) stiff end connect and its described high level input port (IN1, IN2, IN3, IN4 one to one ... IN27, IN28).
With reference to accompanying drawing 2 to 4, be respectively test board circuit theory schematic diagram, test adapter schematic diagram and the test panel schematic diagram of the semiconductor device testing apparatus that another embodiment of the utility model provides.
Described semiconductor device testing apparatus, comprises test board and test adapter 1:
The described semiconductor devices socket for the device under test of pegging graft is arranged at described test adapter 1, and described test adapter 1 also comprises the first connector socket DIP1; Described semiconductor devices socket and the first connector socket DIP1 include 28 jacks; Connect one to one each jack of described semiconductor devices socket of each jack of described the first connector socket DIP1.
Described test board comprises and described semiconductor devices receptacle sockets 28 single-pole triple-throw (SPTT) switches (K1, K2, K3, K4 one to one ... K27, K28), and with described 28 single-pole triple-throw (SPTT) switches high level input port (IN1, IN2, IN3, IN4 one to one ... IN27, IN28); On described test board, be provided with the second connector socket DIP2, described and semiconductor devices receptacle sockets be connect one to one each jack of described the second connector socket DIP2 of the stiff end of 28 single-pole triple-throw (SPTT) switches one to one; Described the first connector socket DIP1 is electrically connected by connecting line with described the second connector socket DIP2; Make connect one to one the respectively jack of described semiconductor devices socket of the stiff end of described each single-pole triple-throw (SPTT) switch.
Described test board also comprises test panel 2; On described test panel 2, be provided with power supply socket V
cC, ground connection socket GND, described high level input port (IN1, IN2, IN3, IN4 ... IN27, IN28), described each single-pole triple-throw (SPTT) switch (K1, K2, K3, K4 ... K27, K28) plug-in strip; The first switch terminal of described each single-pole triple-throw (SPTT) switch is by described power supply socket V
cCbe connected with device power supply; The 3rd switch terminal of described each single-pole triple-throw (SPTT) switch is by described ground connection socket GND ground connection; Described high level input port is for selectivity access test high level; The plug-in strip of described each single-pole triple-throw (SPTT) switch connects different switch terminal for switching as required.
The second switch terminal of described each single-pole triple-throw (SPTT) switch is unsettled, and the stiff end of described each single-pole triple-throw (SPTT) switch connects and its described high level input port one to one.
The liquid crystal Hot spots detection process of semiconductor devices to be measured comprises:
First, drip liquid crystal at described semiconductor device surface to be measured, make liquid crystal cover described semiconductor device surface to be measured.
Then, device under test is inserted to described semiconductor devices socket, by described power supply socket V
cCaccess power supply, by described ground connection socket GND ground connection.
Then, the pin of test as required, to described high level input port access high level that should pin.
Subsequently, the plug-in strip correspondence of described single-pole triple-throw (SPTT) switch is pushed to the switch terminal that it need to connect.
Finally, open power supply and high level input power, the corresponding pin of device under test is corresponding access power supply, ground connection, unsettled or access high level, thereby starts the detection of semiconductor device chip to be measured.
As can be seen from above, described semiconductor device testing apparatus, by designing semiconductor device socket and test circuit, make its pass through single-pole triple-throw (SPTT) switch can be selectively with power supply, be connected, or select centre tap unsettled or connect other power supplys, while making to utilize liquid crystal phase transition to carry out failpoint detection and localization, no longer need interim connection line, but directly measured device is inserted to test adapter.And, in the time that the pin of device can not be unsettled, as long as toggle switch, be placed on and connect the switch terminal of power supply or the switch terminal of ground connection, and in the time that needs are unsettled, toggle switch, be placed on unsettled switch terminal, it is convenient especially to use, and controls also convenient, flexible especially, can select at any time the powering state of the each pin of device under test; Test site is cleaner and tidier, is also not easy to occur wiring error.
Described semiconductor device testing apparatus, for the specific demand of semiconductor device chip failpoint liquid crystal detection and localization, multichannel control loop is integrated in a pick-up unit, simultaneously, by unique test circuit design, use single-pole triple-throw (SPTT) switch, to the independent control of each pin powering state, realization and power supply, or input end be connected (unsettled or input high level).
Further, described semiconductor device testing apparatus has configured 28 control channels, by connecting line, two 28 line DIP sockets is connected; The jack of described DIP socket is corresponding one by one with the single-pole triple-throw (SPTT) switch on described test panel, and arrangement mode is consistent.Utilize the single-pole triple-throw (SPTT) switch on test panel, each road port on DIP socket can realization with power supply, or input end be connected (unsettled or input high level).
Further, described test adapter is connected with test board by connecting line, as long as carry out the design of test adapter for different size device separately, can make the device of different size that different test adapters can corresponding be set, and only adopt same test board to test, greatly save units test cost.
It needs to be noted, each splicing ear (for example, stiff end, the first switch terminal etc.) of described single-pole triple-throw (SPTT) switch is only a representation noun, does not represent with similar other nouns of this terminal function and does not belong to protection content of the present utility model; And, if desired, can and understand meaning and the function of each splicing ear of described single-pole triple-throw (SPTT) switch in conjunction with instructions word with reference to accompanying drawing.
In addition, the second switch terminal of described each single-pole triple-throw (SPTT) switch can directly connect and its described high level input port one to one, the stiff end of described each single-pole triple-throw (SPTT) switch need not connect this high level input port more simultaneously, also can reach technique effect of the present utility model; Therefore protection domain of the present utility model should not only limit to the technical scheme in described embodiment.
In addition; described semiconductor device testing apparatus can also be set directly at described semiconductor devices socket on described test board; thereby save the process that connector socket is set, therefore, protection domain of the present utility model should not only limit to the technical scheme in described embodiment.
Have again; 28 control channels in described embodiment, are designed; those skilled in the art are easy to expect; adopt more or less control channel can complete the detection to different model device; therefore protection domain of the present utility model should be limited in to 28 control channels, the number of certain single-pole triple-throw (SPTT) switch etc. also can correspondingly be adjusted.
Finally, in described embodiment, this semiconductor device testing apparatus is the liquid crystal Hot spots detection for semiconductor device chip, those skilled in the art are easy to expect, the technical solution of the utility model also can be used for the units test of other type, therefore, application of the present utility model should be confined to liquid crystal Hot spots detection.
Those of ordinary skill in the field are to be understood that: the foregoing is only specific embodiment of the utility model; be not limited to the utility model; all within spirit of the present utility model and principle; any modification of making, be equal to replacement, improvement etc., within all should being included in protection domain of the present utility model.
Claims (4)
1. a semiconductor device testing apparatus, is characterized in that, comprises test board and the semiconductor devices socket for the device under test of pegging graft; Described semiconductor devices socket comprises multiple jacks; Described test board comprises and described jack multiple single-pole triple-throw (SPTT) switches one to one, and with described multiple single-pole triple-throw (SPTT) switches high level input port one to one; Connect one to one respectively each jack of described semiconductor devices socket of the stiff end of described each single-pole triple-throw (SPTT) switch, the first switch terminal of described each single-pole triple-throw (SPTT) switch is connected with device power supply, the 3rd switch terminal ground connection of described each single-pole triple-throw (SPTT) switch; Wherein:
The second switch terminal of described each single-pole triple-throw (SPTT) switch is unsettled, and the stiff end of described each single-pole triple-throw (SPTT) switch connects and its described high level input port one to one;
Or the second switch terminal of described each single-pole triple-throw (SPTT) switch connects and its described high level input port one to one.
2. semiconductor device testing apparatus according to claim 1, is characterized in that, described test board comprises test panel; On described test panel, be provided with the plug-in strip of power supply socket, ground connection socket, described high level input port, described each single-pole triple-throw (SPTT) switch; The first switch terminal of described each single-pole triple-throw (SPTT) switch is connected with device power supply by described power supply socket; The 3rd switch terminal of described each single-pole triple-throw (SPTT) switch is by described ground connection socket ground connection; Described high level input port is for selectivity access test high level; The plug-in strip of described each single-pole triple-throw (SPTT) switch connects different switch terminal for switching as required.
3. semiconductor device testing apparatus according to claim 2, is characterized in that, described proving installation also comprises test adapter; The described semiconductor devices socket for the device under test of pegging graft is arranged at described test adapter, and described test adapter also comprises the first connector socket; Connect one to one each jack of described semiconductor devices socket of each jack of described the first connector socket; On described test board, be provided with the second connector socket, described and semiconductor devices receptacle sockets be connect one to one each jack of described the second connector socket of the stiff end of multiple single-pole triple-throw (SPTT) switches one to one; Described the first connector socket is electrically connected by connecting line with described the second connector socket; Make connect one to one the respectively jack of described semiconductor devices socket of the stiff end of described each single-pole triple-throw (SPTT) switch.
4. according to the semiconductor device testing apparatus described in claims 1 to 3 any one, it is characterized in that, described semiconductor devices socket comprises 28 jacks, and described test board comprises 28 single-pole triple-throw (SPTT) switches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420009043.1U CN203705599U (en) | 2014-01-07 | 2014-01-07 | Semiconductor device detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420009043.1U CN203705599U (en) | 2014-01-07 | 2014-01-07 | Semiconductor device detector |
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| CN203705599U true CN203705599U (en) | 2014-07-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420009043.1U Expired - Lifetime CN203705599U (en) | 2014-01-07 | 2014-01-07 | Semiconductor device detector |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108944421A (en) * | 2018-05-30 | 2018-12-07 | 谢鑫钰 | A kind of truck oil tank anti-theft lock system |
| CN109490738A (en) * | 2018-11-05 | 2019-03-19 | 南京中电熊猫晶体科技有限公司 | A kind of measuring device of crystal oscillator diode characteristic |
| CN110045259A (en) * | 2019-03-28 | 2019-07-23 | 武汉市毅联升科技有限公司 | A kind of LD-TO device aging system |
| CN111999626A (en) * | 2020-08-02 | 2020-11-27 | 上海精密计量测试研究所 | Configurable I-V characteristic testing device and testing method thereof for semiconductor device |
| CN113484735A (en) * | 2021-07-30 | 2021-10-08 | 锐石创芯（深圳）科技有限公司 | Chip test gating module and chip test system |
-
2014
- 2014-01-07 CN CN201420009043.1U patent/CN203705599U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108944421A (en) * | 2018-05-30 | 2018-12-07 | 谢鑫钰 | A kind of truck oil tank anti-theft lock system |
| CN109490738A (en) * | 2018-11-05 | 2019-03-19 | 南京中电熊猫晶体科技有限公司 | A kind of measuring device of crystal oscillator diode characteristic |
| CN110045259A (en) * | 2019-03-28 | 2019-07-23 | 武汉市毅联升科技有限公司 | A kind of LD-TO device aging system |
| CN110045259B (en) * | 2019-03-28 | 2021-01-05 | 武汉市毅联升科技有限公司 | LD-TO device aging system |
| CN111999626A (en) * | 2020-08-02 | 2020-11-27 | 上海精密计量测试研究所 | Configurable I-V characteristic testing device and testing method thereof for semiconductor device |
| CN113484735A (en) * | 2021-07-30 | 2021-10-08 | 锐石创芯（深圳）科技有限公司 | Chip test gating module and chip test system |
| CN113484735B (en) * | 2021-07-30 | 2022-11-08 | 锐石创芯(深圳)科技股份有限公司 | Chip test gating module and chip test system |
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Granted publication date: 20140709 |