CN106199393A - A kind of fault test set and fault detection method - Google Patents
A kind of fault test set and fault detection method Download PDFInfo
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- CN106199393A CN106199393A CN201610525246.XA CN201610525246A CN106199393A CN 106199393 A CN106199393 A CN 106199393A CN 201610525246 A CN201610525246 A CN 201610525246A CN 106199393 A CN106199393 A CN 106199393A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31717—Interconnect testing
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Abstract
The invention discloses a kind of fault test set and fault detection method, including: emulator, for downloading the first test program；Flash chip, is connected with described emulator, is used for storing described first test program；PLD, is connected with described flash chip；Wherein, when described fault test set and a digital processing unit connect, described fault test set is read from described flash chip by described PLD and is run described first test program, obtain the pin duty of the pin of described digital processing unit, to determine whether described digital processing unit exists fault according to described pin duty.The technical scheme provided by the present invention, complex for solving the process fault detection of digital processing unit in prior art.
Description
Technical field
The present invention relates to field of equipment failure detection, particularly to a kind of fault test set and fault detection method.
Background technology
Along with the development of science and technology, the appearance in succession of LSI, VLSI, ULSI, silicon Single-Chip Integration degree constantly carries
Height, the requirement to integrated antenna package is more strict, and the great increase of I/O number of pins, power consumption is also with increase, in order to meet development
Needs, on the basis of original encapsulation kind, add again new kind one BGA Package.
In prior art, the fault detection method to the chip with BGA Package, is to take off chip to weigh one by one
Weldering, if or faulty, change device the most one by one, but, take and chip of rewelding is all the most complicated process, simultaneously to printing
The damage of plate is bigger.
Visible, in prior art, the process fault detection of digital processing unit is complex.
Summary of the invention
The embodiment of the present invention provides a kind of fault test set and fault detection method, is used for solving numeral in prior art
The technical problem that the process fault detection of processing module is complex, to simplify answering of the process fault detection of digital processing unit
The technique effect of miscellaneous degree.
On the one hand, the embodiment of the present application provides a kind of fault test set, including:
Emulator, for downloading the first test program；
Flash chip, is connected with described emulator, is used for storing described first test program；
PLD, is connected with described flash chip；
Wherein, when described fault test set and a digital processing unit connect, described fault test set passes through institute
State PLD read from described flash chip and run described first test program, obtain described digital processing dress
According to described pin duty, the pin duty of the pin put, to determine whether described digital processing unit exists event
Barrier.
Optionally, described fault test set also includes:
Connecting interface, be connected with described PLD by bus, wherein, described fault test set passes through institute
State connection interface to be connected with described digital processing unit.
Optionally, described PLD is used for:
Obtain the pin duty of described connection interface；
Determine whether described pin duty is to preset pin duty；
If it has not, the first signal then generated, described first signal is for characterizing the event that described digital processing unit exists
Barrier.
Optionally, described fault test set also includes:
Processor, is connected with described PLD, for processing described first signal, obtains described number
The fault message of word processing device.
Optionally, described fault test set also includes:
Mainboard, is connected between described emulator and described processor, is used for obtaining described fault message.
Optionally, described fault test set also includes:
Electrical level transferring chip, is connected between described processor and described mainboard, so that described processor and described mainboard
Between can be carried out data transmission by asynchronous transmission standard interface.
Optionally, described fault test set also includes:
USB interface, is connected between described processor and described mainboard, so that energy between described processor and described mainboard
Enough carry out data transmission based on usb protocol.
Optionally, described fault test set also includes:
Display device, is connected with described mainboard, is used for showing described fault message.
On the other hand, the embodiment of the present application also provides for a kind of digital processing unit, including:
Connect slot, for being connected with fault test set；
Processor, connects with the described slot that is connected；
Wherein, when described digital processing unit is connected with described fault test set by described connection slot, download
And run the first test program, control each input/input port on the connection interface corresponding with described connection slot successively
Level value is according to prefixed time interval saltus step.
On the other hand, the embodiment of the present application also provides for a kind of fault detection method, is applied to fault test set, when described
When fault test set and a digital processing unit connect, described method includes:
Described fault test set downloads the first test program by emulator, and is stored in flash chip；
Described fault test set is read from described flash chip by PLD and is run described first
Test program, obtains the pin duty of the pin of described digital processing unit, to determine according to described pin duty
Whether described digital processing unit exists fault.
Optionally, read at described fault test set from described flash chip by PLD and run
After described first test program, described method also includes:
Based on described pin duty, determine whether described pin duty is to preset pin duty；
If it has not, then there is the first signal of fault for characterizing described digital processing unit in generation.
Optionally, described if it has not, the first signal of then generating, described first signal is used for characterizing described digital processing
After the fault that device exists, described method also includes:
Described first signal is processed by the processor of described fault test set, obtains described digital processing unit
Fault message.
Optionally, described first signal is processed by the processor at described fault test set, obtains described
After the fault message of digital processing unit, described method also includes:
Described fault message is shown by the display device of described fault test set.
On the other hand, the embodiment of the present application also provides for a kind of information processing method, is applied to a digital processing unit, works as institute
When stating digital processing unit and fault test set connection, described method includes:
Download and run the first test program, each defeated to control successively on the connection interface corresponding with described connection slot
Enter/level value of input port is according to prefixed time interval saltus step.
One, due to the technical scheme in the embodiment of the present application, fault test set includes: emulator, for download first
Test program；Flash chip, is connected with described emulator, is used for storing described first test program；PLD, with
Described flash chip connects；Wherein, when described fault test set and a digital processing unit connect, described fault detect sets
For being read from described flash chip by described PLD and running described first test program, obtain described number
Whether the pin duty of the pin of word processing device, determine described digital processing unit according to described pin duty
There is fault.I.e. will not be as in prior art, the fault detect to digital processing unit, need the chip of digital processing unit
Take off and reweld one by one, spend the time longer.And in the technical program, by the programmable logic device in fault test set
The first test program that part runs, reads the pin duty of the pin of digital processing unit, to determine that digital processing fills
The fault put, thus avoid taking off chip rewelding, simplify whole operating process, thus it is possible to effectively solve existing
The technical problem of the complexity of the process fault detection of digital processing unit in technology, and then reach to simplify digital processing unit
The technique effect of complexity of process fault detection.
Two, due to the technical scheme in the embodiment of the present application, between processor and mainboard, level conversion core can be passed through
Sheet connects, so that can be carried out data transmission by asynchronous transmission standard interface between described processor and described mainboard.Or it is logical
Cross USB interface to connect, so that can carry out data transmission based on usb protocol between described processor and described mainboard.I.e. at this
In technical scheme, the diversity communication mode between processor and mainboard, those of ordinary skill in the art can be according to actual need
Select, and then reached the technique effect of the use scene of abundant fault test set.
Accompanying drawing explanation
The structural representation of a kind of fault test set that Fig. 1 provides for the embodiment of the present application one；
The structural representation of a kind of digital processing unit that Fig. 2 provides for the embodiment of the present application two；
The structural representation of a kind of fault detection method that Fig. 3 provides for the embodiment of the present application three.
Detailed description of the invention
The embodiment of the present invention provides a kind of fault test set and fault detection method, is used for solving numeral in prior art
The technical problem that the process fault detection of processing means is complex, to reach to simplify the process fault detection of digital processing unit
The technique effect of complexity.
Technical scheme in the embodiment of the present application is for solving above-mentioned technical problem, and general thought is as follows:
Emulator, for downloading the first test program；
Flash chip, is connected with described emulator, is used for storing described first test program；
PLD, is connected with described flash chip；
Wherein, when described fault test set and a digital processing unit connect, described fault test set passes through institute
State PLD read from described flash chip and run described first test program, to determine described digital processing
Whether device exists fault.
By technique scheme, fault test set includes: emulator, for downloading the first test program；Flash memory core
Sheet, is connected with described emulator, is used for storing described first test program；PLD, with described flash chip even
Connect；Wherein, when described fault test set and a digital processing unit connect, described fault test set is compiled by described
Journey logical device reads from described flash chip and runs described first test program, to determine that described digital processing unit is
No there is fault.I.e. will not be as in prior art, the fault detect to digital processing unit, need the core of digital processing unit
Sheet is taken off and is rewelded one by one, spends the time longer.And in the technical program, by the FPGA in fault test set
The first test program that device runs determines the fault of digital processing unit, thus avoids taking off chip rewelding, letter
Change whole operating process, thus it is possible to effectively solve the complexity of the process fault detection of digital processing unit in prior art
The technical problem of degree, and then reach to simplify the technique effect of the complexity of the process fault detection to digital processing unit.
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under not making creative work premise, broadly falls into the scope of protection of the invention.
Embodiment one
Refer to Fig. 1, the embodiment of the present application one provides a kind of fault test set, including:
Emulator 10, for downloading the first test program；
Flash chip 11, is connected with described emulator 10, is used for storing described first test program；
PLD 12, is connected with described flash chip 11；
Wherein, when described fault test set and a digital processing unit connect, described fault test set passes through institute
State PLD read from described flash chip and run described first test program, to determine described digital processing
Whether device exists fault.
In the embodiment of the present application, emulator is connected between mainboard and flash chip, and emulator is specifically as follows BMD and imitates
True device or be JTAG emulator.During implementing, if emulator is as a example by JTAG emulator, JTAG emulator and master
Then connected by USB cable between plate, for the first test program is downloaded in flash chip.
Further, in the embodiment of the present application, jtag interface is four lines: TMS, TCK, TDI, TDO, and wherein, TCK is test
Clock inputs；TDI is test data input, and data input jtag interface by TDI pin；TDO is test data output, data
Exported from jtag interface by TDO pin；TMS is that test pattern selects, and TMS is used for arranging jtag interface, and to be in certain specific
Test pattern.Connected by four lines between JTAG emulator and flash chip in the embodiment of the present application, same flash chip
And be also to be connected by four lines between PLD.
In the embodiment of the present application, PLD be specifically as follows CPLD CPLD or
FPGA.In the embodiment of the present application, PLD is as a example by FPGA.And when PLD is specially FPGA
Time, the emulation to PLD, debugging and programming can be completed at bottom by four signals of above-mentioned four line transmission,
So that FPGA can run application program, and then complete the fault detect to digital processing unit.
Further, in the embodiment of the present application, described fault test set also includes:
Connecting interface, be connected with described PLD by bus, wherein, described fault test set passes through institute
State connection interface to be connected with described digital processing unit.
In the embodiment of the present application, fault test set is connected with digital processing unit by connecting interface.As: specifically
During realization, connect interface and be specifically as follows 1,2 or 3, or be other quantity, those of ordinary skill in the art
Depending on can be according to the specific design demand of (Printed Circuit Board, PCB) printed circuit board, implement in the application
Example is not especially limited.
In the embodiment of the present application, as a example by an interface, concrete, such as: it is corresponding that interface 1 is connected to FPGA by bus
I/O pin on.
After fault test set is connected on digital processing unit, then from the electricity being connected digital processing unit
On subset, compiled test program 2 is downloaded in digital processing unit, accordingly, by JTAG emulator by compiled
Test program 1 be downloaded in flash chip so that after system electrification, digital processing unit testing results program 2
Meanwhile, FPGA testing results program 2.
In the embodiment of the present application, test program 2 is for controlling the N number of input/output terminal on described connection interface successively
The level value of each input/input port in Kou is according to prefixed time interval saltus step.So that FPGA is in testing results program
1, by the duty of bus synchronous scanning pin 1 to bus pin 220, with the event of discriminating digit processing means respective chip
Barrier.
In the embodiment of the present application, described PLD is used for:
Obtain the pin duty of described connection interface；
Determine whether described pin duty is to preset pin duty；
If it has not, the first signal then generated, described first signal is for characterizing the event that described digital processing unit exists
Barrier.
In the embodiment of the present application, the pin duty connecting interface is specifically as follows the magnitude of voltage of pin output, or
The low and high level value that person exports for pin, or be other state, it is not especially limited in the embodiment of the present application.
During implementing, owing to digital processing unit comprising power supply chip and by the chip of BGA package,
As: DSP, FPGA, the most respectively the process fault detection of this two classes chip is illustrated.
The first kind: the process fault detection of power supply chip.
In the embodiment of the present application, the pin duty connecting interface that FPGA obtains, such as: the magnitude of voltage of output is 5V
Or 0V, during implementing, PFGA can carry out analog digital conversion to the signal received, such as: 5V voltage signal is converted into number
Word signal is then 255, and it is then 0 that 0V voltage signal is converted into digital signal.Accordingly, in the embodiment of the present application, pin is preset
Duty corresponding digital signals is 255.
During implementing, if it is 0 that PFGA carries out the digital signal after analog digital conversion, it not to preset pin work
State 255, the most then judge that power supply chip exists fault, generates the first signal such as: 01, fe the most accordingly.
Equations of The Second Kind: with the process fault detection of the chip of BGA form encapsulation.
In the embodiment of the present application, for the chip encapsulated by BGA form, then directly defeated by detecting corresponding pin
Whether the low and high level gone out is to preset low and high level.Concrete, such as: pin 2 output level value of detection is low level, for non-pre-
If level, high level, so after all pins detect, generate the first signal the most accordingly such as: 02, fd；Or 03, fc.
Further, in the embodiment of the present application, described fault test set also includes:
Processor, is connected with described PLD, for processing described first signal, obtains described number
The fault message of word processing device.
During implementing, processor is specifically as follows ARM, AMD or is other processor, the common skill in this area
Art personnel can be set according to actual needs, is not especially limited in the embodiment of the present application.
In the embodiment of the present application, processor, as a example by ARM, receives and dispatches number by USB communication protocol between ARM and FPGA
According to, FPGA is by the first signal, such as: 01, fe；02, fd；Or 03, fc sends to ARM, ARM then judge it is numeral according to the first signal
There is fault in which chip block in processing means, and has several pin to have problems, such as: 01, fe characterizes power supply chip, has 1
Individual pin has problems；02, fd characterizes DSP, has 2 pin existing problems etc..
During implementing, fault type is broadly divided into three classes, carries out this three classes fault type in detail separately below
Describe in detail bright.
The first fault type: the chip failure of digital processing unit.
One, fault test set cannot scan the power supply signal in respective bus, then show the electricity of digital processing unit
Source chip lost efficacy；
Two, cannot download in digital signal processing module at test program 2, then show that the flash chip of digital processing unit loses
Effect；
Three, when the FPGA bus of fault test set cannot scan corresponding pulse signal, then digital processing is shown
The fpga chip of device lost efficacy；
Four, when the dsp bus of fault test set cannot scan corresponding pulse signal, then show that digital processing fills
The DSP failure put.
The second fault type: digital processing unit chip even weldering.
One, fault test set detects load current overload, and relay disconnects digital processing unit power supply, then show number
The even weldering of the power supply chip of word processing device；
Two, cannot download in digital processing unit when test program 2, and with relay module current overload, then show
The even weldering of the flash chip of digital processing unit；
Three, when in the FPGA bus of fault test set synchronization scan multiple pulse signal, then show FPGA core
Sheet even weldering；
Four, when synchronization scans multiple pulse signal on the dsp bus of fault test set, then DSP core is shown
Sheet even weldering.
The third fault type: digital processing unit chip rosin joint.
One, fault test set bus cannot scan corresponding power supply signal, after firmly pressing power module gently, always
Line scanning is normal, then show power supply chip rosin joint；
Two, test program 2 cannot download in digital processing unit, and after firmly pressing flash chip gently, program is normal
Download, then show flash chip rosin joint；
When three, having scanned indivedual pin pulse-free signal in the FPGA bus of fault test set, then show FPGA core
Sheet rosin joint；
Four, scanned indivedual pin pulse-free signal on the dsp bus of fault test set, then shown that dsp chip is empty
Weldering.
Further, in the embodiment of the present application, described fault test set also includes:
Mainboard, is connected between described emulator and described processor, is used for obtaining described fault message.
In the embodiment of the present application, mainboard is specifically including but not limited to, such as: cpu central processing unit, memory bar, video card,
Hard disk, power supply etc..After ARM determines the fault message of digital processing unit according to the first signal, then by corresponding fault
Information sends to mainboard, to be saved on the hard disk of mainboard.
In the embodiment of the present application, specifically there are two kinds of connected modes between mainboard and ARM, separately below both connected
Mode is described in detail.
The first connected mode, described fault test set also includes:
Electrical level transferring chip, is connected between described processor and described mainboard, so that described processor and described mainboard
Between can be carried out data transmission by asynchronous transmission standard interface.
During implementing, although ARM single-chip microcomputer has a function of serial communication, but the signal that single-chip microcomputer provides
The standard of level and RS232 is different, therefore, in the embodiment of the present application, also includes electrical level transferring chip, such as: MAX232 enters
Line level is changed, so that ARM can be by communicating between RS232 interface and mainboard.
The second connected mode, described fault test set also includes:
USB interface, is connected between described processor and described mainboard, so that energy between described processor and described mainboard
Enough carry out data transmission based on usb protocol.
During implementing, USB interface can also be passed through between ARM and mainboard, communicate based on usb protocol.
For above two implementation, those of ordinary skill in the art can select according to actual needs, implements in the application
Example is not especially limited.
Further, in the embodiment of the present application, described fault test set also includes:
Display device, is connected with described mainboard, is used for showing described fault message.
During implementing, fault test set also includes display device, for being shown by fault message in display
Checking for user in device, to process the fault detected, in the embodiment of the present application, display device passes through PCI-E
Interface is attached with mainboard.
In the embodiment of the present application, display device is specifically as follows LCD liquid crystal display screen or LED display, or is it
The display screen of its type, those of ordinary skill in the art can select, the most according to actual needs
Make concrete restriction.
Embodiment two
Refer to Fig. 2, the embodiment of the present application provides a kind of digital processing unit, including:
Connect slot 20, for being connected with fault test set；
Processor 21, connects with the described slot that is connected；
Wherein, when described digital processing unit is connected with described fault test set by described connection slot, download
And run the first test program, control each input/input port on the connection interface corresponding with described connection slot successively
Level value is according to prefixed time interval saltus step.
In the embodiment of the present application, digital processing unit specially comprises fpga chip, dsp processor, power supply chip
Processing means, and the chip in digital processing unit in the embodiment of the present application, such as: FPGA, DSP are all by BGA package side
Formula is packaged.
Further, digital processing unit specifically includes slot, for being connected with fault test set, implements in the application
In example, the number of slot is corresponding, such as with the quantity connecting interface: if only one of which connects interface, then the number of slot is also 1
Individual；If there being 2 to connect interface, then the number of slot is 2.
In the embodiment of the present application, fault test set is for detecting the fault of digital processing unit.Implementing
Cheng Zhong, when digital processing unit is connected with fault test set, the first test program is downloaded and run to digital processing unit,
In the embodiment of the present application, the first test program of operation is for controlling all of I/ mouth on the connection interface corresponding with connecting slot
It is initially high level, then according to prefixed time interval controls the level of a corresponding pin in bus by high level saltus step is
Low level, in the embodiment of the present application, prefixed time interval can be 100 milliseconds, 200 milliseconds or 300 milliseconds, or is other
Prefixed time interval, is not especially limited in the embodiment of the present application.
Accordingly, when the level of the most corresponding pin is low level by high level saltus step, also to control
Make this pin and be in low level one predetermined time period, such as: 200 milliseconds, 300 milliseconds or 400 milliseconds, or be other default time
Between length, those of ordinary skill in the art can be set according to actual needs, the most specifically limit
Fixed.
During implementing, successively from pin 1 to bus pin 220, run 220 digital processing unit program knots
Bundle, when digital processing unit testing results program 2, in system, FPGA testing results program 2 simultaneously, is scanned by bus synchronous
Pin 1 is to the duty of bus pin 220, with the fault of discriminating digit processing means respective chip.
Embodiment three
Refer to Fig. 3, the embodiment of the present application provides a kind of fault detection method, is applied to fault test set, when described
When fault test set and a digital processing unit connect, described method includes:
S301: described fault test set downloads the first test program by emulator, and is stored in flash chip；
S302: described fault test set is read by PLD and is run described from described flash chip
First test program, obtains the pin duty of the pin of described digital processing unit, with according to described pin duty
Determine whether described digital processing unit exists fault.
In the embodiment of the present application, step S301 is first carried out: described fault test set downloads first by emulator
Test program, and be stored in flash chip.
In the embodiment of the present application, emulator is specifically as follows BMD emulator or is JTAG emulator.Implementing
During, if emulator is as a example by JTAG emulator, when fault test set is connected with digital processing unit by connecting interface
Time, fault test set is downloaded the first test program by emulator JTAG and is stored in flash chip.
After execution of step S302, then perform step S302: described fault test set passes through programmable logic device
Part reads from described flash chip and runs described first test program, obtains the pin of the pin of described digital processing unit
According to described pin duty, duty, to determine whether described digital processing unit exists fault.
In the embodiment of the present application, PLD be specifically as follows CPLD CPLD or
FPGA.During implementing, if PLD is as a example by FPGA, at emulator, the first test program is downloaded to
After in flash chip, FPGA then reads from flash chip and runs the first test program.
In the embodiment of the present application, after described FPGA runs the first test program, described method also includes:
Obtain the pin duty of described connection interface；
Determine whether described pin duty is to preset pin duty；
If it has not, the first signal then generated, described first signal is for characterizing the event that described digital processing unit exists
Barrier.
In the embodiment of the present application, how PLD determines at numeral according to the pin duty of scanning
The fault that reason device exists.In the embodiment of the present application, the pin duty connecting interface is specifically as follows pin output
Magnitude of voltage, or the low and high level value for pin output, or be other state, the most specifically limit
Fixed.
During implementing, owing to digital processing unit comprising power supply chip and by the chip of BGA package,
As: DSP, FPGA, the most respectively the process fault detection of this two classes chip is illustrated.
The first kind: the process fault detection of power supply chip.
In the embodiment of the present application, the pin duty connecting interface that FPGA obtains, such as: the magnitude of voltage of output is 5V
Or 0V, during implementing, PFGA can carry out analog digital conversion to the signal received, such as: 5V voltage signal is converted into number
Word signal is then 255, and it is then 0 that 0V voltage signal is converted into digital signal.Accordingly, in the embodiment of the present application, pin is preset
Duty corresponding digital signals is 255.
During implementing, if it is 0 that PFGA carries out the digital signal after analog digital conversion, it not to preset pin work
State 255, the most then judge that power supply chip exists fault, generates the first signal such as: 01, fe the most accordingly.
Equations of The Second Kind: with the process fault detection of the chip of BGA form encapsulation.
In the embodiment of the present application, for the chip encapsulated by BGA form, then directly defeated by detecting corresponding pin
Whether the low and high level gone out is to preset low and high level.Concrete, such as: pin 2 output level value of detection is low level, for non-pre-
If level, high level, so after all pins detect, generate the first signal the most accordingly such as: 02, fd；Or 03, fc.
In the embodiment of the present application, after step S301, described method also includes:
Processor, is connected with described PLD, for processing described first signal, obtains described number
The fault message of word processing device.
In the embodiment of the present application, processor is specifically as follows ARM or AMD or is other type of processor, ability
Territory those of ordinary skill can be set according to actual needs, is not especially limited in the embodiment of the present application.
During implementing, processor, as a example by ARM, receives and dispatches number by USB communication protocol between ARM and FPGA
According to, FPGA is by the first signal, such as: 01, fe；02, fd；Or 03, fc sends to ARM, ARM then judge it is numeral according to the first signal
There is fault in which chip block in processing means, and has several pin to have problems, such as: 01, fe characterizes power supply chip, has 1
Individual pin has problems；02, fd characterizes DSP, has 2 pin existing problems etc..
During implementing, fault type is broadly divided into three classes, carries out this three classes fault type in detail separately below
Describe in detail bright.
The first fault type: the chip failure of digital processing unit.
One, fault test set cannot scan the power supply signal in respective bus, then show the electricity of digital processing unit
Source chip lost efficacy；
Two, cannot download in digital signal processing module at test program 2, then show that the flash chip of digital processing unit loses
Effect；
Three, when the FPGA bus of fault test set cannot scan corresponding pulse signal, then digital processing is shown
The fpga chip of device lost efficacy；
Four, when the dsp bus of fault test set cannot scan corresponding pulse signal, then show that digital processing fills
The DSP failure put.
The second fault type: digital processing unit chip even weldering.
One, fault test set detects load current overload, and relay disconnects digital processing unit power supply, then show number
The even weldering of the power supply chip of word processing device；
Two, cannot download in digital processing unit when test program 2, and with relay module current overload, then show
The even weldering of the flash chip of digital processing unit；
Three, when in the FPGA bus of fault test set synchronization scan multiple pulse signal, then show FPGA core
Sheet even weldering；
Four, when synchronization scans multiple pulse signal on the dsp bus of fault test set, then DSP core is shown
Sheet even weldering.
The third fault type: digital processing unit chip rosin joint.
One, fault test set bus cannot scan corresponding power supply signal, after firmly pressing power module gently, always
Line scanning is normal, then show power supply chip rosin joint；
Two, test program 2 cannot download in digital processing unit, and after firmly pressing flash chip gently, program is normal
Download, then show flash chip rosin joint；
When three, having scanned indivedual pin pulse-free signal in the FPGA bus of fault test set, then show FPGA core
Sheet rosin joint；
Four, scanned indivedual pin pulse-free signal on the dsp bus of fault test set, then shown that dsp chip is empty
Weldering.
In the embodiment of the present application, described first signal is processed by the processor at described fault test set, obtains
After taking the fault message of described digital processing unit, described method also includes:
Described fault message is shown by the display device of described fault test set.
During implementing, after processor determines the fault message of digital processing unit, then by fault message
Send to mainboard, and shown by the display device being connected with mainboard, consult for user, so to fault at
Reason.
Embodiment four
The embodiment of the present application example provides a kind of information processing method, is applied to a digital processing unit, at described numeral
When reason device and a fault test set connect, described method includes:
Download and run the first test program, each defeated to control successively on the connection interface corresponding with described connection slot
Enter/level value of input port is according to prefixed time interval saltus step.
In the embodiment of the present application, fault test set is for detecting the fault of digital processing unit.Implementing
Cheng Zhong, when digital processing unit is connected with fault test set, the first test program is downloaded and run to digital processing unit,
In the embodiment of the present application, the first test program of operation is initial for controlling all of I/ mouth on the interface corresponding with connecting slot
For high level, then according to it is low electricity by high level saltus step that prefixed time interval controls the level of a corresponding pin in bus
Flat, in the embodiment of the present application, prefixed time interval can be 100 milliseconds, 200 milliseconds or 300 milliseconds, or presets for other
Time interval, is not especially limited in the embodiment of the present application.
Accordingly, when the level of the most corresponding pin is low level by high level saltus step, also to control
Make this pin and be in low level one predetermined time period, such as: 200 milliseconds, 300 milliseconds or 400 milliseconds, or be other default time
Between length, those of ordinary skill in the art can be set according to actual needs, the most specifically limit
Fixed.
During implementing, successively from pin 1 to bus pin 220, run 220 digital processing unit program knots
Bundle, when digital processing unit testing results program 2, in system, FPGA testing results program 2 simultaneously, is scanned by bus synchronous
Pin 1 is to the duty of bus pin 220, with the fault of discriminating digit processing means respective chip.Thus avoid numeral
The chip of processing means is taken off and is rewelded one by one, and whole operating process is complex.
Said one in the embodiment of the present application or multiple technical scheme, at least have following one or more technology effect
Really:
One, due to the technical scheme in the embodiment of the present application, fault test set includes: emulator, for download first
Test program；Flash chip, is connected with described emulator, is used for storing described first test program；PLD, with
Described flash chip connects；Wherein, when described fault test set and a digital processing unit connect, described fault detect sets
For being read from described flash chip by described PLD and running described first test program, obtain described number
Whether the pin duty of the pin of word processing device, determine described digital processing unit according to described pin duty
There is fault.I.e. will not be as in prior art, the fault detect to digital processing unit, need the chip of digital processing unit
Take off and reweld one by one, spend the time longer.And in the technical program, by the programmable logic device in fault test set
The first test program that part runs, reads the pin duty of the pin of digital processing unit, to determine that digital processing fills
The fault put, thus avoid taking off chip rewelding, simplify whole operating process, thus it is possible to effectively solve existing
The technical problem of the complexity of the process fault detection of digital processing unit in technology, and then reach to simplify digital processing unit
The technique effect of complexity of process fault detection.
Two, due to the technical scheme in the embodiment of the present application, between processor and mainboard, level conversion core can be passed through
Sheet connects, so that can be carried out data transmission by asynchronous transmission standard interface between described processor and described mainboard.Or it is logical
Cross USB interface to connect, so that can carry out data transmission based on usb protocol between described processor and described mainboard.I.e. at this
In technical scheme, the diversity communication mode between processor and mainboard, those of ordinary skill in the art can be according to actual need
Select, and then reached the technique effect of the use scene of abundant fault test set.
Those skilled in the art are it should be appreciated that embodiments of the invention can be provided as method, system or computer program
Product.Therefore, the reality in terms of the present invention can use complete hardware embodiment, complete software implementation or combine software and hardware
Execute the form of example.And, the present invention can use at one or more computers wherein including computer usable program code
The upper computer program product implemented of usable storage medium (including but not limited to disk memory, CD-ROM, optical memory etc.)
The form of product.
The present invention is with reference to method, equipment (system) and the flow process of computer program according to embodiments of the present invention
Figure and/or block diagram describe.It should be understood that can the most first-class by computer program instructions flowchart and/or block diagram
Flow process in journey and/or square frame and flow chart and/or block diagram and/or the combination of square frame.These computer programs can be provided
Instruction arrives the processor of general purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device to produce
A raw machine so that the instruction performed by the processor of computer or other programmable data processing device is produced for real
The device of the function specified in one flow process of flow chart or multiple flow process and/or one square frame of block diagram or multiple square frame now.
These computer program instructions may be alternatively stored in and computer or other programmable data processing device can be guided with spy
Determine in the computer-readable memory that mode works so that the instruction being stored in this computer-readable memory produces and includes referring to
Make the manufacture of device, this command device realize at one flow process of flow chart or multiple flow process and/or one square frame of block diagram or
The function specified in multiple square frames.
These computer program instructions also can be loaded in computer or other programmable data processing device so that at meter
Perform sequence of operations step on calculation machine or other programmable devices to produce computer implemented process, thus at computer or
The instruction performed on other programmable devices provides for realizing at one flow process of flow chart or multiple flow process and/or block diagram one
The step of the function specified in individual square frame or multiple square frame.
Specifically, the fault detect and computer program corresponding to information processing method that provide in the embodiment of the present application refer to
Order can be stored in CD, and hard disk, on the storage medium such as USB flash disk.
The fault detection method that embodiment three is provided, corresponding with described fault detection method when in storage medium
When computer program instructions is read by an electronic equipment or is performed, comprise the steps:
Described fault test set downloads the first test program by emulator, and is stored in flash chip；
Described fault test set is read from described flash chip by PLD and is run described first
Test program, obtains the pin duty of the pin of described digital processing unit, to determine according to described pin duty
Whether described digital processing unit exists fault.
Optionally, in described storage medium, also storage has other computer instruction, this other computer instruction
With step: described fault test set is read from described flash chip by PLD and run described first
The computer instruction that test program is corresponding is performed after being performed execution, and this other computer instruction is specifically being performed
During, specifically include following steps:
Based on described pin duty, determine whether described pin duty is to preset pin duty；
If it has not, then there is the first signal of fault for characterizing described digital processing unit in generation.
Optionally, in described storage medium, also storage has other computer instruction, this other computer instruction
With step: described if it has not, the first signal of then generating, described first signal is used for characterizing described digital processing unit and deposits
Computer instruction corresponding to fault be performed and be performed afterwards, this other computer instruction is specifically being performed process
In, specifically include following steps:
Described first signal is processed by the processor of described fault test set, obtains described digital processing unit
Fault message.
Optionally, in described storage medium, also storage has other computer instruction, this other computer instruction
With step: described first signal is processed by the processor of fault test set, obtains the event of described digital processing unit
Computer instruction corresponding to barrier information is performed and is performed afterwards, and this other computer instruction is specifically being performed process
In, specifically include following steps:
Described fault message is shown by the display device of described fault test set.
The information processing method that embodiment four is provided, corresponding with described information processing method when in storage medium
When computer program instructions is read by an electronic equipment or is performed, comprise the steps:
Download and run the first test program, each defeated to control successively on the connection interface corresponding with described connection slot
Enter/level value of input port is according to prefixed time interval saltus step.
The above, above example is only in order to be described in detail the technical scheme of the application, but implements above
The explanation of example is only intended to help to understand method and the core concept thereof of the present invention, should not be construed as limitation of the present invention.This
Those skilled in the art in the technical scope that the invention discloses, the change that can readily occur in or replacement, all should contain
Within protection scope of the present invention.
Claims (14)
1. a fault test set, including:
Emulator, for downloading the first test program；
Flash chip, is connected with described emulator, is used for storing described first test program；
PLD, is connected with described flash chip；
Wherein, when described fault test set and a digital processing unit connect, described fault test set by described can
Programmed logic device reads from described flash chip and runs described first test program, to determine described digital processing unit
Whether there is fault.
2. fault test set as claimed in claim 1, it is characterised in that described fault test set also includes:
Connecting interface, be connected with described PLD by bus, wherein, described fault test set passes through described company
Connection interface is connected with described digital processing unit.
3. fault test set as claimed in claim 1, it is characterised in that described PLD is used for:
Obtain the pin duty of described connection interface；
Determine whether described pin duty is to preset pin duty；
If it has not, the first signal then generated, described first signal is for characterizing the fault that described digital processing unit exists.
4. fault test set as claimed in claim 3, it is characterised in that described fault test set also includes:
Processor, is connected with described PLD, for processing described first signal, obtains at described numeral
The fault message of reason device.
5. fault test set as claimed in claim 4, it is characterised in that described fault test set also includes:
Mainboard, is connected between described emulator and described processor, is used for obtaining described fault message.
6. fault test set as claimed in claim 5, it is characterised in that described fault test set also includes:
Electrical level transferring chip, is connected between described processor and described mainboard, so that between described processor and described mainboard
Can be carried out data transmission by asynchronous transmission standard interface.
7. fault test set as claimed in claim 5, it is characterised in that described fault test set also includes:
USB interface, is connected between described processor and described mainboard, so that can base between described processor and described mainboard
Carry out data transmission in usb protocol.
8. the fault test set as described in claim as arbitrary in claim 4-7, it is characterised in that described fault test set also wraps
Include:
Display device, is connected with described mainboard, is used for showing described fault message.
9. a digital processing unit, including:
Connect slot, for being connected with fault test set；
Processor, connects with the described slot that is connected；
Wherein, when described digital processing unit is connected with described fault test set by described connection slot, downloads and transport
Row the first test program, controls the level of each input/input port on the connection interface corresponding with described connection slot successively
Value is according to prefixed time interval saltus step.
10. a fault detection method, is applied to fault test set, when described fault test set and a digital processing unit
During connection, described method includes:
Described fault test set downloads the first test program by emulator, and is stored in flash chip；
Described fault test set reads and runs described first test by PLD from described flash chip
Program, to determine whether described digital processing unit exists fault.
11. methods as claimed in claim 10, it is characterised in that pass through PLD at described fault test set
After reading from described flash chip and running described first test program, described method also includes:
Obtain the pin duty of described connection interface；
Determine whether described pin duty is to preset pin duty；
If it has not, the first signal then generated, described first signal is for characterizing the fault that described digital processing unit exists.
12. methods as claimed in claim 11, it is characterised in that described if it has not, the first signal of then generating, described
One signal is after characterizing the fault that described digital processing unit exists, and described method also includes:
Described first signal is processed by the processor of described fault test set, obtains the fault of described digital processing unit
Information.
Method as described in 13. claims as arbitrary in claim 10-12, it is characterised in that in the process of described fault test set
Described first signal is processed by device, and after obtaining the fault message of described digital processing unit, described method also includes:
Described fault message is shown by the display device of described fault test set.
14. 1 kinds of information processing methods, are applied to a digital processing unit, when described digital processing unit and a fault detect set
During standby connection, described method includes:
Download and run the first test program, with control successively each input on the connection interface corresponding with described connection slot/
The level value of input port is according to prefixed time interval saltus step.
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