CN106199393B - A kind of fault test set and fault detection method - Google Patents
A kind of fault test set and fault detection method Download PDFInfo
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- CN106199393B CN106199393B CN201610525246.XA CN201610525246A CN106199393B CN 106199393 B CN106199393 B CN 106199393B CN 201610525246 A CN201610525246 A CN 201610525246A CN 106199393 B CN106199393 B CN 106199393B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31717—Interconnect testing
Abstract
The invention discloses a kind of fault test set and fault detection methods, comprising: emulator, for downloading the first test program；Flash chip is connect with the emulator, for storing first test program；Programmable logic device is connect with the flash chip；Wherein, when the fault test set is connect with a digital processing unit, the fault test set is read from the flash chip by the programmable logic device and runs first test program, the pin working condition of the pin of the digital processing unit is obtained, to determine the digital processing unit with the presence or absence of failure according to the pin working condition.The technical solution provided through the invention, the process fault detection for solving digital processing unit in the prior art are complex.
Description
Technical field
The present invention relates to field of equipment failure detection, in particular to a kind of fault test set and fault detection method.
Background technique
With the continuous development of science and technology, the successive appearance of LSI, VLSI, ULSI, silicon Single-Chip Integration degree constantly mention
Height, the requirement to integrated antenna package is stringenter, the great increase of I/O number of pins, and power consumption is also with increase, in order to meet development
Needs, on the basis of original encapsulation kind, and add new one BGA Package of kind.
In the prior art, to the fault detection method of the chip of BGA Package, being to take off chip to weigh one by one
Weldering, if still faulty, just replaces device, however, taking and reweld chip all is very complicated process, while to printing one by one
The damage of plate is larger.
As it can be seen that the process fault detection of digital processing unit is complex in the prior art.
Summary of the invention
The embodiment of the present invention provides a kind of fault test set and fault detection method, digital in the prior art for solving
The process fault detection of processing module complex technical problem is answered with simplifying the process fault detection of digital processing unit
The technical effect of miscellaneous degree.
On the one hand, the embodiment of the present application provides a kind of fault test set, comprising:
Emulator, for downloading the first test program；
Flash chip is connect with the emulator, for storing first test program；
Programmable logic device is connect with the flash chip；
Wherein, when the fault test set is connect with a digital processing unit, the fault test set passes through institute
It states programmable logic device and first test program is read and run from the flash chip, obtain the digital processing dress
The pin working condition for the pin set, to determine the digital processing unit with the presence or absence of event according to the pin working condition
Barrier.
Optionally, the fault test set further include:
Connecting interface is connect by bus with the programmable logic device, wherein the fault test set passes through institute
Connecting interface is stated to connect with the digital processing unit.
Optionally, the programmable logic device is used for:
Obtain the pin working condition of the connecting interface；
Determine whether the pin working condition is default pin working condition；
If it has not, the first signal then generated, first signal is for characterizing event existing for the digital processing unit
Barrier.
Optionally, the fault test set further include:
Processor is connect with the programmable logic device, for handling first signal, obtains the number
The fault message of word processing device.
Optionally, the fault test set further include:
Mainboard is connected between the emulator and the processor, for obtaining the fault message.
Optionally, the fault test set further include:
Electrical level transferring chip is connected between the processor and the mainboard, so that the processor and the mainboard
Between can be carried out data transmission by asynchronous transmission standard interface.
Optionally, the fault test set further include:
USB interface is connected between the processor and the mainboard, so that energy between the processor and the mainboard
Enough carried out data transmission based on usb protocol.
Optionally, the fault test set further include:
Display device is connect with the mainboard, for showing the fault message.
On the other hand, the embodiment of the present application also provides a kind of digital processing unit, comprising:
Connected slot, for being connect with fault test set；
Processor is connect with the connected slot；
Wherein, when the digital processing unit is connect by the connected slot with the fault test set, downloading
And the first test program is run, successively control each input/input port in connecting interface corresponding with the connected slot
Level value is jumped according to prefixed time interval.
On the other hand, the embodiment of the present application also provides a kind of fault detection method, is applied to fault test set, when described
When fault test set is connect with a digital processing unit, which comprises
The fault test set downloads the first test program by emulator, and is stored in flash chip；
The fault test set reads from the flash chip by programmable logic device and runs described first
Test program obtains the pin working condition of the pin of the digital processing unit, to be determined according to the pin working condition
The digital processing unit whether there is failure.
Optionally, it reads and runs from the flash chip by programmable logic device in the fault test set
After first test program, the method also includes:
Based on the pin working condition, determine whether the pin working condition is default pin working condition；
If it has not, then generating for characterizing first signal of the digital processing unit there are failure.
Optionally, described if it has not, the first signal then generated, first signal is for characterizing the digital processing
After failure existing for device, the method also includes:
The processor of the fault test set handles first signal, obtains the digital processing unit
Fault message.
Optionally, first signal is handled in the processor of the fault test set, described in acquisition
After the fault message of digital processing unit, the method also includes:
The fault message is shown by the display device of the fault test set.
On the other hand, the embodiment of the present application also provides a kind of information processing method, is applied to a digital processing unit, works as institute
When stating digital processing unit and being connect with a fault test set, which comprises
The first test program is downloaded and runs, it is each defeated in connecting interface corresponding with the connected slot successively to control
Enter/level value of input port jumps according to prefixed time interval.
One, due to the technical solution in the embodiment of the present application, fault test set includes: emulator, for downloading first
Test program；Flash chip is connect with the emulator, for storing first test program；Programmable logic device, with
The flash chip connection；Wherein, when the fault test set is connect with a digital processing unit, the fault detection is set
It is standby to read and run first test program from the flash chip by the programmable logic device, obtain the number
The pin working condition of the pin of word processing device, whether to determine the digital processing unit according to the pin working condition
There are failures.I.e. will not be as in the prior art, fault detection to digital processing unit is needed the chip of digital processing unit
It takes off and rewelds one by one, spend the time longer.And in the technical scheme, pass through the programmable logic device in fault test set
Part operation the first test program, come read digital processing unit pin pin working condition, with determine digital processing fill
The failure set is rewelded to avoid removing chip, simplifies whole operation process, thus it is possible to effectively solve existing
In technology the technical issues of the complexity of the process fault detection of digital processing unit, and then reaches and simplify to digital processing unit
Process fault detection complexity technical effect.
Two, due to the technical solution in the embodiment of the present application, level conversion core can be passed through between processor and mainboard
Piece connection, so as to can be carried out data transmission by asynchronous transmission standard interface between the processor and the mainboard.Or it is logical
USB interface connection is crossed, so as to can carry out data transmission based on usb protocol between the processor and the mainboard.I.e. at this
In technical solution, diversity communication mode between processor and mainboard, those of ordinary skill in the art can be according to practical need
It is selected, and then has reached the technical effect of the usage scenario of abundant fault test set.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram for fault test set that the embodiment of the present application one provides；
Fig. 2 is a kind of structural schematic diagram for digital processing unit that the embodiment of the present application two provides；
Fig. 3 is a kind of structural schematic diagram for fault detection method that the embodiment of the present application three provides.
Specific embodiment
The embodiment of the present invention provides a kind of fault test set and fault detection method, digital in the prior art for solving
The complex technical problem of the process fault detection of processing unit, to reach the process fault detection of simplified digital processing unit
Complexity technical effect.
Technical solution in the embodiment of the present application is in order to solve the above technical problems, general thought is as follows:
Emulator, for downloading the first test program；
Flash chip is connect with the emulator, for storing first test program；
Programmable logic device is connect with the flash chip；
Wherein, when the fault test set is connect with a digital processing unit, the fault test set passes through institute
It states programmable logic device and first test program is read and run from the flash chip, with the determination digital processing
Device whether there is failure.
Through the above technical solutions, fault test set includes: emulator, for downloading the first test program；Flash memory core
Piece is connect with the emulator, for storing first test program；Programmable logic device connects with the flash chip
It connects；Wherein, when the fault test set is connect with a digital processing unit, the fault test set can be compiled by described
Journey logical device reads from the flash chip and runs first test program, is with the determination digital processing unit
It is no that there are failures.I.e. will not be as in the prior art, fault detection to digital processing unit is needed the core of digital processing unit
Piece is taken off to be rewelded one by one, spends the time longer.And in the technical scheme, pass through the programmable logic in fault test set
First test program of device operation determines the failure of digital processing unit, rewelds to avoid removing chip, letter
Whole operation process is changed, thus it is possible to effectively solve the complexity of the process fault detection of digital processing unit in the prior art
The technical issues of spending, and then reach the technical effect for simplifying the complexity to the process fault detection of digital processing unit.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Embodiment one
Referring to FIG. 1, the embodiment of the present application one provides a kind of fault test set, comprising:
Wherein, when the fault test set is connect with a digital processing unit, the fault test set passes through institute
It states programmable logic device and first test program is read and run from the flash chip, with the determination digital processing
Device whether there is failure.
In the embodiment of the present application, emulator is connected between mainboard and flash chip, and it is imitative that emulator is specifically as follows BMD
True device is JTAG emulator.During specific implementation, if emulator by taking JTAG emulator as an example, JTAG emulator and master
It is then connected by USB cable between plate, for the first test program to be downloaded in flash chip.
Further, in the embodiment of the present application, jtag interface is four lines: TMS, TCK, TDI, TDO, wherein TCK is test
Clock input；TDI is test data input, and data input jtag interface by TDI pin；TDO is test data output, data
It is exported by TDO pin from jtag interface；TMS is test pattern selection, and TMS is used to be arranged jtag interface and is in certain specific
Test pattern.It is connected between JTAG emulator and flash chip by four lines in the embodiment of the present application, same flash chip
It is also to be connected by four lines between programmable logic device.
In the embodiment of the present application, programmable logic device be specifically as follows CPLD Complex Programmable Logic Devices or
FPGA.In the embodiment of the present application, programmable logic device is by taking FPGA as an example.And when programmable logic device is specially FPGA
When, emulation, debugging and programming to programmable logic device can be completed in bottom by four signals of above-mentioned four line transmission,
So that FPGA can run application program, and then complete the fault detection to digital processing unit.
Further, in the embodiment of the present application, the fault test set further include:
Connecting interface is connect by bus with the programmable logic device, wherein the fault test set passes through institute
Connecting interface is stated to connect with the digital processing unit.
In the embodiment of the present application, fault test set is connect by connecting interface with digital processing unit.Such as: specific
During realization, connecting interface is specifically as follows 1,2 perhaps 3 or for other quantity, those of ordinary skill in the art
It can implement depending on specific design requirement according to (Printed Circuit Board, PCB) printed circuit board in the application
It is not especially limited in example.
In the embodiment of the present application, by taking an interface as an example, specifically, such as: it is corresponding that interface 1 by bus is connected to FPGA
I/O pin on.
After fault test set is connected on digital processing unit, then from the electricity that is connected on digital processing unit
Compiled test program 2 is downloaded in digital processing unit in sub- equipment, correspondingly, will be compiled by JTAG emulator
Test program 1 be downloaded in flash chip so that after system electrification, digital processing unit runs test program 2
Meanwhile FPGA runs test program 2.
In the embodiment of the present application, test program 2 is used to successively control N number of input/output terminal in the connecting interface
The level value of each input/input port in mouthful is jumped according to prefixed time interval.So that FPGA is in operation test program
1, the working condition that pin 1 arrives bus pin 220 is scanned by bus synchronous, with the event of discriminating digit processing unit respective chip
Barrier.
In the embodiment of the present application, the programmable logic device is used for:
Obtain the pin working condition of the connecting interface；
Determine whether the pin working condition is default pin working condition；
If it has not, the first signal then generated, first signal is for characterizing event existing for the digital processing unit
Barrier.
In the embodiment of the present application, the pin working condition of connecting interface is specifically as follows the voltage value of pin output, or
Person is the low and high level value of pin output, or is other states, is not especially limited in the embodiment of the present application.
During specific implementation, due to including power supply chip and by the chip of BGA package in digital processing unit,
Such as: DSP, FPGA are below then respectively illustrated the process fault detection of these two types of chips.
The first kind: the process fault detection of power supply chip.
In the embodiment of the present application, the pin working condition for the connecting interface that FPGA is obtained, such as: the voltage value of output is 5V
Or 0V, during specific implementation, PFGA can carry out analog-to-digital conversion to the signal received, and such as: 5V voltage signal is converted into number
Word signal is then that be converted into digital signal be then 0 to 255,0V voltage signal.Correspondingly, in the embodiment of the present application, presetting pin
Working condition corresponding digital signals are 255.
It is not default pin work if the digital signal after PFGA progress analog-to-digital conversion is 0 during specific implementation
At this moment state 255 then determines that there are failures for power supply chip, at this moment then generate the first signal such as accordingly: 01, fe.
Second class: the process fault detection of the chip encapsulated in the form of BGA.
In the embodiment of the present application, for the chip encapsulated by BGA form, then directly defeated by detecting corresponding pin
Whether low and high level out is default low and high level.Specifically, such as: 2 output level value of pin of detection is low level, is non-pre-
If level, high level then generates the first signal such as accordingly: 02, fd in this way after all pins detect；Or 03, fc.
Further, in the embodiment of the present application, the fault test set further include:
Processor is connect with the programmable logic device, for handling first signal, obtains the number
The fault message of word processing device.
During specific implementation, processor is specifically as follows ARM, AMD or is other processors, the common skill in this field
Art personnel can set according to actual needs, be not especially limited in the embodiment of the present application.
In the embodiment of the present application, processor receives and dispatches number by USB communication protocol between ARM and FPGA by taking ARM as an example
According to FPGA is by the first signal, such as: 01, fe；02, fd；Or 03, fc is sent to ARM, and ARM is then number according to the judgement of the first signal
There are failures for which block chip in processing unit, and with the presence of several pin problems, such as: 01, fe characterization power supply chip has 1
There are problems for a pin；02, fd characterization DSP, with the presence of 2 pin problems etc..
During specific implementation, fault type is broadly divided into three classes, carries out separately below to these three types of fault types detailed
It describes in detail bright.
The first fault type: the chip failure of digital processing unit.
One, fault test set can not scan the power supply signal in respective bus, then show the electricity of digital processing unit
Source chip failure；
Two, it can not be downloaded in digital processing module in test program 2, then show that the flash chip of digital processing unit loses
Effect；
Three, when the FPGA bus of fault test set can not scan corresponding pulse signal, then show digital processing
The fpga chip of device fails；
Four, when the dsp bus of fault test set can not scan corresponding pulse signal, then show that digital processing fills
The DSP failure set.
Second of fault type: digital processing unit chip even welds.
One, fault test set detects that load current overload, relay disconnect digital processing unit power supply, then show to count
The power supply chip of word processing device even welds；
Two, when test program 2 can not download in digital processing unit, and with relay module current overload, then show
The flash chip of digital processing unit even welds；
Three, when in the FPGA bus of fault test set synchronization scanning to multiple pulse signals, then show FPGA core
Piece even welds；
Four, when synchronization scanning is to multiple pulse signals on the dsp bus of fault test set, then show DSP core
Piece even welds.
The third fault type: digital processing unit chip rosin joint.
One, fault test set bus can not scan corresponding power supply signal, after gently firmly pressing power module, always
Line scanning is normal, then shows power supply chip rosin joint；
Two, test program 2 can not download in digital processing unit, and after gently firmly pressing flash chip, program is normal
Downloading, then show flash chip rosin joint；
Three, scanning then shows FPGA core to when having individual pin pulse-free signals in the FPGA bus of fault test set
Piece rosin joint；
Four, scanning then shows dsp chip void to there is individual pin pulse-free signals on the dsp bus of fault test set
Weldering.
Further, in the embodiment of the present application, the fault test set further include:
Mainboard is connected between the emulator and the processor, for obtaining the fault message.
In the embodiment of the present application, be specifically including but not limited on mainboard, such as: cpu central processing unit, memory bar, video card,
Hard disk, power supply etc..After ARM determines the fault message of digital processing unit according to the first signal, then by corresponding failure
Information is sent to mainboard, to be stored on the hard disk of mainboard.
In the embodiment of the present application, specific between mainboard and ARM there are two types of connection types, separately below to both connections
Mode is described in detail.
The first connection type, the fault test set further include:
Electrical level transferring chip is connected between the processor and the mainboard, so that the processor and the mainboard
Between can be carried out data transmission by asynchronous transmission standard interface.
During specific implementation, although ARM single-chip microcontroller has the function of serial communication, the signal that single-chip microcontroller provides
The standard of level and RS232 are different, further include electrical level transferring chip in the embodiment of the present application therefore, such as: MAX232 into
Line level conversion, so that ARM can be by being communicated between RS232 interface and mainboard.
Second of connection type, the fault test set further include:
USB interface is connected between the processor and the mainboard, so that energy between the processor and the mainboard
Enough carried out data transmission based on usb protocol.
During specific implementation, it can also be communicated by USB interface based on usb protocol between ARM and mainboard.
For above two implementation, those of ordinary skill in the art can select according to actual needs, implement in the application
It is not especially limited in example.
Further, in the embodiment of the present application, the fault test set further include:
Display device is connect with the mainboard, for showing the fault message.
During specific implementation, fault test set further includes display device, is being shown for showing fault message
It is checked in device for user, to handle the failure detected, in the embodiment of the present application, display device passes through PCI-E
Interface is attached with mainboard.
In the embodiment of the present application, display device is specifically as follows LCD liquid crystal display screen or LED display, or is it
The display screen of its type, those of ordinary skill in the art can select according to actual needs, in the embodiment of the present application not
Make specific limit.
Embodiment two
Referring to FIG. 2, providing a kind of digital processing unit in the embodiment of the present application, comprising:
Connected slot 20, for being connect with fault test set；
Processor 21 is connect with the connected slot；
Wherein, when the digital processing unit is connect by the connected slot with the fault test set, downloading
And the first test program is run, successively control each input/input port in connecting interface corresponding with the connected slot
Level value is jumped according to prefixed time interval.
In the embodiment of the present application, digital processing unit includes specially fpga chip, dsp processor, power supply chip
Processing unit, and the chip in digital processing unit in the embodiment of the present application, such as: FPGA, DSP are by BGA package side
Formula is packaged.
Further, digital processing unit specifically includes slot, for connecting with fault test set, is implemented in the application
In example, the number of slot and the quantity of connecting interface are corresponding, such as: if only one connecting interface, the number of slot is also 1
It is a；If there is 2 connecting interfaces, the number of slot is 2.
In the embodiment of the present application, fault test set is used to detect the failure of digital processing unit.It was implementing
Cheng Zhong, when digital processing unit is connect with fault test set, the first test program is downloaded and run to digital processing unit,
In the embodiment of the present application, the first test program of operation is for controlling I/ mouth all in connecting interface corresponding with connected slot
It is initially high level, is then by high level jump according to the level of a pin corresponding in prefixed time interval control bus
Low level, in the embodiment of the present application, prefixed time interval can be 100 milliseconds, 200 milliseconds or 300 milliseconds, or be other
Prefixed time interval is not especially limited in the embodiment of the present application.
Correspondingly, on the control bus the level of a corresponding pin by high level jump be low level when, also to control
Make the pin and be in one predetermined time period of low level, such as: 200 milliseconds, 300 milliseconds or 400 milliseconds, or for it is other default when
Between length, those of ordinary skill in the art can set according to actual needs, not limit specifically in the embodiment of the present application
It is fixed.
During specific implementation, successively from pin 1 to bus pin 220,220 digital processing program of device knots are run
Beam, when digital processing unit runs test program 2, FPGA runs test program 2 simultaneously in system, is scanned by bus synchronous
Pin 1 arrives the working condition of bus pin 220, with the failure of discriminating digit processing unit respective chip.
Embodiment three
Referring to FIG. 3, the embodiment of the present application provides a kind of fault detection method, it is applied to fault test set, when described
When fault test set is connect with a digital processing unit, which comprises
S301: the fault test set downloads the first test program by emulator, and is stored in flash chip；
S302: the fault test set is read from the flash chip by programmable logic device and is run described
First test program obtains the pin working condition of the pin of the digital processing unit, according to the pin working condition
Determine the digital processing unit with the presence or absence of failure.
In the embodiment of the present application, step S301 is first carried out: the fault test set passes through emulator downloading first
Test program, and be stored in flash chip.
In the embodiment of the present application, emulator is specifically as follows BMD emulator or is JTAG emulator.It is implementing
In the process, if emulator is by taking JTAG emulator as an example, when fault test set is connect by connecting interface with digital processing unit
When, fault test set is downloaded the first test program by emulator JTAG and is stored in flash chip.
After executing the step S302, then follow the steps S302: the fault test set passes through programmable logic device
Part reads from the flash chip and runs first test program, obtains the pin of the pin of the digital processing unit
Working condition, to determine the digital processing unit with the presence or absence of failure according to the pin working condition.
In the embodiment of the present application, programmable logic device be specifically as follows CPLD Complex Programmable Logic Devices or
FPGA.During specific implementation, if the first test program by taking FPGA as an example, is downloaded to by programmable logic device in emulator
After in flash chip, FPGA then reads from flash chip and runs the first test program.
In the embodiment of the present application, after the FPGA runs the first test program, the method also includes:
Obtain the pin working condition of the connecting interface；
Determine whether the pin working condition is default pin working condition；
If it has not, the first signal then generated, first signal is for characterizing event existing for the digital processing unit
Barrier.
In the embodiment of the present application, how programmable logic device determines digital place according to the pin working condition of scanning
Manage failure existing for device.In the embodiment of the present application, the pin working condition of connecting interface is specifically as follows pin output
Voltage value, perhaps for pin output low and high level value or be other states, do not limit specifically in the embodiment of the present application
It is fixed.
During specific implementation, due to including power supply chip and by the chip of BGA package in digital processing unit,
Such as: DSP, FPGA are below then respectively illustrated the process fault detection of these two types of chips.
The first kind: the process fault detection of power supply chip.
In the embodiment of the present application, the pin working condition for the connecting interface that FPGA is obtained, such as: the voltage value of output is 5V
Or 0V, during specific implementation, PFGA can carry out analog-to-digital conversion to the signal received, and such as: 5V voltage signal is converted into number
Word signal is then that be converted into digital signal be then 0 to 255,0V voltage signal.Correspondingly, in the embodiment of the present application, presetting pin
Working condition corresponding digital signals are 255.
It is not default pin work if the digital signal after PFGA progress analog-to-digital conversion is 0 during specific implementation
At this moment state 255 then determines that there are failures for power supply chip, at this moment then generate the first signal such as accordingly: 01, fe.
Second class: the process fault detection of the chip encapsulated in the form of BGA.
In the embodiment of the present application, for the chip encapsulated by BGA form, then directly defeated by detecting corresponding pin
Whether low and high level out is default low and high level.Specifically, such as: 2 output level value of pin of detection is low level, is non-pre-
If level, high level then generates the first signal such as accordingly: 02, fd in this way after all pins detect；Or 03, fc.
In the embodiment of the present application, after step S301, the method also includes:
Processor is connect with the programmable logic device, for handling first signal, obtains the number
The fault message of word processing device.
In the embodiment of the present application, processor is specifically as follows ARM or AMD or is other types of processor, ability
Domain those of ordinary skill can set according to actual needs, be not especially limited in the embodiment of the present application.
During specific implementation, processor receives and dispatches number by USB communication protocol between ARM and FPGA by taking ARM as an example
According to FPGA is by the first signal, such as: 01, fe；02, fd；Or 03, fc is sent to ARM, and ARM is then number according to the judgement of the first signal
There are failures for which block chip in processing unit, and with the presence of several pin problems, such as: 01, fe characterization power supply chip has 1
There are problems for a pin；02, fd characterization DSP, with the presence of 2 pin problems etc..
During specific implementation, fault type is broadly divided into three classes, carries out separately below to these three types of fault types detailed
It describes in detail bright.
The first fault type: the chip failure of digital processing unit.
One, fault test set can not scan the power supply signal in respective bus, then show the electricity of digital processing unit
Source chip failure；
Two, it can not be downloaded in digital processing module in test program 2, then show that the flash chip of digital processing unit loses
Effect；
Three, when the FPGA bus of fault test set can not scan corresponding pulse signal, then show digital processing
The fpga chip of device fails；
Four, when the dsp bus of fault test set can not scan corresponding pulse signal, then show that digital processing fills
The DSP failure set.
Second of fault type: digital processing unit chip even welds.
One, fault test set detects that load current overload, relay disconnect digital processing unit power supply, then show to count
The power supply chip of word processing device even welds；
Two, when test program 2 can not download in digital processing unit, and with relay module current overload, then show
The flash chip of digital processing unit even welds；
Three, when in the FPGA bus of fault test set synchronization scanning to multiple pulse signals, then show FPGA core
Piece even welds；
Four, when synchronization scanning is to multiple pulse signals on the dsp bus of fault test set, then show DSP core
Piece even welds.
The third fault type: digital processing unit chip rosin joint.
One, fault test set bus can not scan corresponding power supply signal, after gently firmly pressing power module, always
Line scanning is normal, then shows power supply chip rosin joint；
Two, test program 2 can not download in digital processing unit, and after gently firmly pressing flash chip, program is normal
Downloading, then show flash chip rosin joint；
Three, scanning then shows FPGA core to when having individual pin pulse-free signals in the FPGA bus of fault test set
Piece rosin joint；
Four, scanning then shows dsp chip void to there is individual pin pulse-free signals on the dsp bus of fault test set
Weldering.
In the embodiment of the present application, first signal is handled in the processor of the fault test set, is obtained
After the fault message for taking the digital processing unit, the method also includes:
The fault message is shown by the display device of the fault test set.
During specific implementation, after processor determines the fault message of digital processing unit, then by fault message
Be sent to mainboard, and the display device by connecting with mainboard is shown, for user access, and then to failure at
Reason.
Example IV
The embodiment of the present application example provides a kind of information processing method, is applied to a digital processing unit, at the number
When reason device is connect with a fault test set, which comprises
The first test program is downloaded and runs, it is each defeated in connecting interface corresponding with the connected slot successively to control
Enter/level value of input port jumps according to prefixed time interval.
In the embodiment of the present application, fault test set is used to detect the failure of digital processing unit.It was implementing
Cheng Zhong, when digital processing unit is connect with fault test set, the first test program is downloaded and run to digital processing unit,
In the embodiment of the present application, the first test program of operation is initial for controlling I/ mouth all on interface corresponding with connected slot
It is then low electricity by high level jump according to the level of a pin corresponding in prefixed time interval control bus for high level
Flat, in the embodiment of the present application, prefixed time interval can be 100 milliseconds, 200 milliseconds or 300 milliseconds, or be other default
Time interval is not especially limited in the embodiment of the present application.
Correspondingly, on the control bus the level of a corresponding pin by high level jump be low level when, also to control
Make the pin and be in one predetermined time period of low level, such as: 200 milliseconds, 300 milliseconds or 400 milliseconds, or for it is other default when
Between length, those of ordinary skill in the art can set according to actual needs, not limit specifically in the embodiment of the present application
It is fixed.
During specific implementation, successively from pin 1 to bus pin 220,220 digital processing program of device knots are run
Beam, when digital processing unit runs test program 2, FPGA runs test program 2 simultaneously in system, is scanned by bus synchronous
Pin 1 arrives the working condition of bus pin 220, with the failure of discriminating digit processing unit respective chip.To which avoid will be digital
The chip of processing unit is taken off to be rewelded one by one, and whole operation process is complex.
Said one or multiple technical solutions in the embodiment of the present application at least have following one or more technology effect
Fruit:
One, due to the technical solution in the embodiment of the present application, fault test set includes: emulator, for downloading first
Test program；Flash chip is connect with the emulator, for storing first test program；Programmable logic device, with
The flash chip connection；Wherein, when the fault test set is connect with a digital processing unit, the fault detection is set
It is standby to read and run first test program from the flash chip by the programmable logic device, obtain the number
The pin working condition of the pin of word processing device, whether to determine the digital processing unit according to the pin working condition
There are failures.I.e. will not be as in the prior art, fault detection to digital processing unit is needed the chip of digital processing unit
It takes off and rewelds one by one, spend the time longer.And in the technical scheme, pass through the programmable logic device in fault test set
Part operation the first test program, come read digital processing unit pin pin working condition, with determine digital processing fill
The failure set is rewelded to avoid removing chip, simplifies whole operation process, thus it is possible to effectively solve existing
In technology the technical issues of the complexity of the process fault detection of digital processing unit, and then reaches and simplify to digital processing unit
Process fault detection complexity technical effect.
Two, due to the technical solution in the embodiment of the present application, level conversion core can be passed through between processor and mainboard
Piece connection, so as to can be carried out data transmission by asynchronous transmission standard interface between the processor and the mainboard.Or it is logical
USB interface connection is crossed, so as to can carry out data transmission based on usb protocol between the processor and the mainboard.I.e. at this
In technical solution, diversity communication mode between processor and mainboard, those of ordinary skill in the art can be according to practical need
It is selected, and then has reached the technical effect of the usage scenario of abundant fault test set.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Specifically, the corresponding computer program of fault detection and information processing method provided in the embodiment of the present application refers to
CD can be stored in by enabling, hard disk, on the storage mediums such as USB flash disk.
For the fault detection method that embodiment three provides, when corresponding with the fault detection method in storage medium
Computer program instructions are read or are performed by an electronic equipment, include the following steps:
The fault test set downloads the first test program by emulator, and is stored in flash chip；
The fault test set reads from the flash chip by programmable logic device and runs described first
Test program obtains the pin working condition of the pin of the digital processing unit, to be determined according to the pin working condition
The digital processing unit whether there is failure.
Optionally, it is also stored with other computer instruction in the storage medium, the other computer instruction
With step: the fault test set is read from the flash chip by programmable logic device and runs described first
The corresponding computer instruction of test program is performed after being performed execution, which is specifically being performed
In the process, specifically comprise the following steps:
Based on the pin working condition, determine whether the pin working condition is default pin working condition；
If it has not, then generating for characterizing first signal of the digital processing unit there are failure.
Optionally, it is also stored with other computer instruction in the storage medium, the other computer instruction
With step: described if it has not, the first signal then generated, first signal are deposited for characterizing the digital processing unit
The corresponding computer instruction of failure be performed after be performed, which is specifically being performed process
In, specifically comprise the following steps:
The processor of the fault test set handles first signal, obtains the digital processing unit
Fault message.
Optionally, it is also stored with other computer instruction in the storage medium, the other computer instruction
With step: the processor of fault test set handles first signal, obtains the event of the digital processing unit
The corresponding computer instruction of barrier information is performed after being performed, which is specifically being performed process
In, specifically comprise the following steps:
The fault message is shown by the display device of the fault test set.
For the information processing method that example IV provides, when corresponding with the information processing method in storage medium
Computer program instructions are read or are performed by an electronic equipment, include the following steps:
The first test program is downloaded and runs, it is each defeated in connecting interface corresponding with the connected slot successively to control
Enter/level value of input port jumps according to prefixed time interval.
The above, above embodiments are only described in detail to the technical solution to the application, but the above implementation
The explanation of example is merely used to help understand method and its core concept of the invention, should not be construed as limiting the invention.This
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those skilled in the art, should all cover
Within protection scope of the present invention.
Claims (11)
1. a kind of fault test set characterized by comprising
Emulator, for downloading the first test program；
Flash chip is connect with the emulator, for storing first test program；
Programmable logic device is connect with the flash chip；
Connecting interface is connect by bus with the programmable logic device, wherein the fault test set passes through the company
Connection interface is connect with a digital processing unit；
Wherein, when the fault test set is connect with the digital processing unit, the fault test set passes through described
Programmable logic device reads from the flash chip and runs first test program, to cooperate the digital processing to fill
The second test program for setting middle operation determines the digital processing unit with the presence or absence of failure, and second test program is used for
The level value for successively controlling each input/output end port in the connecting interface is jumped according to prefixed time interval；
The programmable logic device is used for: obtaining the pin working condition of the connecting interface；Determine the pin work shape
Whether state is default pin working condition；If it has not, then generating the first signal, first signal is for characterizing at the number
Manage failure existing for device.
2. fault test set as described in claim 1, which is characterized in that the fault test set further include:
Processor is connect with the programmable logic device, for handling first signal, is obtained at the number
Manage the fault message of device.
3. fault test set as claimed in claim 2, which is characterized in that the fault test set further include:
Mainboard is connected between the emulator and the processor, for obtaining the fault message.
4. fault test set as claimed in claim 3, which is characterized in that the fault test set further include:
Electrical level transferring chip is connected between the processor and the mainboard, so that between the processor and the mainboard
It can be carried out data transmission by asynchronous transmission standard interface.
5. fault test set as claimed in claim 3, which is characterized in that the fault test set further include:
USB interface is connected between the processor and the mainboard, so that being capable of base between the processor and the mainboard
Carry out data transmission in usb protocol.
6. the fault test set as described in any claim of claim 3-5, which is characterized in that the fault test set also wraps
It includes:
Display device is connect with the mainboard, for showing the fault message.
7. a kind of digital processing unit characterized by comprising
Connected slot, for being connect with fault test set；
Processor is connect with the connected slot；
Wherein, it when the digital processing unit is connect by the connected slot with the fault test set, downloads and transports
The first test program of row successively controls the level of each input/output end port in connecting interface corresponding with the connected slot
Value is jumped according to prefixed time interval, with the second test journey for cooperating the programmable logic device of the fault test set to run
Sequence determines the digital processing unit with the presence or absence of failure, and second test program is used to obtain the pipe of the connecting interface
Foot working condition, and determine whether the pin working condition is default pin working condition；If it has not, then generating the first letter
Number, first signal is for characterizing failure existing for the digital processing unit.
8. a kind of fault detection method, which is characterized in that be applied to fault test set, when the fault test set and a number
When word processing device connects, which comprises
The fault test set downloads the first test program by emulator, and is stored in flash chip；
The fault test set is read from the flash chip by programmable logic device and runs first test
Program determines that the digital processing unit whether there is to cooperate the second test program run in the digital processing unit
Failure, the level value that second test program is used to successively control each input/output end port in the connecting interface are pressed
It is jumped according to prefixed time interval；
It is read from the flash chip by programmable logic device in the fault test set and runs described first and surveyed
After trying program, the method also includes:
Obtain the pin working condition of the connecting interface；
Determine whether the pin working condition is default pin working condition；
If it has not, the first signal then generated, first signal is for characterizing failure existing for the digital processing unit.
9. method according to claim 8, which is characterized in that described if it has not, the first signal then generated, described first
After signal is used to characterize failure existing for the digital processing unit, the method also includes:
The processor of the fault test set handles first signal, obtains the failure of the digital processing unit
Information.
10. the method as described in any claim of claim 8-9, which is characterized in that in the processor of the fault test set
First signal is handled, after the fault message for obtaining the digital processing unit, the method also includes:
The fault message is shown by the display device of the fault test set.
11. a kind of information processing method, which is characterized in that be applied to a digital processing unit, when the digital processing unit with
When one fault test set connects, which comprises
Download and run the first test program, with successively control in connecting interface corresponding with the connected slot it is each input/
The level value of output port is jumped according to prefixed time interval, to cooperate the programmable logic device of the fault test set to transport
The second capable test program determines the digital processing unit with the presence or absence of failure, and second test program is for obtaining institute
The pin working condition of connecting interface is stated, and determines whether the pin working condition is default pin working condition；If it has not,
The first signal is then generated, first signal is for characterizing failure existing for the digital processing unit.
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| CN106708685A (en) * | 2017-02-24 | 2017-05-24 | 上海与德信息技术有限公司 | Fault detection method and electronic equipment |
| CN107592697A (en) * | 2017-08-09 | 2018-01-16 | 深圳纳富特科技有限公司 | Detection method, device and the readable storage medium storing program for executing of the working condition of LED lamp |
| CN108107352A (en) * | 2017-12-06 | 2018-06-01 | 中国电子产品可靠性与环境试验研究所 | FPGA device tests system and method |
| CN110022178B (en) * | 2018-08-13 | 2022-06-17 | 深圳市天工测控技术有限公司 | Detection circuit and detection method of WiFi module |
| CN110471807A (en) * | 2019-07-25 | 2019-11-19 | 广州朗国电子科技有限公司 | Hardware fault detection method, system, storage medium and integrated machine equipment |
| CN112817807B (en) * | 2020-02-28 | 2023-07-14 | 加特兰微电子科技(上海)有限公司 | Chip detection method, device and storage medium |
| CN111913471A (en) * | 2020-07-21 | 2020-11-10 | 北京京瀚禹电子工程技术有限公司 | Testing device |
| CN113567843B (en) * | 2021-07-20 | 2023-12-12 | 天津津航计算技术研究所 | Circuit board active path testing method based on FPGA |
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