CN105138487A - Built-out card CPLD/FPGA program downloading method - Google Patents
Built-out card CPLD/FPGA program downloading method Download PDFInfo
- Publication number
- CN105138487A CN105138487A CN201510529999.3A CN201510529999A CN105138487A CN 105138487 A CN105138487 A CN 105138487A CN 201510529999 A CN201510529999 A CN 201510529999A CN 105138487 A CN105138487 A CN 105138487A
- Authority
- CN
- China
- Prior art keywords
- card
- cpld
- outer plug
- fpga program
- built
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Abstract
The invention discloses a built-out card CPLD/FPGA program downloading method, and belongs to the field of program downloading methods. According to the structure, a testing jig with a PCIE interface, built-out cards with PCIE interfaces, a testing host with a PCIE interface and a CPLD/FPGA program downloader are included, the testing jig comprises a switching control unit, a many-way selection switching circuit is adopted in the switching control unit, a dial switch triggers control, and JTAG signals of the downloader are switched to all the built-out cards in sequence. The method aims at application scenarios that multiple built-out cards are inserted in at the same time, the JTAG program downloader does not need to be pulled and plugged many times after being connected with the jig, programmable logic devices of all the built-out cards are switched in a dial-up mode for program downloading, working efficiency is improved, and the service life of a cable is prolonged.
Description
Technical field
The present invention relates to a kind of program down-loading method, specifically a kind of outer plug-in card CPLD/FPGA program down-loading method.
Background technology
At present, in server product, PCIE outer plug-in card is widely used, and comes practical function expansion and performance boost, as: network interface card, GPU video card, SAS/Raid card, optical fiber HBA card, infiniband card etc.These high performance outer plug-in cards often integrated level are very high, need the complicated logical sequence such as power-on and power-off, reset.This makes the programmable logic device (PLD) such as CPLD/FPGA be widely applied in the design of PCIE outer plug-in card.
In traditional program down-loading method, test platform is connected by golden finger with PCIE outer plug-in card, and CPLD Program download is connected with PCIE outer plug-in card jtag interface by JTAG flat wire.This method often download burning board need plug outer plug-in card once, need plug CPLD/FPGA downloader cable once, waste time and energy, easy loss cable, production efficiency is low.
summary of the invention
Technical assignment of the present invention is to provide a kind of outer plug-in card CPLD/FPGA program down-loading method, solves above technical matters.
The technical solution adopted for the present invention to solve the technical problems is: a kind of outer plug-in card CPLD/FPGA program down-loading method, it is characterized in that comprising the measurement jig with PCIE interface, the outer plug-in card with PCIE interface, with the Test Host of PCIE interface and CPLD/FPGA Program download, described measurement jig comprises switch control unit, described switch control unit adopts multi-path choice commutation circuit, toggle switch trigging control, the JTAG signal switching downloader arrives each outer plug-in card successively.
The up going port of described measurement jig is connected with the PCIE interface of Test Host, and down going port inserts at least one outer plug-in card.
Described CPLD/FPGA Program download one end is logical to be connected with PC, and the other end is connected with measurement jig by flat cable.
The PCIE interface of described Test Host is PCIEx16 or PCIEx8, and speed is GEN3.0.
Described switch control unit is connected with the CPLD of outer plug-in card by PCIE golden finger, and Test Host is connected with the controller of outer plug-in card by PCIE golden finger.
A kind of outer plug-in card CPLD/FPGA program down-loading method of the present invention compared to the prior art, there is following beneficial effect: the method is the application scenarios for once inserting multiple outer plug-in card simultaneously, repeatedly plug is no longer needed after JTAG Program download connection fixture, the programmable logic device (PLD) download program of each outer plug-in card is switched by dial-up, improve work efficiency, extend the serviceable life of cable.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the present invention is further described.
Accompanying drawing 1 is a kind of structured flowchart of outer plug-in card CPLD/FPGA program down-loading method.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
Embodiment 1
As shown in Figure 1, a kind of outer plug-in card CPLD/FPGA program down-loading method of the present invention, its structure comprises the measurement jig with PCIE interface, the outer plug-in card with PCIE interface, is Test Host and the CPLD/FPGA Program download of the PCIEx16 interface of GEN3.0 with speed, described measurement jig comprises switch control unit, described switch control unit adopts multi-path choice commutation circuit, toggle switch trigging control, the JTAG signal switching downloader arrives each outer plug-in card successively.The up going port of described measurement jig is connected with the PCIE interface of Test Host, and down going port inserts an outer plug-in card.Described CPLD/FPGA Program download one end is logical to be connected with PC, the other end is connected with measurement jig by flat cable, described switch control unit is connected with the CPLD of outer plug-in card by PCIE golden finger, and Test Host is connected with the controller of outer plug-in card by PCIE golden finger.
Embodiment 2
As shown in Figure 1, a kind of outer plug-in card CPLD/FPGA program down-loading method of the present invention, its structure comprises the measurement jig with PCIE interface, the outer plug-in card with PCIE interface, is Test Host and the CPLD/FPGA Program download of the PCIEx8 interface of GEN3.0 with speed, described measurement jig comprises switch control unit, described switch control unit adopts multi-path choice commutation circuit, toggle switch trigging control, the JTAG signal switching downloader arrives each outer plug-in card successively.The up going port of described measurement jig is connected with the PCIE interface of Test Host, and down going port inserts two outer plug-in cards.Described CPLD/FPGA Program download one end is logical to be connected with PC, the other end is connected with measurement jig by flat cable, described switch control unit is connected with the CPLD of outer plug-in card by PCIE golden finger, and Test Host is connected with the controller of outer plug-in card by PCIE golden finger.
The course of work is:
1, prepare and put up platform.Be connected with the PCIEx8 interface of Test Host by the up going port of measurement jig, down going port inserts 2 outer plug-in cards;
2, be connected with PC by USB cable CPLD/FPGA Program download one end, the other end is connected with the jtag interface of measurement jig by flat cable, opens download program software simultaneously;
3, the toggle switch of measurement jig is adjusted to first PCIE outer plug-in card; Now connect preliminary work to complete;
4, start powers on, and CPLD downloads;
5, test platform start powers on, and starts first board CPLD download program;
6, after having downloaded, toggle switch is switched to second PCIE outer plug-in card, carry out CPLD download program;
7, main control FW downloads;
Above-mentioned complete after power-off restarting, enter DOS environment, successively FW burning download carried out to two board master controllers;
8, functional test, after above operation completes, carries out functional test to board; After functional test PASS, board is pulled up and changes another 2 boards download, test.
By embodiment above, described those skilled in the art can be easy to realize the present invention.But should be appreciated that the present invention is not limited to above-mentioned embodiment.On the basis of disclosed embodiment, described those skilled in the art can the different technical characteristic of combination in any, thus realizes different technical schemes.
Claims (5)
1. an outer plug-in card CPLD/FPGA program down-loading method, it is characterized in that comprising the measurement jig with PCIE interface, the outer plug-in card with PCIE interface, with the Test Host of PCIE interface and CPLD/FPGA Program download, described measurement jig comprises switch control unit, described switch control unit adopts multi-path choice commutation circuit, toggle switch trigging control, the JTAG signal switching downloader arrives each outer plug-in card successively.
2. a kind of outer plug-in card CPLD/FPGA program down-loading method according to claim 1, it is characterized in that the up going port of described measurement jig is connected with the PCIE interface of Test Host, down going port inserts at least one outer plug-in card.
3. a kind of outer plug-in card CPLD/FPGA program down-loading method according to claim 1, it is characterized in that described CPLD/FPGA Program download one end is logical and be connected with PC, the other end is connected with measurement jig by flat cable.
4. a kind of outer plug-in card CPLD/FPGA program down-loading method according to claim 1 and 2, it is characterized in that the PCIE interface of described Test Host is PCIEx16 or PCIEx8, speed is GEN3.0.
5. a kind of outer plug-in card CPLD/FPGA program down-loading method according to claim 3, is characterized in that described switch control unit is connected with the CPLD of outer plug-in card by PCIE golden finger, and Test Host is connected with the controller of outer plug-in card by PCIE golden finger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510529999.3A CN105138487A (en) | 2015-08-26 | 2015-08-26 | Built-out card CPLD/FPGA program downloading method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510529999.3A CN105138487A (en) | 2015-08-26 | 2015-08-26 | Built-out card CPLD/FPGA program downloading method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105138487A true CN105138487A (en) | 2015-12-09 |
Family
ID=54723839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510529999.3A Pending CN105138487A (en) | 2015-08-26 | 2015-08-26 | Built-out card CPLD/FPGA program downloading method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105138487A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105591839A (en) * | 2015-12-23 | 2016-05-18 | 浪潮集团有限公司 | Device, method and system of testing network exchange chip |
| CN106959932A (en) * | 2017-04-14 | 2017-07-18 | 广东浪潮大数据研究有限公司 | A kind of Riser card methods for designing of automatic switchover PCIe signals |
| CN107193752A (en) * | 2017-05-19 | 2017-09-22 | 郑州云海信息技术有限公司 | It is a kind of to solve the method that outer plug-in card memory address is not enough distributed |
| CN107943734A (en) * | 2017-12-14 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of more FPGA isomeries accelerator card debugging systems and its interface connecting method, system |
| CN108646172A (en) * | 2018-07-06 | 2018-10-12 | 郑州云海信息技术有限公司 | A kind of apparatus for testing chip |
| CN108880936A (en) * | 2018-06-07 | 2018-11-23 | 锐骐(厦门)电子科技有限公司 | A kind of communication module test system and communication module test method |
| CN112506172A (en) * | 2020-12-07 | 2021-03-16 | 天津津航计算技术研究所 | Multi-CPLD real-time monitoring device |
| CN112578723A (en) * | 2020-12-07 | 2021-03-30 | 天津津航计算技术研究所 | Redundancy CPLD switching control device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104778109A (en) * | 2015-04-28 | 2015-07-15 | 浪潮电子信息产业股份有限公司 | Program downloading system and method of PCIE/PCIX external plug-in card |
-
2015
- 2015-08-26 CN CN201510529999.3A patent/CN105138487A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104778109A (en) * | 2015-04-28 | 2015-07-15 | 浪潮电子信息产业股份有限公司 | Program downloading system and method of PCIE/PCIX external plug-in card |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105591839A (en) * | 2015-12-23 | 2016-05-18 | 浪潮集团有限公司 | Device, method and system of testing network exchange chip |
| CN106959932A (en) * | 2017-04-14 | 2017-07-18 | 广东浪潮大数据研究有限公司 | A kind of Riser card methods for designing of automatic switchover PCIe signals |
| CN107193752A (en) * | 2017-05-19 | 2017-09-22 | 郑州云海信息技术有限公司 | It is a kind of to solve the method that outer plug-in card memory address is not enough distributed |
| CN107943734A (en) * | 2017-12-14 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of more FPGA isomeries accelerator card debugging systems and its interface connecting method, system |
| CN107943734B (en) * | 2017-12-14 | 2021-06-29 | 郑州云海信息技术有限公司 | Multi-FPGA heterogeneous accelerator card debugging system and interface connection method and system thereof |
| CN108880936A (en) * | 2018-06-07 | 2018-11-23 | 锐骐(厦门)电子科技有限公司 | A kind of communication module test system and communication module test method |
| CN108880936B (en) * | 2018-06-07 | 2020-09-15 | 锐骐(厦门)电子科技有限公司 | Communication module test system and communication module test method |
| CN108646172A (en) * | 2018-07-06 | 2018-10-12 | 郑州云海信息技术有限公司 | A kind of apparatus for testing chip |
| CN108646172B (en) * | 2018-07-06 | 2020-08-18 | 苏州浪潮智能科技有限公司 | Chip testing device |
| CN112506172A (en) * | 2020-12-07 | 2021-03-16 | 天津津航计算技术研究所 | Multi-CPLD real-time monitoring device |
| CN112578723A (en) * | 2020-12-07 | 2021-03-30 | 天津津航计算技术研究所 | Redundancy CPLD switching control device |
| CN112506172B (en) * | 2020-12-07 | 2022-09-30 | 天津津航计算技术研究所 | Multi-CPLD real-time monitoring device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105138487A (en) | Built-out card CPLD/FPGA program downloading method | |
| CN104778109B (en) | Program downloading system and method of PCIE/PCIX external plug-in card | |
| CN210006040U (en) | expansion cards | |
| CN107783871B (en) | USB signal consistency code type switcher and testing system | |
| CN101102566B (en) | A design method and debugging method for mobile phone JTAG debugging interface signals | |
| CN101950265B (en) | Method for CPU board card program downloading and hardware online detection and plug-in connector | |
| CN101666855B (en) | Universal test system and method of integrated circuit | |
| CN102854417B (en) | Master test board and testing method thereof | |
| US20130166954A1 (en) | Test apparatus for testing signal transmission of motherboard | |
| CN105490844A (en) | PCIe port reconstruction method | |
| CN102761624B (en) | Method and device for debugging Internet access out of panel | |
| CN112073213A (en) | Method for flexibly and safely configuring PCIe switch | |
| CN103440148A (en) | Device and method for programming multiple single-chip microcomputer programs | |
| CN107329863B (en) | General hardware platform of measuring instrument based on COMe | |
| CN204331370U (en) | Single Chip Microcomputer (SCM) program cd-rom recorder and system | |
| CN105487906A (en) | Method and system for updating MCU core code by plug-in FLASH | |
| CN209433397U (en) | Multichannel usb signal switching device | |
| CN201429842Y (en) | Code downloading system using JTAG method | |
| CN103984243A (en) | Single-chip microcomputer program downloading, debugging and simulating system | |
| CN209072452U (en) | A kind of signal conversion circuit | |
| CN110708403A (en) | Circuit and method for automatically configuring MAC address of network card by utilizing single chip microcomputer | |
| CN203882315U (en) | Network physical isolation device | |
| CN113630294B (en) | Switch modularization detection method and device | |
| CN209151305U (en) | The core board circuit of the small base station of integration | |
| CN107395190B (en) | Circuit and driving system for rapidly responding to fault signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151209 |
|
| RJ01 | Rejection of invention patent application after publication |