CN209151305U - The core board circuit of the small base station of integration - Google Patents

Abstract

The utility model discloses a kind of core board circuits of small base station of integration, comprising: baseband processing chip, the baseband processing chip are configured with the Serial Peripheral Interface (SPI) of GPIO simulation；First FLASH is connected by Serial Peripheral Interface (SPI) with the GPIO Serial Peripheral Interface (SPI) simulated；On-site programmable gate array FPGA is connected with the GPIO interface of the baseband processing chip, and is connected with the Serial Peripheral Interface (SPI) of the first FLASH；Controller, the input interface of the controller are connected with the baseband processing chip；2nd FLASH is connected by Serial Peripheral Interface (SPI) with the output interface of the controller；And Ethernet switch, it is connected with the GPIO interface of the baseband processing chip, and be connected with the Serial Peripheral Interface (SPI) of the 2nd FLASH.The core circuit plate of the small base station of integration provided by the utility model may be implemented circuit design and not limited by Serial Peripheral Interface (SPI), saves cost, reduces the size of circuit, improve circuit reliability.

Description

The core board circuit of the small base station of integration

Technical field

The utility model is about a kind of core board circuit, especially with regard to the core board circuit of the small base station of integration.

Background technique

As technology constantly improves, the various businesses of national grid electric system are to efficient and intelligent development, integrally Change small base station to be gradually applied.

The small base station of integration is mainly made of four parts: core board, power amplifier, power supply and structural housing form.Core board master It realizes base band signal process and RF small signals transmission-receiving function, is the core component of base station.Core board mainly includes at base band Manage chip, RF transceiver, field programmable gate array (full name in English: Field-Programmable Gate Array, English Text abbreviation: FPGA) and the components such as Ethernet switch.Baseband processing chip and RF transceiver pass through Serial Peripheral Interface (SPI) (English Literary full name: Serial Peripheral Interface, english abbreviation: SPI) realize communication.

Existing communications baseband processing chip is gathered around there are two SPI interface, and one is read BOOT ROM when starting for system In configuration information, another is for controlling RF transceiver.And baseband processing chip, FPGA and Ethernet switch also need The configuration file or firmware that read by SPI interface in flash memory FLASH are configured, therefore the SPI interface circuitry of core board Design is the key that core board hardware design.SPI is usually worked with master slave mode, this mode usually support a main equipment and One or more is from equipment.Its interface is generally made of 4 lines, is SDI, SDO, SCK and CS respectively.

Referring to Fig. 1, it is existing core board electrical block diagram, at present for FPGA and Ethernet switch into The solution of row edition upgrading is, since the limitation of SPI interface needs to increase in core board two 8 switch chips, And baseband processing chip is required to increase two or more SPI controllers, it is carried out with completing FPGA and Ethernet switch Edition upgrading.

Based on this, the inventors of the present application found that current baseband processing chip includes two 8 switch chips and electricity Road design is complicated, high to the hardware resource requirements of baseband processing chip, causes baseband processing chip hardware cost high.

The information disclosed in the background technology section is intended only to increase the understanding to the general background of the utility model, and It is not construed as recognizing or implying in any form that information composition is already known to those of ordinary skill in the art existing Technology.

Utility model content

The purpose of this utility model is to provide a kind of core board circuits of small base station of integration, can reduce at base band Manage the cost of chip.

To achieve the above object, the core board circuit that the utility model provides a kind of small base station of integration includes: base band Chip is handled, the baseband processing chip is configured with the Serial Peripheral Interface (SPI) of GPIO simulation；First FLASH, passes through serial peripheral Interface is connected with the GPIO Serial Peripheral Interface (SPI) simulated；On-site programmable gate array FPGA, with the Base-Band Processing core The GPIO interface of piece is connected, and is connected with the Serial Peripheral Interface (SPI) of the first FLASH, wherein stores in the first FLASH There is the configuration file of the FPGA；Controller, the input interface of the controller are connected with the baseband processing chip；Second FLASH is connected by Serial Peripheral Interface (SPI) with the output interface of the controller；And Ethernet switch, with the base band The GPIO interface of processing chip is connected, and is connected with the Serial Peripheral Interface (SPI) of the 2nd FLASH, wherein the 2nd FLASH In be stored with the firmware of the Ethernet switch.

In a preferred embodiment, the GPIO interface of the control interface of the controller and the baseband processing chip It is connected, the input interface of the controller is connected with the GPIO of the baseband processing chip Serial Peripheral Interface (SPI) simulated.

In a preferred embodiment, the controller is 4 bit switches.

Compared with prior art, the core circuit plate of the small base station of integration according to the present utility model may be implemented circuit and set Meter is not limited by spi bus interface, and application range is wider, simplifies design, and reduces the quantity of controller to save Cost has been saved, the size of circuit has been reduced, improves circuit reliability.

Detailed description of the invention

Fig. 1 is according to the existing core board electrical block diagram of the utility model.

Fig. 2 is the structural representation according to a kind of core board circuit of small base station of integration of one embodiment of the utility model Figure.

Fig. 3 is the upgrading flow chart according to the small base station of integration of one embodiment of the utility model.

Main appended drawing reference explanation:

1- baseband processing chip, 2-FPGA, 3- controller, 4- Ethernet switch, 5- the first FLASH, 6- second FLASH。

Specific embodiment

With reference to the accompanying drawing, specific embodiment of the present utility model is described in detail, it is to be understood that this is practical Novel protection scope is not limited by the specific implementation.

Unless otherwise explicitly stated, otherwise in entire disclosure and claims, term " includes " or its change Changing such as "comprising" or " including " etc. will be understood to comprise stated element or component, and not exclude other members Part or other component parts.

As shown in Fig. 2, according to a kind of core board circuit of small base station of integration of the preferred embodiments of the present invention Structural schematic diagram, comprising: baseband processing chip 1, on-site programmable gate array FPGA 2, controller 3, Ethernet switch 4, One FLASH5 and the 2nd FLASH6.

Baseband processing chip 1 is configured with the Serial Peripheral Interface (SPI) of GPIO simulation.

First FLASH5 is connected by serial peripheral equipment interface SPI with the GPIO serial peripheral equipment interface SPI simulated.

On-site programmable gate array FPGA 2 is connected with the GPIO interface of the baseband processing chip 1, and with described The serial peripheral equipment interface SPI of one FLASH5 is connected, wherein the configuration file of the FPGA is stored in the first FLASH5.

Controller 3, the input interface of the controller 3 are connected with the baseband processing chip 1；Wherein, the control Device can be 4 bit switches or data selector MUX.The GPIO of the control interface of the controller 3 and the baseband processing chip 1 Interface is connected, and the input interface of the controller 3 is connected with the GPIO of the baseband processing chip 1 SPI interface simulated.

2nd FLASH6 is connected by serial peripheral equipment interface SPI with the output interface of the controller 3.

Ethernet switch 4 is connected with the GPIO interface of the baseband processing chip 1, and the string with the 2nd FLASH6 Row Peripheral Interface SPI is connected, wherein the firmware of the Ethernet switch 4 is stored in the 2nd FLASH6.

Baseband processing chip 1 is also connected by SPI interface with RF transceiver.

It is not total by SPI that circuit design may be implemented in the core circuit plate of the small base station of integration provided in this embodiment as a result, The limitation of line interface, application range is wider, simplifies design, and reduces the quantity of controller to save cost, subtracts The small size of circuit, improves circuit reliability.

As shown in figure 3, according to the upgrading flow chart of the small base station of integration of the preferred embodiments of the present invention.

Specifically, system electrification moment, the GPIO that communications baseband processing chip 1 connects FPGA2 and the first FLASH5 are in High-impedance state, 4 bit switches are in high resistant and off-state, and FPGA2 reads configuration file from the first FLASH5, Ethernet exchanging Machine 4 reads firmware from the 2nd FLASH6, completes device configuration.

When system needs to update FPGA configuration file, baseband processing chip 1 passes through GPIO for the PROGRAM_B of FPGA2 Pin is set low, and FPGA is made to be in reseting logic state, and the SPI interface of FPGA2 is in high-impedance state.Baseband processing chip 1 passes through GPIO control switch 3 makes the pin of switch 3 be in high-impedance state.Baseband processing chip 1 is connected by the SPI interface that GPIO is simulated The first FLASH5 is met, FPGA configuration file therein is updated.After update, baseband processing chip 1 will be by that will be used to simulate SPI GPIO be set to high-impedance state, the PROGRAM_B pin of FPGA2 is then set into height, FPGA starts to download in the first FLASH5 Configuration file, the configuration file for completing FPGA2 update.

When system needs to update 4 firmware of Ethernet switch, baseband processing chip 1 will by GPIO FPGA2PROGRAM_B pin is set low, and FPGA is made to be in reseting logic state, and the SPI interface of FPGA is in high-impedance state.Base band Chip 1 is handled by GPIO control switch 3, keeps the pin of switch 3 in the conductive state.Baseband processing chip 1 will by GPIO The reseting pin of Ethernet switch 4 is set low, and is at reset state, and the SPI interface of Ethernet switch is in high resistant shape State.Communications baseband handles chip 1 and is connected to switch 3 by the SPI interface that GPIO is simulated, and is then connected to second again FLASH6 updates Ethernet switch firmware therein.After update, switch 3 is set to by baseband processing chip 1 by GPIO Disconnection and high-impedance state, then set height for the reseting pin of Ethernet switch 4, Ethernet switch 4 starts downloading second Firmware in FLASH6 completes 4 firmware update of Ethernet switch.

The problem of can achieve online updating system equipment firmware using GPIO simulation SPI interface as a result,.Solves system Dedicated hardware SPI interface lazy weight and multiple SPI main equipments mutual switching problem in the same spi bus interface.Circuit Whether design is not supported that spi bus interface is limited by MCU hardware resource, and application range is wider, simplifies design, is reduced pair The demand of MCU.A switch chip has been used less, has saved cost, is reduced the size of circuit, is improved circuit reliability.? It is connected to 3 main equipments on one spi bus circuit and 2 are realized main set by the design of timing and switching circuit from equipment Standby access is accordingly from the demand of equipment.

The description of the aforementioned specific exemplary embodiment to the utility model is in order to illustrate and illustration purpose.These Description is not wishing to for the utility model to be limited to disclosed precise forms, and it will be apparent that according to the above instruction, can carry out It is many to change and change.The purpose of selecting and describing the exemplary embodiment is that explaining the specific principle of the utility model And its practical application, so that those skilled in the art can be realized and utilize a variety of different examples of the utility model Property embodiment and various chooses and changes.The scope of the utility model is intended to by claims and its waits similar shapes Formula is limited.

Claims (3)

1. a kind of core board circuit of the small base station of integration characterized by comprising

Baseband processing chip, the baseband processing chip are configured with the Serial Peripheral Interface (SPI) of GPIO simulation；

First FLASH is connected by Serial Peripheral Interface (SPI) with the GPIO Serial Peripheral Interface (SPI) simulated；

On-site programmable gate array FPGA is connected with the GPIO interface of the baseband processing chip, and with the first FLASH Serial Peripheral Interface (SPI) be connected, wherein the configuration file of the FPGA is stored in the first FLASH；

Controller, the input interface of the controller are connected with the baseband processing chip；

2nd FLASH is connected by Serial Peripheral Interface (SPI) with the output interface of the controller；With

Ethernet switch is connected with the GPIO interface of the baseband processing chip, and connects with the serial peripheral of the 2nd FLASH Mouth is connected, wherein the firmware of the Ethernet switch is stored in the 2nd FLASH.

2. core board circuit as described in claim 1, which is characterized in that at the control interface of the controller and the base band The GPIO interface of reason chip is connected, and the GPIO of the input interface of the controller and the baseband processing chip simulates serial Peripheral Interface is connected.

3. core board circuit as described in claim 1, which is characterized in that the controller is 4 bit switches.