CN210573287U - Expansion circuit - Google Patents
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- CN210573287U CN210573287U CN201921477721.6U CN201921477721U CN210573287U CN 210573287 U CN210573287 U CN 210573287U CN 201921477721 U CN201921477721 U CN 201921477721U CN 210573287 U CN210573287 U CN 210573287U
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Abstract
The application discloses extension circuit includes: the first conversion equipment is connected with a first interface of the mainboard and used for converting the first interface into at least two serial ports, wherein each serial port in the at least two serial ports has two working modes, and the two working modes comprise: the first interface is used for allocating an exclusive channel bandwidth to the expansion circuit; the at least two level converters are connected with the at least two serial ports one by one and are used for converting first levels of the at least two serial ports into second levels, wherein the second levels are working levels of the two working modes; and the mode control circuit is respectively connected with the second interface of the mainboard and the at least two level converters and is used for controlling the working mode of each serial port, and the second interface is used for transmitting data signals and clock signals between the expansion circuit and the mainboard. The application solves the technical problems that in the prior art, in the application of multiple serial ports, the working mode of the serial ports is single, and the application scenes of multiple industrial fields cannot be adapted to.
Description
Technical Field
The present application relates to the field of circuits, and in particular, to an expansion circuit.
Background
Along with more and more intelligent substation's construction of starting a job and putting into operation, intelligent substation construction has become the mainstream in market, put forward more demands to the hardware function integration of data communication net shutdown machine in the intelligent substation, physical address, passageway address or parameter name etc. to the data equipment that will gather, can be set for by the user independently, after the user accomplishes configuration, can download the engineering that the configuration is good to hardware equipment in, and the gateway operation procedure in the hardware equipment of can long-rangely starting, to the data in the hardware equipment of having gathered, industry communication platform operation procedure can carry out various operations with various modes, include: data transformation, data filtering, arithmetic processing, historical data storage, statistical processing, alarm processing, service request and the like.
The work that industrial communication platforms need to do is increasing, but the size requirement of the whole industrial communication platform is also decreasing.
The existing industrial communication platforms mainly comprise the following 3 types: a, a single-network-port multi-serial-port industrial communication platform. And b, a multi-path network port two-path serial port industrial communication platform. And c, a multi-network-port and multi-serial-port industrial communication platform. With the increasing requirement for the networking of the communication platform in the construction of the intelligent substation, the existing industrial communication platform implementation method has the following defects: a, a single-network-port multi-serial-port industrial communication platform, wherein the number of network communication interfaces is only one, and the requirement of more and more communication interfaces cannot be met; b, the industrial communication platform with the two serial ports and the multi-path network port can meet the requirement of more and more communication interfaces, but the industrial communication platform has more limitation on application scenes in an industrial field due to the small number of the serial ports and cannot be popularized in a large scale; and c, the multi-network-port and multi-serial-port industrial communication platform can meet the requirements of more and more communication interfaces and the application requirements of an industrial field on the number of serial ports, but the working mode of the serial ports is an RS232 mode or an RS485 mode, and the industrial communication platform cannot adapt to various use scenes of the industrial field.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the application provides an extension circuit, and the technical problem that in the prior art, in the application of multiple serial ports, the working mode of the serial ports is single, and the application scenes of multiple industrial fields cannot be adapted is solved.
According to an aspect of an embodiment of the present application, there is provided an expansion circuit including: the first conversion equipment is connected with a first interface of the mainboard and used for converting the first interface into at least two serial ports, wherein each serial port in the at least two serial ports has two working modes, and the two working modes comprise: the first interface is used for allocating an exclusive channel bandwidth to the expansion circuit; the at least two level converters are connected with the at least two serial ports one by one and are used for converting first levels of the at least two serial ports into second levels, wherein the second levels are working levels of the two working modes; and the mode control circuit is respectively connected with the second interface of the mainboard and the at least two level converters and is used for controlling the working mode of each serial port, and the second interface is used for transmitting data signals and clock signals between the expansion circuit and the mainboard.
Optionally, the mode control circuit includes at least two control interfaces, and the at least two control interfaces are connected to the at least two level shifters one to one.
Optionally, the expansion circuit comprises: and the terminal is connected with the at least two level converters and is used for transmitting data corresponding to the two working modes.
Optionally, the expansion circuit comprises: and the connecting circuit is connected with the first conversion equipment, the mode control circuit and the at least two level converters and is used for controlling the at least two level converters to convert the first level into the second level based on a first control instruction sent by the mode control circuit.
Optionally, the connection circuit comprises: the first connection pin is connected with the first conversion equipment and used for forwarding the data sent by the connection circuit to the first conversion equipment; the second connecting pin is connected with the first conversion equipment and used for forwarding the data sent by the first conversion equipment to the connecting circuit; the third connecting pin is connected with the level converter and used for forwarding the data sent by the connecting circuit to the level converter when the working mode of the serial port is an unbalanced transmission mode; the fourth connecting pin is connected with the level shifter and used for forwarding the data sent by the level shifter to the connecting circuit when the working mode of the serial port is an unbalanced transmission mode; the fifth connecting pin is connected with the level shifter and used for forwarding the data sent by the connecting circuit to the level shifter when the working mode of the serial port and the level shifter is a balanced transmission mode; the sixth connecting pin is connected with the level shifter and used for forwarding the data sent by the level shifter to the connecting circuit when the working mode of the serial port is a balanced transmission mode; a seventh connection pin, connected to the mode control circuit, for forwarding the first control instruction to the connection circuit; and the eighth connecting pin is connected with the seventh connecting pin through a first inverting circuit and used for forwarding the inverted first control instruction to the connecting circuit.
Optionally, the expansion circuit comprises: the first inverting circuit; and a first input end of the first inverting circuit is connected with the seventh connecting pin, and a first output end of the first inverting circuit is connected with the eighth connecting pin and used for inverting the level of the first input end.
Optionally, the level shifter comprises: the first conversion pin is connected with the third connection pin and used for forwarding the data sent by the connection circuit to the level converter when the working mode of the serial port is an unbalanced transmission mode; the second conversion pin is connected with the fourth connection pin and used for forwarding the data sent by the level converter to the connection circuit when the working mode of the serial port is an unbalanced transmission mode; the third conversion pin is connected with the fifth connection pin and used for forwarding the data sent by the connection circuit to the level converter when the working mode of the serial port and the third connection pin is a balanced transmission mode; the fourth conversion pin is connected with the sixth connection pin and used for forwarding the data sent by the level converter to the connection circuit when the working mode of the serial port and the fourth connection pin is a balanced transmission mode; the first pin is connected with the mode control circuit and used for adjusting the working mode of the serial port based on a second control instruction sent by the mode control circuit; and the second pin is connected with the first pin through a second inverting circuit and used for forwarding the inverted second control instruction to the level shifter.
Optionally, the expansion circuit comprises: the second inverting circuit; and a second input end of the second inverting circuit is connected with the first pin, and a second output end of the second inverting circuit is connected with the second pin and used for inverting the level of the second input end.
Optionally, the expansion circuit comprises: and the second conversion equipment is connected with a third interface of the mainboard and used for converting the third interface into two paths of gigabit network ports, and the third interface is used for allocating an exclusive channel bandwidth for the expansion circuit.
Optionally, the second conversion device comprises: a PCIE expander, configured to expand the third interface into two PCIE interfaces; the expansion circuit further comprises two network controllers, wherein each network controller is connected with one PCIE interface and one RJ45 interface in the two PCIE interfaces.
In the embodiment of the present application, the method includes: the first conversion equipment is connected with a first interface of the mainboard and used for converting the first interface into at least two serial ports, wherein each serial port in the at least two serial ports has two working modes, and the two working modes comprise: the first interface is used for allocating an exclusive channel bandwidth to the expansion circuit; the at least two level converters are connected with the at least two serial ports one by one and are used for converting first levels of the at least two serial ports into second levels, wherein the second levels are working levels of the two working modes; the mode control circuit is respectively connected with the second interface of the mainboard and the at least two level converters and used for controlling the working mode of each serial port, the second interface is used for the expansion circuit for transmitting data signals and clock signals between the expansion circuit and the mainboard, so that the multi-serial port with the unbalanced transmission mode and the balanced transmission mode can be flexibly configured, the technical effect of adaptability of various use scenes of the multi-serial port in an industrial field is improved, and the technical problem that in the prior art, in the application of the multi-serial port, the working mode of the serial port is single and the application scenes of the multi-serial port cannot be adapted to the various industrial fields is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of an expansion circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an expansion circuit according to an embodiment of the present application;
FIG. 3a is a circuit schematic of a connection circuit according to an embodiment of the present application;
FIG. 3b is a schematic diagram of a first inverting circuit according to an embodiment of the present application;
FIG. 4a is a schematic diagram of a level shifter according to an embodiment of the present application;
FIG. 4b is a schematic diagram of a structure of a level shifter according to an embodiment of the present application;
fig. 4c is a schematic structural diagram of a second inverter circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic structural diagram of an expansion circuit according to an embodiment of the present application, and as shown in fig. 1, the expansion circuit includes: a first switching device 12, a mode control circuit 14, at least two level shifters 160, 162 …; wherein:
the first conversion device 12 is connected to the first interface of the motherboard 10, and configured to convert the first interface into at least two serial ports, where two working modes exist in each serial port of the at least two serial ports, where the two working modes include: the first interface is used for allocating an exclusive channel bandwidth to the expansion circuit;
the at least two level shifters 160 and 162 …, the at least two level shifters 160 and 162 … are connected to the at least two serial ports one by one, and are configured to convert a first level of the at least two serial ports into a second level, where the second level is an operating level of the two operating modes, that is, the second level is an RS-232 mode level or an RS-485 mode level.
A mode control circuit 14, connected to the second interface of the motherboard 10 and the at least two level shifters 160 and 162 … respectively, for controlling the operating mode of each serial port, where the second interface is used to transmit data signals and clock signals between the expansion circuit and the motherboard 10.
In some optional embodiments of the present application, the first interface may be a PCIE interface for transmitting PCIE data, the second interface may be an I2C interface for transmitting I2C data, the serial port may be a Uart serial port, the unbalanced transmission mode may be an RS-232 mode, and the balanced transmission mode may be an RS-485 mode.
Alternatively, the first conversion device 12 may be an AX99100 chip, the mode control circuit 14 may be an F75111RG chip, and the level shifter 160 and the level shifter 162 may be an SP338 chip.
In the application, the expansion circuit converts a 12V to 36V wide-voltage input direct-current power supply into a 9.4V direct-current power supply through the TPS40056PWP power management chip, and the maximum voltage can be provided for the mainboard by 10A.
FIG. 2 is a schematic diagram of an expansion circuit according to an embodiment of the present application, as shown in FIG. 2 in conjunction with FIG. 1;
alternatively, the first conversion device 12 may convert the first interface into 4 serial ports, where the 4 serial ports may be 4 Uart serial ports, and the expansion circuit may include 4 level shifters, such as the level shifter 160, the level shifter 162, the level shifter 164, and the level shifter 166 in fig. 2, where each level shifter may be an SP338 chip. Optionally, the level shifter 160, the level shifter 162, the level shifter 164, and the level shifter 166 convert 4 UART serial ports into 4 COM serial ports.
Optionally, the mode control circuit 14 includes at least two control interfaces, such as 4 GPIO interfaces in fig. 2, and the at least two control interfaces are connected to the at least two level shifters one by one.
Alternatively, the mode control circuit 14 may include 4 control interfaces, and the 4 control interfaces are connected to the 4 level shifters one by one.
Optionally, the expansion circuit comprises: and a terminal 28 connected to the at least two level shifters and configured to transmit data corresponding to the two operation modes, that is, data corresponding to the two operation modes of RS-232 and RS-485.
Optionally, the expansion circuit comprises: and the second conversion device 210 is connected to a third interface of the motherboard, and is configured to convert the third interface into two gigabit ports, where the third interface is configured to allocate an exclusive channel bandwidth to the expansion circuit. The third interface may be a PCIE interface and is configured to transmit PCIE data. Optionally, the second conversion device 210 includes: a PCIE expander, configured to expand the third interface into two PCIE interfaces; the expansion circuit further includes two network controllers, such as the network controller 212 and the network controller 214 in fig. 2, where each network controller connects one of the two PCIE interfaces with one RJ45 interface, and the RJ45 interface may be an interface of the RJ45 connector 216 or the RJ45 connector 218. The second conversion device 210 may be an ASM1182e chip.
In the application, the PCIE interface provided by the mainboard has two paths, each path of PCIE is a channel, two paths of kilomega network ports and 4 paths of serial ports need to be generated, wherein the 4 paths of serial ports can be selected from RS-232 or RS-485 in a software configuration mode, and the 120 omega terminal resistor of the RS-485 can be hooked in a software configuration mode. As shown in fig. 2, each road network port needs to have one PCIE signal, and 4 serial port signals can be obtained by converting one PCIE. The ASM1182e has clock expansion, a clock buffer does not need to be added, and the PCB space and the component cost are effectively controlled in the application of PCIE division into two parts; the gigabit network port selects i211, two paths of PCIE signals expanded by ASM1182e are connected to two i211, two gigabit network ports are generated, the i211 has a storage space, an external flash memory is not required to be added, and a nonvolatile memory and an MAC address can be directly burned into an i211 chip; the PCIE-to-serial port is selected from AX99100, and one path of PCIe signal is converted into 4 paths of UART; and F75111RG is selected as GPIO extension, and GPIO is extended through I2C, so that the serial port working mode is flexibly controlled. AX99100 has 8 middle-level operating modes, and 4 serial port mode 4S is selected for this application, can be respectively for pull-down, pull-up to three configuration ports selected in advance. One PCIE signal is converted out of the 4 UART through the AX 99100.
In some optional embodiments of the present application, the PCIE expander may be an ASM1182e chip, and the third interface is a PCIE interface on the motherboard; the network controller 212 and the network controller 214 may be I211 ports.
Next, the first conversion device 12, the second conversion device 210, and the mode control circuit 14 may be connected to the motherboard through the connection unit 20, and the connection unit 20 may be a SAMTEC connector.
Optionally, the expansion circuit comprises: fig. 3a is a circuit diagram of the connection circuit 30 according to an embodiment of the present application, and fig. 3a is a circuit diagram of the connection circuit 30, which is combined with fig. 1 and fig. 2;
the connection circuit 30 is connected to the first switching device 12, the mode control circuit 14, and the at least two level shifters 160, 162 …, and is configured to control the at least two level shifters to switch the first level to the second level based on a first control instruction sent by the mode control circuit 14.
In some alternative embodiments of the present application, the connection circuit 30 may be an SN74CBT3125PMR chip.
In some alternative embodiments of the present application, in fig. 3a, the connection circuit 30 includes: a first connection pin 32, connected to the first conversion device 12, and configured to forward the data sent by the connection circuit 30 to the first conversion device 12; a second connection pin 34, connected to the first conversion device 12, for forwarding the data sent by the first conversion device 12 to the connection circuit 30; a third connection pin 36, connected to the level shifter, for forwarding the data sent by the connection circuit 30 to the level shifter when the operating mode of the serial port is an unbalanced transmission mode; a fourth connection pin 38, connected to the level shifter, for forwarding the data sent by the level shifter to the connection circuit 30 when the operating mode of the serial port is an unbalanced transmission mode; a fifth connection pin 310, connected to the level shifter, for forwarding the data sent by the connection circuit 30 to the level shifter when the working mode of the serial port is a balanced transmission mode; a sixth connection pin 312, connected to the level shifter, for forwarding the data sent by the level shifter to the connection circuit 30 when the working mode of the serial port is a balanced transmission mode; a seventh connection pin 314, connected to the mode control circuit 14, for forwarding the first control instruction to the connection circuit 30; an eighth connection pin 316, connected to the seventh connection pin 314 through a first inverting circuit, for forwarding the inverted first control instruction to the connection circuit 30. The first control instruction may be a level signal.
Alternatively, the first connection pin 32 may be pin 2 and pin 5 in the SN74CBT3125PMR chip;
alternatively, the second connection pin 34 may be pin 9 and pin 12 in the SN74CBT3125PMR chip;
alternatively, the third connection pin 36 may be pin 3 in the SN74CBT3125PMR chip;
alternatively, the fourth connection pin 38 may be pin 8 in the SN74CBT3125PMR chip;
alternatively, the fifth connection pin 310 may be pin 6 in the SN74CBT3125PMR chip;
alternatively, the sixth connection pin 312 may be pin 11 in the SN74CBT3125PMR chip;
alternatively, the seventh connection pin 314 may be pin 1 and pin 10 in the SN74CBT3125PMR chip;
alternatively, the eighth connection pin 316 may be pin 4 and pin 13 in the SN74CBT3125PMR chip;
alternatively, pin 7 of the SN74CBT3125PMR chip is connected to ground, and pin 14 is connected to a 5V power supply.
Fig. 3b is a schematic structural diagram of a first inverter circuit, and optionally, the expansion circuit includes the first inverter circuit 300 in fig. 3 b; the first input 318 of the first inverter circuit 300 is connected to the seventh connection pin 314, and the first output 320 of the first inverter circuit 300 is connected to the eighth connection pin 316, for inverting the level of the first input 318.
Alternatively, the first inverter circuit 300 may be an NC7SZ04 chip, the first input 318 may be pin 2 of an NC7SZ04 chip, the first output 320 may be pin 4 of an NC7SZ04 chip, and then pin 3 and pin 5 of an NC7SZ04 chip are connected to ground and 5V is connected to a power supply.
In some optional embodiments of the present application, the serial port designed in the present application may perform switching between two operating modes, which are RS-232 and RS-485, and all the following are described as any serial port COM serial port, as shown in fig. 3a and fig. 3B, switching is performed by an SN74CBT3125PWR chip at the UART signal stage, when the level of the seventh connection pin 314 is high, the level of the eighth connection pin 316 obtained through the first inverse circuit 300 is low, that is, OE2 and OE4 are low, port 2A is conducted with port 2B, port 4A is conducted with port 4B, the first connection pin 32 is conducted with the fifth connection pin 310, the second connection pin 34 is conducted with the sixth connection pin 312, and the COM serial port at this time is in the RS-485 operating mode; when the level of the seventh connection pin 314 is low, the level of the eighth connection pin 316 is high after passing through the first inverter circuit 300, that is, OE1 and OE3 are low, the port 1A is conducted with the port 1B, the port 3A is conducted with the port 3B, the first connection pin 32 is conducted with the third connection pin 36, the second connection pin 34 is conducted with the fourth connection pin 38, and the COM serial port at this time is in the RS-232 operating mode.
Optionally, one COM serial port corresponds to one Uart serial port.
Fig. 4a is a schematic structural diagram of a level shifter 40 according to an embodiment of the present application, and with reference to fig. 2 and fig. 3, in fig. 4a, the level shifter 40 includes: a first switch pin 42, connected to the third connection pin 36 in fig. 3a, for forwarding the data sent by the connection circuit 30 to the level shifter 40 when the operation mode of the serial port is an unbalanced transmission mode; a second conversion pin 44, connected to the fourth connection pin 38, for forwarding the data sent by the level shifter 40 to the connection circuit 30 when the operating mode of the serial port is an unbalanced transmission mode; a first pin 46, connected to the mode control circuit 14, for adjusting a working mode of the serial port based on a second control instruction sent by the mode control circuit 14; a second pin 48, connected to the first pin 46 through a second inverting circuit, for forwarding the inverted second control command to the level shifter 40. Of these, there are two second pins 48. Wherein, the second control instruction may be a level signal.
Alternatively, the level shifter 40 may be an SP338 chip, wherein,
the first switch pin 42 may be pin 6 in the SP338 chip;
the second switch pin 44 may be pin 8 in the SP338 chip;
the first pin 46 may be pin 14 in the SP338 chip;
the second pin 48 may be pin 15, pin 16 in the SP338 chip.
When the COM serial port is in the RS-232 operating Mode, the present application selects the operating Mode setting Mode [2:0] ═ 001 as shown in fig. 4a, that is, Mode2 ═ 0, Mode1 ═ 0, and Mode0 ═ 1 in fig. 4a, sets pin 16, pin 15, and pin 14 of SP338 to low, and high, connects the third connecting pin 36 in fig. 3a to the first transition pin 42 in fig. 4a, generates TX of RS-232 from pin 24, inputs RX of RS-232 from pin 21 in fig. 4a, and generates input of the fourth connecting pin 38 from the second transition pin 44. The level of the third connection pin 36 is converted into TX of RS232 through SP338 level, and RX of RS232 is converted into the level of the fourth connection pin 38 through SP338 level.
In fig. 4a, in the level shifter 40, inverters are connected between pins 1 and 31, between pins 2 and 30, between pins 3 and 28, between pins 4 and 27, between pins 5 and 25, between pins 6 and 24, between pins 7 and 22, and between pins 8 and 21, and pins 29, 26, 23, 10, and 36 are grounded. Pin 31 is connected to one end of a resistor with a resistance of 5k omega, and the other end of the resistor is grounded; the pin 30 is connected with one end of a resistor with the resistance value of 5k omega, and the other end of the resistor is grounded; pin 25 is connected to one end of a resistor with a resistance of 5k omega, and the other end of the resistor is grounded; the pin 22 is connected with one end of a resistor with the resistance value of 5k omega, and the other end of the resistor is grounded; pin 21 is connected to one end of a resistor having a resistance of 5k Ω, and the other end of the resistor is grounded.
The capacitance of the first capacitor 410 is 0.1 μ F, the capacitance of the second capacitor 412 is 0.1 μ F, and the capacitance of the third capacitor 414 is 0.1 μ F.
In fig. 4a, a data receiving end R1 is arranged on the side of the inverter between pin 31 and pin 1 near pin 31, and data is sent from pin 31 to pin 1;
a data receiving end R2 is arranged on the side, close to the pin 30, of the reverser between the pin 30 and the pin 2, and data are sent to the pin 2 from the pin 30;
a data sending end T1 is arranged on the side of the reverser between the pin 28 and the pin 3, which is close to the pin 3, and data is sent to the pin 28 from the pin 3;
a data sending end T2 is arranged on the side, close to the pin 4, of the reverser between the pin 27 and the pin 4, and data is sent to the pin 27 from the pin 4;
a data receiving end R3 is arranged on the side, close to the pin 25, of the reverser between the pin 25 and the pin 5, and data are sent to the pin 5 from the pin 25;
a data transmitting end T3 is arranged on the side, close to the pin 6, of the reverser between the pin 24 and the pin 6, and data are transmitted to the pin 24 from the pin 6;
a data receiving end R4 is arranged on the side of the reverser between the pin 22 and the pin 7, which is close to the pin 22, and data is sent to the pin 7 from the pin 22;
the inverter between pin 21 and pin 8 has a data receiving terminal R5 on the side close to pin 21, and data is transmitted from pin 21 to pin 8.
Fig. 4b is a schematic structural diagram of a level shifter according to an embodiment of the present application, and optionally, the level shifter 40 in fig. 4a and the level shifter 40 in fig. 4b are the same device, in combination with fig. 3a, that is, the level shifter 40 further includes:
a third conversion pin 420, connected to the fifth connection pin 310, and configured to forward the data sent by the connection circuit 30 to the level shifter 40 when the operation mode of the serial port is a balanced transmission mode; a fourth conversion pin 422, connected to the sixth connection pin 314, and configured to forward the data sent by the level shifter 40 to the connection circuit 30 when the working mode of the serial port is a balanced transmission mode;
in fig. 4b, in the level shifter 40, inverters are connected between pins 2 and 31 and between pins 3 and 31, a data receiving end R2 is disposed on a side close to pin 2 of the inverter between pins 2 and 31, and a data transmitting end T1 is disposed on a side close to pin 3 of the inverter between pins 3 and 31; the pin 11 may be connected to the data receiving terminal R2 through an inverter, the pin 11 may be connected to the data transmitting terminal T1, the pin 27 may be connected to the first transmitting terminal 11, and the pin 27 may also be connected to a data receiving segment R2.
The capacitance of the first capacitor 410 is 0.1 μ F, the capacitance of the second capacitor 412 is 0.1 μ F, and the capacitance of the third capacitor 414 is 0.1 μ F.
When the COM serial port is in the RS-485 operating Mode, the present application selects the operating Mode setting Mode [2:0] ═ 110 as shown in fig. 4b, i.e. Mode2 ═ 1, Mode1 ═ 1, and Mode0 ═ 0 in fig. 4b, sets pin 16, pin 15, and pin 14 of SP338 to high, and low, connects the fifth connection pin 310 in fig. 3a to the third switch pin 420 in fig. 4b, connects the sixth connection pin 312 to the fourth switch pin 422 in fig. 4b, and switches D-and D + of RS-485 from pin 31 and pin 27. RS-485 is in half-duplex operating mode, and the sending and receiving direction control interface selects to access the RTS signal of the UART, and the direction control interface is pin 11 of the level shifter 40 in fig. 4 b.
To alleviate the IO port number stress of F75111RG, the logic of mode [1] is opposite to mode [0], and the application chooses to invert the level of the second input 402 to form the level of the second output 404.
The mode of the COM serial port controls the IO extension logic, the first I2C address configuration pin of F75111RG is set to high, the I2C address is configured to 0x6E, the COM serial port occupies 3 IOs, the second pin is connected to the seventh connection pin 314 in fig. 3a, the third pin is connected to the second input terminal 402 of the second inverter circuit in fig. 4c, and the fourth pin is connected to the first conversion pin 42 in fig. 4 a. When the MODE2/MODE0 is 01, the COM serial port MODE is set to be the RS-232 MODE; when the MODE2/MODE0 is 10, the COM serial port MODE is set to the RS-485 MODE. In the RS-485 mode, whether to hook a 120 Ω terminal resistor or not can be selected, when the level of the first conversion pin 42 is low, the 120 Ω terminal resistor is not hooked, and when the level of the first conversion pin 42 is high, the 120 Ω terminal resistor is hooked. Wherein, the first pin, the second pin, the third pin and the fourth pin can be selected by a user.
The method has the advantages that the multi-serial port with the RS-232 and RS-485 switching function is expanded through the PICE, and the serial port working mode is flexibly configured through I2C; the dual-network port is expanded through the PICe, the multi-serial ports of the RS-232 and RS-485 working modes can be flexibly configured through the I2C, the requirement of more and more communication interfaces can be met, the application requirement on an industrial field can be met on the number of the serial ports, the software switching between the RS-232 and RS-485 can also be met on the serial port working mode, and the multi-serial port communication device is suitable for various use scenes of the industrial field. The application provides a solution based on PCIE expansion network interface and serial port new application, and the solution can be widely applied to an intelligent substation.
The application relates to an industrial communication platform applied to an intelligent substation, the size of the industrial communication platform is 78.0mmx146.0mmx 127.0mm, the industrial communication platform is installed on a guide rail, an all-aluminum casing is designed without a fan, and main resources of a mainboard comprise
AtomTMProcessor E3845(2M Cache,1.91GHz), 1x SO-DIMM socket to support up to 4GBDDR3L SDRAM. What this application is the expander circuit who connects above mainboard, the expander board need provide 9.4V power for the mainboard promptly, expands two ways PCIE resources of mainboard into 2 ways giga net gapes and the serial ports of the changeable mode of 4 ways.
It should be noted that, GPIO extension configuring the serial port operating mode may select other modes, such as a single chip microcomputer, USB to GPIO. The serial port level conversion can also be replaced by other serial port chips, such as SP232A, SP485, MAX485E, and the like. The voltage can be converted into 9.4V direct current power supply through other power management chips.
In the embodiment of the present application, the method includes: the first conversion equipment is connected with a first interface of the mainboard and used for converting the first interface into at least two serial ports, wherein each serial port in the at least two serial ports has two working modes, and the two working modes comprise: the first interface is used for allocating an exclusive channel bandwidth to the expansion circuit; the at least two level converters are connected with the at least two serial ports one by one and are used for converting first levels of the at least two serial ports into second levels, wherein the second levels are working levels of the two working modes; the mode control circuit is respectively connected with the second interface of the mainboard and the at least two level converters and used for controlling the working mode of each serial port, the second interface is used for the expansion circuit for transmitting data signals and clock signals between the expansion circuit and the mainboard, so that the multi-serial port with the unbalanced transmission mode and the balanced transmission mode can be flexibly configured, the technical effect of adaptability of various use scenes of the multi-serial port in an industrial field is improved, and the technical problem that in the prior art, in the application of the multi-serial port, the working mode of the serial port is single and the application scenes of the multi-serial port cannot be adapted to the various industrial fields is solved.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit may be a division of a logic function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or may not be executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (10)
1. An expansion circuit, comprising:
the first conversion equipment is connected with a first interface of the mainboard and used for converting the first interface into at least two serial ports, wherein each serial port in the at least two serial ports has two working modes, and the two working modes comprise: the first interface is used for allocating an exclusive channel bandwidth to the expansion circuit;
the at least two level converters are connected with the at least two serial ports one by one and are used for converting first levels of the at least two serial ports into second levels, wherein the second levels are working levels of the two working modes;
and the mode control circuit is respectively connected with the second interface of the mainboard and the at least two level converters and is used for controlling the working mode of each serial port, and the second interface is used for transmitting data signals and clock signals between the expansion circuit and the mainboard.
2. The expansion circuit of claim 1, wherein the mode control circuit comprises at least two control interfaces, and wherein the at least two control interfaces are connected to the at least two level shifters one to one.
3. The expansion circuit of claim 1, comprising:
and the terminal is connected with the at least two level converters and is used for transmitting data corresponding to the two working modes.
4. The expansion circuit of claim 3, comprising: and the connecting circuit is connected with the first conversion equipment, the mode control circuit and the at least two level converters and is used for controlling the at least two level converters to convert the first level into the second level based on a first control instruction sent by the mode control circuit.
5. The expansion circuit of claim 4, wherein the connection circuit comprises:
the first connection pin is connected with the first conversion equipment and used for forwarding the data sent by the connection circuit to the first conversion equipment;
the second connecting pin is connected with the first conversion equipment and used for forwarding the data sent by the first conversion equipment to the connecting circuit;
the third connecting pin is connected with the level converter and used for forwarding the data sent by the connecting circuit to the level converter when the working mode of the serial port is an unbalanced transmission mode;
the fourth connecting pin is connected with the level shifter and used for forwarding the data sent by the level shifter to the connecting circuit when the working mode of the serial port is an unbalanced transmission mode;
the fifth connecting pin is connected with the level shifter and used for forwarding the data sent by the connecting circuit to the level shifter when the working mode of the serial port and the level shifter is a balanced transmission mode;
the sixth connecting pin is connected with the level shifter and used for forwarding the data sent by the level shifter to the connecting circuit when the working mode of the serial port is a balanced transmission mode;
a seventh connection pin, connected to the mode control circuit, for forwarding the first control instruction to the connection circuit;
and the eighth connecting pin is connected with the seventh connecting pin through a first inverting circuit and used for forwarding the inverted first control instruction to the connecting circuit.
6. The expansion circuit of claim 5, comprising: the first inverting circuit; and a first input end of the first inverting circuit is connected with the seventh connecting pin, and a first output end of the first inverting circuit is connected with the eighth connecting pin and used for inverting the level of the first input end.
7. The expansion circuit of claim 6, wherein the level shifter comprises:
the first conversion pin is connected with the third connection pin and used for forwarding the data sent by the connection circuit to the level converter when the working mode of the serial port is an unbalanced transmission mode;
the second conversion pin is connected with the fourth connection pin and used for forwarding the data sent by the level converter to the connection circuit when the working mode of the serial port is an unbalanced transmission mode;
the third conversion pin is connected with the fifth connection pin and used for forwarding the data sent by the connection circuit to the level converter when the working mode of the serial port and the third connection pin is a balanced transmission mode;
the fourth conversion pin is connected with the sixth connection pin and used for forwarding the data sent by the level converter to the connection circuit when the working mode of the serial port and the fourth connection pin is a balanced transmission mode;
the first pin is connected with the mode control circuit and used for adjusting the working mode of the serial port based on a second control instruction sent by the mode control circuit;
and the second pin is connected with the first pin through a second inverting circuit and used for forwarding the inverted second control instruction to the level shifter.
8. The expansion circuit of claim 7, comprising: the second inverting circuit; and a second input end of the second inverting circuit is connected with the first pin, and a second output end of the second inverting circuit is connected with the second pin and used for inverting the level of the second input end.
9. The expansion circuit of claim 8, comprising:
and the second conversion equipment is connected with a third interface of the mainboard and used for converting the third interface into two paths of gigabit network ports, and the third interface is used for allocating an exclusive channel bandwidth for the expansion circuit.
10. The expansion circuit of claim 9, wherein the second switching device comprises:
a PCIE expander, configured to expand the third interface into two PCIE interfaces;
the expansion circuit further comprises two network controllers, wherein each network controller is connected with one PCIE interface and one RJ45 interface in the two PCIE interfaces.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921477721.6U CN210573287U (en) | 2019-09-05 | 2019-09-05 | Expansion circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921477721.6U CN210573287U (en) | 2019-09-05 | 2019-09-05 | Expansion circuit |
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| CN210573287U true CN210573287U (en) | 2020-05-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115878539A (en) * | 2023-01-31 | 2023-03-31 | 北京智芯微电子科技有限公司 | Serial port self-adaptive circuit, electronic equipment and circuit board |
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2019
- 2019-09-05 CN CN201921477721.6U patent/CN210573287U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115878539A (en) * | 2023-01-31 | 2023-03-31 | 北京智芯微电子科技有限公司 | Serial port self-adaptive circuit, electronic equipment and circuit board |
| CN115878539B (en) * | 2023-01-31 | 2023-05-16 | 北京智芯微电子科技有限公司 | Serial port self-adapting circuit, electronic equipment and circuit board |
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Denomination of utility model: Expansion circuit Effective date of registration: 20210719 Granted publication date: 20200519 Pledgee: Zhongguancun Beijing technology financing Company limited by guarantee Pledgor: BEIJING HUADIAN ZHONGXIN TECHNOLOGY Co.,Ltd. Registration number: Y2021990000635 |