CN113626359A - Signal switching device and method for flash memory chip of server - Google Patents

Signal switching device and method for flash memory chip of server Download PDF

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Publication number
CN113626359A
CN113626359A CN202110865540.6A CN202110865540A CN113626359A CN 113626359 A CN113626359 A CN 113626359A CN 202110865540 A CN202110865540 A CN 202110865540A CN 113626359 A CN113626359 A CN 113626359A
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chip
flash memory
memory chip
spi
signals
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王晓
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention discloses a signal switching device and a method of a flash memory chip of a server, wherein the signal switching device comprises: a baseboard management controller comprising an SPI controller and a plurality of GPIO signals; the multi-channel selection switch chip is connected with the substrate management controller and is configured to select the on or off of the channels based on the GPIO signals; the power supply control module is connected with the substrate management controller; the flash memory chip and the south bridge chip are mutually connected and are both connected with the power control module and the multi-way selection switch chip. By the scheme of the invention, the read-write mode of the flash memory chip can be automatically switched after the server is powered on, the problem that the flash memory chip is switched to the QUAD mode and needs to be additionally burnt by other equipment is solved, the operation is simple, the production cost is reduced, and the production efficiency is improved.

Description

Signal switching device and method for flash memory chip of server
Technical Field
The present invention relates to the field of server technologies, and in particular, to a signal switching device and method for a flash memory chip of a server.
Background
In the server, BIOS (Basic Input Output System ) firmware is generally stored in an SPI (Serial Peripheral Interface) FLASH (FLASH memory) chip. SPI is a high-speed, full-duplex, synchronous communication bus. The read-write modes of the SPI FLASH chip (a FLASH memory chip integrated with an SPI bus) include the following three types:
one, SINGLE mode. The Input/Output signals of the SINGLE mode include CLK (Clock, generated by a Master), MOSI (Master Output Slave Input, Master data Output, Slave data Input), MISO (Master Input Slave Output, Master data Input, Slave data Output), CS (Chip Select, Slave enable signal, controlled by a Master), when the Master reads the Slave data, only one MISO signal line transmits data, and the schematic diagram of the operating principle of the SINGLE mode is shown in fig. 1.
Two, DUAL mode. The number of input and output signals of the DUAL mode is the same as that of the SINGLE mode, when the master device is in the SINGLE mode, a command byte may be sent through the MOSI signal to make the SPI slave device enter the DUAL mode, so that the MOSI becomes SIO0(serial io 0), and the MOIS becomes SIO1(serial io 1), so that the slave device can transmit 2 bits of data to the master device simultaneously in one clock cycle, which doubles data transmission, and the working principle diagram of the DUAL mode is shown in fig. 2.
And thirdly, a QUAD mode. Compared with the DUAL mode, two input and output signals (SIO2, SIO3) are added in order to transmit 4 bits of data in one clock. The working principle of the QUAD mode is schematically shown in fig. 3.
In the three read-write modes of the SPI FLASH chip, as the number of input and output signals in the DUAD mode increases, the SPI FLASH chip currently used in the server needs to be additionally programmed by other devices before the default SINGLE mode is switched to the QUAD mode, and the driving capability of the SIO0/SIO1/SIO2/SIO3 signals of the slave devices is set.
In the current server system, the SPI FLASH chip is directly connected to the PCH chip (a south bridge chip of intel corporation), and the structural schematic diagrams of the SPI FLASH chip and the PCH chip are shown in fig. 4. In the connection structure of the SPI FLASH chip and the PCH chip shown in fig. 4, the PCH can only be fixedly set to use an SPI mode, and cannot separately send a command to the BIOS SPI FLASH chip, and if the QUAD mode is used, the SPI FLASH chip needs to be additionally burned by other devices when leaving the factory, which increases the production cost.
Disclosure of Invention
In view of the above, the present invention provides a signal switching device and method for a flash memory chip of a server, which can automatically switch a read-write mode of the flash memory chip after the server is powered on, and solve the problem that the flash memory chip needs to be switched to a QUAD mode and needs to be additionally programmed by other devices, and have the advantages of simple operation, reduced production cost and improved production efficiency.
In view of the above, an aspect of the embodiments of the present invention provides a signal switching apparatus for a flash memory chip of a server, including:
a baseboard management controller comprising an SPI controller and a plurality of GPIO signals;
the multi-channel selection switch chip is connected with the substrate management controller and is configured to select the on or off of the channels based on the GPIO signals;
the power supply control module is connected with the substrate management controller;
a flash memory chip and a south bridge chip, the flash memory chip and the south bridge chip are connected with each other and are connected with the power control module and the multi-way selection switch chip,
the multi-way selection switch chip is configured to enable the south bridge chip to be conducted with the flash memory chip and the SPI controller to be disconnected with the flash memory chip based on GPIO signals of a baseboard management controller, or enable the south bridge chip to be disconnected with the flash memory chip and the SPI controller to be conducted with the flash memory chip, and the power supply control module is configured to control the south bridge chip to be powered on or powered off based on the GPIO signals of the baseboard management controller.
In some embodiments, the first GPIO signal of the baseboard management controller is connected to the power control module, the first power output of the power control module is connected to the south bridge chip, the second power output of the power control module is connected to the flash memory chip, the second GPIO signal of the baseboard management controller and the plurality of SPI signals of the SPI controller are connected to the input/output ports of the corresponding multiplexer chips, the plurality of SPI signals of the south bridge chip are connected to the input/output ports of the corresponding multiplexer chips, the plurality of SPI signals of the flash memory chip are connected to the input/output ports of the corresponding multiplexer chips, and the plurality of SPI signals of the flash memory chip are connected to the south bridge chip.
In some embodiments, the GPIO signals include high level GPIO signals and low level GPIO signals.
In some embodiments, the first low level GPIO signal or the first high level GPIO signal of the baseboard management controller is connected to a power control module configured to power down a first power output of the power control module based on the first low level GPIO signal to power down a south bridge chip connected to the first power output, and to power up the first power output of the power control module based on the first high level GPIO signal to power up the south bridge chip connected to the first power output.
In some embodiments, the second low-level GPIO signal and the second high-level GPIO signal of the baseboard management controller are both connected to the input/output port of a corresponding multiplexing switch chip configured to turn on the plurality of SPI signals of the SPI controller with the plurality of SPI signals of the corresponding flash memory chip, respectively, based on the second low-level GPIO signal, and to turn on the plurality of SPI signals of the south bridge chip with the plurality of SPI signals of the corresponding flash memory chip, respectively, based on the second high-level GPIO signal.
In some embodiments, the SPI signals of the SPI controller and the SPI signals of the south bridge chip are CLK, MOSI, MISO, CS signals, and the SPI signals of the flash memory chip are CLK, MOSI, MISO, CS, and two SIO signals.
In some embodiments, the first GPIO signal of the bmc is connected to the power control module, the first power output of the power control module is connected to the south bridge chip, the second output of the power control module is connected to the flash memory chip, the CLK, MOSI, MISO, CS signal and the second GPIO signal of the SPI controller are respectively connected to the input/output port of the corresponding multiplexer chip, the CLK, MOSI, MISO, CS signal of the south bridge chip are respectively connected to the input/output port of the corresponding multiplexer chip, the CLK, MOSI, MISO, CS signal of the flash memory chip are respectively connected to the input/output port of the corresponding multiplexer chip, and the two SIO signals of the flash memory chip are connected to the south bridge chip.
In some embodiments, the SPI controller is configured to send an enhancement command to the flash memory chip to write enhancement data to the flash memory chip.
In another aspect of the embodiments of the present invention, there is also provided a signal switching method for a flash memory chip of a server, based on the apparatus described above, the method includes:
sending a first GPIO signal to a power control module through an SPI controller to enable the power control module to power off a south bridge chip;
sending a second GPIO signal to a multi-way selection switch chip through the SPI controller, so that the multi-way selection switch chip conducts a plurality of SPI signals of the SPI controller with a plurality of SPI signals of a corresponding flash memory chip respectively;
sending an enhancement command to the flash memory chip from the SPI controller so as to write enhancement data corresponding to the enhancement command into the flash memory chip;
responding to the completion of writing the enhanced data into the flash memory chip, and enabling the multi-path selection switch chip to connect the plurality of SPI signals of the south bridge chip with the plurality of SPI signals of the corresponding flash memory chip through a second GPIO signal of the SPI controller;
and a second GPIO signal sent to the power control module by the SPI controller enables the power control module to electrify the south bridge chip so as to conduct the south bridge chip and the flash memory chip.
In some embodiments, sending an enhanced command from the SPI controller to the flash memory chip to write enhanced data corresponding to the enhanced command to the flash memory chip includes:
sending a status register reading command from the SPI controller to the flash memory chip so as to read data of a status register of the flash memory chip;
sending a write enabling command to the flash memory chip to enable the flash memory chip to execute a write function;
and modifying the data in the status register of the flash memory chip, and writing the modified data into the status register of the flash memory chip.
The invention has the following beneficial technical effects: on the basis of the prior art, the multiway switch selection chip is connected between the south bridge chip and the flash memory chip, so that the read-write mode of the flash memory chip can be automatically switched after the server is powered on, the problems that the flash memory chip is switched to the QUAD mode and burning is additionally required by other equipment are solved, the operation is simple, the production cost is reduced, and the production efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of the working principle of SINGLE mode of SPI bus of a flash memory chip;
FIG. 2 is a schematic diagram illustrating the working principle of the DUAL mode of the SPI bus of a flash memory chip;
FIG. 3 is a schematic diagram of the QUAD mode of the SPI bus of a flash memory chip;
FIG. 4 is a schematic structural diagram of an SPI FLASH chip and a PCH chip in the prior art;
FIG. 5 is a schematic structural diagram of a signal switching apparatus of a flash memory chip of a server according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a signal switching apparatus of a flash memory chip of a server according to another embodiment of the present invention;
fig. 7 is a block diagram of an embodiment of a signal switching method of a flash memory chip of a server according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention provides a signal switching apparatus of a flash memory chip of a server, as shown in fig. 5, the signal switching apparatus includes:
a baseboard management controller 10 comprising an SPI controller 100 and a plurality of GPIO signals;
the multi-channel selection switch chip 20 is connected with the substrate management controller 10, and is configured to select the on or off of the channels based on the GPIO signals;
the power supply control module 30, the power supply control module 30 is connected with the substrate management controller 10;
a flash memory chip 40 and a south bridge chip 50, the flash memory chip 40 and the south bridge chip 50 are connected to each other and are connected to the power control module 30 and the multiplexer chip 20,
wherein the multiplexer chip 20 is configured to make the south bridge chip 50 and the flash memory chip 40 conduct and the SPI controller 100 and the flash memory chip disconnect based on GPIO signals of the bmc, or make the south bridge chip 50 and the flash memory chip 400 disconnect and the SPI controller 100 and the flash memory chip 40 conduct, and the power control module 30 is configured to control the south bridge chip 50 to be powered on or powered off based on GPIO signals of the bmc 10.
Through the signal switching device, the read-write mode of the flash memory chip can be automatically switched after the server is powered on, the problem that the flash memory chip is switched to the QUAD mode and needs to be additionally burned by other equipment is solved, the operation is simple, the production cost is reduced, and the production efficiency is improved.
In some embodiments, the first GPIO signal of the baseboard management controller is connected to the power control module, the first power output of the power control module is connected to the south bridge chip, the second power output of the power control module is connected to the flash memory chip, the second GPIO signal of the baseboard management controller and the plurality of SPI signals of the SPI controller are connected to the input/output ports of the corresponding multiplexer chips, the plurality of SPI signals of the south bridge chip are connected to the input/output ports of the corresponding multiplexer chips, the plurality of SPI signals of the flash memory chip are connected to the input/output ports of the corresponding multiplexer chips, and the plurality of SPI signals of the flash memory chip are connected to the south bridge chip.
In some embodiments, the GPIO signals include high level GPIO signals and low level GPIO signals.
In some embodiments, the first low level GPIO signal or the first high level GPIO signal of the baseboard management controller is connected to a power control module configured to power down a first power output of the power control module based on the first low level GPIO signal to power down a south bridge chip connected to the first power output, and to power up the first power output of the power control module based on the first high level GPIO signal to power up the south bridge chip connected to the first power output;
in some embodiments, the second low-level GPIO signal and the second high-level GPIO signal of the baseboard management controller are both connected to the input/output port of a corresponding multiplexing switch chip configured to turn on the plurality of SPI signals of the SPI controller with the plurality of SPI signals of the corresponding flash memory chip, respectively, based on the second low-level GPIO signal, and to turn on the plurality of SPI signals of the south bridge chip with the plurality of SPI signals of the corresponding flash memory chip, respectively, based on the second high-level GPIO signal.
In some embodiments, the SPI signals of the SPI controller and the SPI signals of the south bridge chip are CLK, MOSI, MISO, CS signals, and the SPI signals of the flash memory chip are CLK, MOSI, MISO, CS, and two SIO signals.
In some embodiments, the first GPIO signal of the bmc is connected to the power control module, the first power output of the power control module is connected to the south bridge chip, the second output of the power control module is connected to the flash memory chip, the CLK, MOSI, MISO, CS signal and the second GPIO signal of the SPI controller are respectively connected to the input/output port of the corresponding multiplexer chip, the CLK, MOSI, MISO, CS signal of the south bridge chip are respectively connected to the input/output port of the corresponding multiplexer chip, the CLK, MOSI, MISO, CS signal of the flash memory chip are respectively connected to the input/output port of the corresponding multiplexer chip, and the two SIO signals of the flash memory chip are connected to the south bridge chip.
In some embodiments, the SPI controller is configured to send an enhancement command to the flash memory chip to write enhancement data to the flash memory chip.
The following describes examples of the present invention with reference to specific embodiments.
Fig. 6 shows a signal switching apparatus of a flash memory chip of a server according to an embodiment of the present invention. In fig. 6, SWITCH is a multi-way selection SWITCH chip, BIOS SPI FLASH is a FLASH memory chip, PCH is a south bridge chip, and BMC is a baseboard management controller.
The signal switching apparatus of the flash memory chip of the server shown in fig. 6 includes:
the BMC 10 comprises an SPI controller 100, an output control signal GPIO1 and a GPIO2, wherein the SPI controller 100 inputs and outputs an SPI signal;
the SWITCH chip 20, the SWITCH chip 20 is connected to the BMC 10, and configured to select on or off of the plurality of channels based on the control signal. Specifically, the SWITCH chip 20 includes a plurality of input/output ports, each represented by A, B, C, D, E, F, G, H, I, J, K, L, M, E, F, G, H of the SWITCH chip 20 is connected to CLK, MOSI, MISO, CS signals input/output by the SPI controller;
the power control modules 30 and 30 are connected with the GPIO1 of the BMC, and each power control module comprises a power output 1 and a power output 2;
the SPI FLASH chip comprises an SPI FLASH chip 40 and a PCH chip 50, wherein the SPI FLASH chip 40 inputs and outputs signals CLK, MOSI, MISO, CS, SIO2 and SIO3, the PCH chip 50 inputs and outputs signals CLK, MOSI, MISO and CS, signals SIO2, SIO3 and the PCH chip 50 of the SPI FLASH chip 40 are connected, signals CS, MISO, MOSI and CLK of the SPI FLASH chip 40 are respectively connected with I, J, K, L of the SWITCH chip 20, and signals CS, MISO, MOSI and CLK of the PCH chip are respectively connected with A, B, C, D of the SPI FLASH chip 20;
the device can be arranged in a storage system of a server, when the server is powered on, the BMC 10 sends a low-level GPIO1 to the power control module 30, and after receiving the low-level GPIO1, the power control module 30 powers off the power output 1, so that the PCH chip 50 connected with the power output 1 is powered off; sending a low-level GPIO2 to an input/output port K of the SWITCH chip 20 through the BMC 10, and connecting and conducting input/output signals CLK, MOSI, MISO and CS of the SPI controller 100 and input/output signals CLK, MOSI, MISO and CS of the SPI FLASH chip 40 through the input/output port K; after the SPI controller 100 is conducted with the SPI FLASH chip 40, the SPI controller 100 sends an enhanced command to the SPI FLASH chip 40 to write enhanced data into the SPI FLASH chip 40, so that signals SIO2, SIO3 of the SPI FLASH chip 40 can be used to transmit data, thereby implementing a QUAD mode; sending a high-level GPIO2 to an input/output port K of the SWITCH chip 20 through the BMC 10, and connecting input/output signals CLK, MOSI, MISO and CS of the PCH50 with input/output signals CLK, MOSI, MISO and CS of the SPI FLASH chip 40 through the input/output port K, wherein at the moment, because the PCH chip 50 is not powered on, signals between the SPI FLASH chip 40 and the PCH chip 50 are not conducted; the BMC 10 sends a high level GPIO1 to the power control module 30, and after the power control module 30 receives the high level GPIO1, the power output 1 is powered on, so that the PCH chip 50 connected with the power output 1 is powered on, and the contents of the SPI FLASH chip 40 are automatically read and written after the PCH chip 50 is powered on.
It should be noted that the interconnection among the above devices is based on a bus, and various signals are transmitted on the bus to realize the communication connection between the two devices.
Through the signal switching device, the read-write mode of the flash memory chip can be automatically switched after the server is powered on, the problem that the flash memory chip is switched to the QUAD mode and needs to be additionally burned by other equipment is solved, the operation is simple, the production cost is reduced, and the production efficiency is improved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 7, an embodiment of the present invention further provides a signal switching method for a flash memory chip of a server, which is based on the apparatus as described above, and performs the following steps:
step S101, a first GPIO signal is sent to a power control module through an SPI controller, and the power control module is powered off to a south bridge chip;
step S103, sending a second GPIO signal to a multi-way selection switch chip through the SPI controller, and enabling the multi-way selection switch chip to conduct a plurality of SPI signals of the SPI controller with a plurality of SPI signals of a corresponding flash memory chip respectively;
step S105, sending an enhancement command from the SPI controller to the flash memory chip so as to write enhancement data corresponding to the enhancement command into the flash memory chip;
step S107, in response to the completion of the writing of the enhanced data into the flash memory chip, enabling the multi-channel selection switch chip to connect the plurality of SPI signals of the south bridge chip with the plurality of SPI signals of the corresponding flash memory chip respectively through a second GPIO signal of the SPI controller;
step S109, the power control module powers on the south bridge chip to conduct the south bridge chip and the flash memory chip through a second GPIO signal sent to the power control module by the SPI controller.
By the method, the read-write mode of the flash memory chip can be automatically switched after the server is powered on, the problem that the flash memory chip is switched to the QUAD mode and needs to be additionally burned by other equipment is solved, the operation is simple, the production cost is reduced, and the production efficiency is improved.
In some embodiments, sending an enhanced command from the SPI controller to the flash memory chip to write enhanced data corresponding to the enhanced command to the flash memory chip includes:
sending a status register reading command from the SPI controller to the flash memory chip so as to read data of a status register of the flash memory chip;
sending a write enabling command to the flash memory chip to enable the flash memory chip to execute a write function;
and modifying the data in the status register of the flash memory chip, and writing the modified data into the status register of the flash memory chip.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer device, which includes a processor and a memory, wherein the memory stores a computer program capable of running on the processor, and the processor executes the program to perform the steps of the above method.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention also provides a computer-readable storage medium storing a computer program for performing the above method when executed by a processor.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. A signal switching apparatus of a flash memory chip of a server, comprising:
a baseboard management controller comprising an SPI controller and a plurality of GPIO signals;
the multi-channel selection switch chip is connected with the substrate management controller and is configured to select the on or off of the channels based on the GPIO signals;
the power supply control module is connected with the substrate management controller;
a flash memory chip and a south bridge chip, the flash memory chip and the south bridge chip are connected with each other and are connected with the power control module and the multi-way selection switch chip,
the multi-way selection switch chip is configured to enable the south bridge chip to be conducted with the flash memory chip and the SPI controller to be disconnected with the flash memory chip based on GPIO signals of a baseboard management controller, or enable the south bridge chip to be disconnected with the flash memory chip and the SPI controller to be conducted with the flash memory chip, and the power supply control module is configured to control the south bridge chip to be powered on or powered off based on the GPIO signals of the baseboard management controller.
2. The device of claim 1, wherein the first GPIO signal of the baseboard management controller is connected to the power control module, the first power output of the power control module is connected to the south bridge chip, the second power output of the power control module is connected to the flash memory chip, the second GPIO signal of the baseboard management controller and the plurality of SPI signals of the SPI controller are respectively connected to the input/output ports of the corresponding multiplexer chip, the plurality of SPI signals of the south bridge chip are respectively connected to the input/output ports of the corresponding multiplexer chip, the plurality of SPI signals of the flash memory chip are respectively connected to the input/output ports of the corresponding multiplexer chip, and the plurality of SPI signals of the flash memory chip are connected to the south bridge chip.
3. The apparatus of claim 2, wherein the GPIO signals comprise high level GPIO signals and low level GPIO signals.
4. The device of claim 2, wherein the first low level GPIO signal or the first high level GPIO signal of the baseboard management controller is connected to a power control module, the power control module configured to power down the first power output of the power control module to power down a south bridge chip connected to the first power output based on the first low level GPIO signal, and to power up the first power output of the power control module to power up the south bridge chip connected to the first power output based on the first high level GPIO signal.
5. The device of claim 2, wherein the second low level GPIO signal and the second high level GPIO signal of the baseboard management controller are both connected to an input/output port of a corresponding multiplexing switch chip, the corresponding multiplexing switch chip is configured to turn on the plurality of SPI signals of the SPI controller with the plurality of SPI signals of the corresponding flash memory chip, respectively, based on the second low level GPIO signal, and to turn on the plurality of SPI signals of the south bridge chip with the plurality of SPI signals of the corresponding flash memory chip, respectively, based on the second high level GPIO signal.
6. The apparatus of claim 2, wherein the plurality of SPI signals of the SPI controller and the plurality of SPI signals of the south bridge chip are CLK, MOSI, MISO, CS signals, and the plurality of SPI signals of the flash memory chip are CLK, MOSI, MISO, CS signals, and two SIO signals.
7. The device of claim 6, wherein the first GPIO signal of the baseboard management controller is connected to the power control module, the first power output of the power control module is connected to the south bridge chip, the second output of the power control module is connected to the flash memory chip, the CLK, MOSI, MISO, CS signals of the SPI controller and the second GPIO signal are respectively connected to the input/output ports of the corresponding multi-way selection switch chip, the CLK, MOSI, MISO, CS signals of the south bridge chip are respectively connected to the input/output ports of the corresponding multi-way selection switch chip, the CLK, MOSI, MISO, CS signals of the flash memory chip are respectively connected to the input/output ports of the corresponding multi-way selection switch chip, and the two SIO signals of the flash memory chip are connected to the south bridge chip.
8. The apparatus of claim 1, wherein the SPI controller is configured to send an enhancement command to the flash memory chip to write enhancement data to the flash memory chip.
9. A signal switching method for a flash memory chip of a server, characterized in that based on the apparatus of claims 1-8, the following steps are performed:
sending a first GPIO signal to a power control module through an SPI controller to enable the power control module to power off a south bridge chip;
sending a second GPIO signal to a multi-way selection switch chip through the SPI controller, so that the multi-way selection switch chip conducts a plurality of SPI signals of the SPI controller with a plurality of SPI signals of a corresponding flash memory chip respectively;
sending an enhancement command to the flash memory chip from the SPI controller so as to write enhancement data corresponding to the enhancement command into the flash memory chip;
responding to the completion of writing the enhanced data into the flash memory chip, and enabling the multi-path selection switch chip to connect the plurality of SPI signals of the south bridge chip with the plurality of SPI signals of the corresponding flash memory chip through a second GPIO signal of the SPI controller;
and a second GPIO signal sent to the power control module by the SPI controller enables the power control module to electrify the south bridge chip so as to conduct the south bridge chip and the flash memory chip.
10. The method of claim 9, wherein sending an enhanced command from the SPI controller to the flash memory chip to write enhanced data corresponding to the enhanced command to the flash memory chip comprises:
sending a status register reading command from the SPI controller to the flash memory chip so as to read data of a status register of the flash memory chip;
sending a write enabling command to the flash memory chip to enable the flash memory chip to execute a write function;
and modifying the data in the status register of the flash memory chip, and writing the modified data into the status register of the flash memory chip.
CN202110865540.6A 2021-07-29 2021-07-29 Signal switching device and method for flash memory chip of server Withdrawn CN113626359A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114996177A (en) * 2022-05-19 2022-09-02 苏州浪潮智能科技有限公司 System, method and server for accessing Flash chip of management board
CN117591460A (en) * 2024-01-17 2024-02-23 紫光恒越技术有限公司 Equipment control method and device, electronic equipment and storage medium

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114996177A (en) * 2022-05-19 2022-09-02 苏州浪潮智能科技有限公司 System, method and server for accessing Flash chip of management board
CN114996177B (en) * 2022-05-19 2023-08-04 苏州浪潮智能科技有限公司 System, method and server for accessing Flash chip of management board
CN117591460A (en) * 2024-01-17 2024-02-23 紫光恒越技术有限公司 Equipment control method and device, electronic equipment and storage medium
CN117591460B (en) * 2024-01-17 2024-04-26 紫光恒越技术有限公司 Equipment control method and device, electronic equipment and storage medium

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