CN105490844A

CN105490844A - PCIe port reconstruction method

Info

Publication number: CN105490844A
Application number: CN201510887578.8A
Authority: CN
Inventors: 张洛
Original assignee: Luoyang Institute of Electro Optical Equipment AVIC
Current assignee: Luoyang Institute of Electro Optical Equipment AVIC
Priority date: 2015-12-05
Filing date: 2015-12-05
Publication date: 2016-04-13

Abstract

The invention relates to a PCIe port reconstruction method. The PCIe port reconstruction method comprises the following steps: step 1) obtaining to-be-expanded PCIe port information by a (root complex) RC, and transmitting the information to an FPGA module; step 2) performing configuration on a Switch by the FPGA module based on default configuration, comparing the to-be-expanded PCIe port information obtained from the RC with the current configuration, and checking the comparison result; and step 3) if the configuration information is consistent according to the comparison result, completing the configuration on the FPGA; and if the configuration information is not consistent, performing configuration according to the information sent to the FPGA module from the CPU in the step 1), and sending an initializing signal to the Switch and the CPU. The PCIe port reconstruction method can enable a main control board to be higher in universality, so that the main control board can be applied to more systems.

Description

A kind of PCIe port reconstructing method

Technical field

The present invention relates to airborne embedded computer technology field, particularly relate to a kind of reconfigurable method of airborne computer veneer PCIe port.

Background technology

In airborne embedded computer system framework, PCIe bus is more and more applied.The processor system framework of general Based PC Ie bus mainly contains root controller RC (RootComplex), destination node EP (Endpoint) and interchanger Switch forms.PCIe bus adopts connected mode end to end, and each PCIe disconnection intelligent link EP, PCIe disconnection can connect switch and enter downlink spreader.The PCIe link expanded by switch can continue to mount EP or other switch.

The PCIe port of current master control borad generally enters downlink spreader by a PCIeswitch, but the extended mode normally fixed by upper pull down resistor, the external PCIe port of master control borad is made to be that fixed qty and data width are (as 4*1PCIe, namely externally there are 4 road PCIe ports, every circuit-switched data width is * 1), when this master control borad is applied in another one system (as needs 2*2PCIe, i.e. external 2 road PCIe ports, every circuit-switched data width is * 2) time, just can not be suitable for the requirement of this system, need to re-start hardware designs.Current this master control borad needs when applying to need to change master control borad according to different systems, is unfavorable for the quick propelling of system item progress.

Summary of the invention

The object of this invention is to provide the method for a kind of PCIe port reconstruct, fix and the not strong problem of adaptability in order to solve existing master control borad due to port number and data width.

For achieving the above object, the solution of the present invention comprises:

A kind of PCIe port reconstructing method, comprises the steps:

Step 1): root controller RC obtains and treats expansion PCIe port information, and by these information transmission to FPGA module;

Step 2): FPGA module is configured interchanger Switch according to default configuration, then treats that expansion PCIe port information is with compared with current configuration by what receive from root controller RC, and checks comparative result;

Step 3): in comparative result, if configuration information is consistent, then complete the configuration to FPGA; If configuration information is inconsistent, then according to step 1) in CPU send to the information of FPGA module to be configured, and to Switch and CPU send initializing signal.

Preferably, described FPGA and CPU communication is communicated by LocalBus bus.

Further, described controller RC is directly connected with interchanger Switch.

The present invention uses the configuration of the framework of CPU+FPGA to PCIeswitch to control, thus can when not changing airborne embedded computer hardware, change quantity and the data width of PCIe port to a certain extent, thus make the master control borad versatility of design so stronger, can be applied in more system.The master control borad designed based on the method has stronger versatility, is more conducive to the standardization of system item development progress progress and management.

Accompanying drawing explanation

Fig. 1 is master control borad inner PCIe port interlock circuit composition frame chart;

Fig. 2 is workflow diagram of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention will be further described in detail.

The technical scheme that the present invention provides for technical solution problem is: the control framework building CPU+FPGA, the port mode of the PCIe of the system that will connect according to PCIe bus and master controller needs, CPU+FPGA framework sends the configuration of corresponding control command to PCIe bus switch switch and controls, and the information of PCIe port mode is write to the register in FPGA by LocalBus, after FPGA obtains port configuration information, corresponding low and high level is exported to the interchanger Switch corresponding port configuration pin of PCIe, then reset signal is sent to interchanger switch and CPU of FPGA to PCIe, re-start initialization.After to be initiated, still PCIe port configuration information needed for master control borad can be write to the register in FPGA by LocalBus, this value and inside settings compare by FPGA, if it is consistent that comparative result is the two, then represent that the PCIe port that now master control borad is external has been configured as consistent with corresponding system required port, now FPGA no longer needs to send reset signal to PCIeswitch and CPU.

As shown in Figure 1, it is the block diagram of master control borad of the present invention inner PCIe port interlock circuit composition, as can be seen from the figure, master control borad inner PCIe port interlock circuit comprises the CPU module, FPGA module and the Switch module with PCIe port that are integrated with root controller RC.As can be seen from the figure, the upstream port that CPU carries out information interaction Switch by the built-in register Register in LocalBus and FPGA is connected with CPU, downstream port is then as the external PCIe port of master control borad, the simultaneously port arrangement pin of FPGA also control Switch, FPGA sends reset signal to CPU module and Switch module.

In above-described embodiment, root controller RC is directly connected with interchanger Switch, and as other execution modes, the interchanger Switch module of multilayer can also be had to carry out expansion interconnected, the interchanger Switch more than second level is indirectly connected with root controller RC.

In order to can more detailed explanation technical scheme of the present invention, now to be illustrated with an example.As shown in Figure 2, the default configuration of the inner PCIe port of master control borad is the PCIe port mode of 1*4, and the PCIe port arrangement needed for the total master control borad of this system is the PCIe port mode of 2*2.

After master control borad electrification reset, CPU module starts to check system, check the port configuration information needed for it, inspection through CPU module knows that the configuration information of PCIe port needed for master control borad in this system is 2*2PCIe port, then these information are sent to FPGA by LocalBus by CPU, be written in the register of FPGA, the root node RC of the processor system framework of the PCIe of initialization simultaneously bus.

And FPGA module is after the loading that powers on completes, then according to default configuration (i.e. the PCIe port information of 1*4), port arrangement is carried out to Switch.Whether, after having configured, FPGA module checks current configuration, consistent with the port configuration information (i.e. the PCIe port information of 2*2) needed for this system to check the PCIe port information configured.If it is consistent that check result is the two, namely default configuration is also 2*2PCIe port, and now PCIe port arrangement completes, then do not carry out subsequent action; If check result is that the two configuration is inconsistent, then the port configuration information that now FPGA sends according to CPU is configured Switch port, is here PCIe port mode Switch being configured to 2*2.To after the reconfiguring and also complete of Switch, then FPGA sends out reset signal to Switch and CPU, makes Switch and CPU to restart initialization.After CPU and Switch initialization is complete, then the PCIe port configuration information (i.e. the PCIe port information of 2*2) needed for master control borad is written in the middle of the register in FPGA by CPU again by LocalBus bus, and the configuration information set in this PCIe port configuration information and Switch contrasts by FPGA, check that whether comparing result is consistent.If comparing result find both inconsistent, then illustrate that the external PCIe interface of this thing master control borad has been configured to the PCIe interface module required for correspondence system, can normally work; If comparing result find both inconsistent, then again configuration information needed for correspondence system is written in FPGA module, again it is configured, and reset and check.

Be presented above the execution mode that the present invention is concrete, but the present invention is not limited to described execution mode.Under the thinking that the present invention provides; the mode easily expected to those skilled in the art is adopted to convert the technological means in above-described embodiment, replace, revise; and the effect played goal of the invention that is substantially identical with the relevant art means in the present invention, that realize is also substantially identical; the technical scheme of such formation is carried out fine setting to above-described embodiment and is formed, and this technical scheme still falls within the scope of protection of the present invention.

Claims

1. a PCIe port reconstructing method, is characterized in that, comprises the steps:

2. a kind of PCIe port reconstructing method according to claim 1, is characterized in that, described FPGA and CPU communication is communicated by LocalBus bus.

3. a kind of PCIe port reconstructing method according to claim 1, it is characterized in that, described controller RC is directly connected with interchanger Switch.