CN111400211B - PCIe bus-based communication method and system - Google Patents
PCIe bus-based communication method and system Download PDFInfo
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- CN111400211B CN111400211B CN202010267176.9A CN202010267176A CN111400211B CN 111400211 B CN111400211 B CN 111400211B CN 202010267176 A CN202010267176 A CN 202010267176A CN 111400211 B CN111400211 B CN 111400211B
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a communication method and a system based on a PCIe bus, which are applied to a communication system comprising a master control CPU, a slave device FPGA, a state monitoring high-reliability antifuse FPGA, a controllable master control CPU power supply DC _ DC module and a slave device FPGA starting program storage chip, wherein the method comprises the following steps: starting a state monitoring high-reliability antifuse FPGA and a main control CPU, and establishing PCIe connection between the slave device FPGA and the main control CPU; and monitoring the communication state between the master control CPU and the slave device FPGA through the state monitoring high-reliability antifuse FPGA. Therefore, the state of the whole PCIe bus communication system is monitored through the state monitoring high-reliability antifuse FPGA, the power supply time sequence of the PCIe sub-equipment and the main equipment is controlled, and the system overload is controlled, so that the reliability of the whole communication system is improved, and the system has fault recovery capability.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a PCIe bus-based communication method and system.
Background
With the progress of the satellite-borne loading technology, the loading data volume is greatly increased. In the field of satellite-borne data transmission, a conventional Low-Voltage Differential Signaling (LVDS) data transmission link cannot meet the requirement of high-speed data transmission in terms of both rate and universality. The demand for high-speed and reliable bus data transmission is increasing.
However, if a customized high-speed data transmission bus communication scheme is separately developed, it is difficult to implement both in terms of cost and reliability. Therefore, the corresponding reliability design of the conventional and universal high-speed bus is one of the most feasible schemes to ensure the reliability thereof in a space environment.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a communication method and a communication system based on a PCIe bus.
In a first aspect, the present invention provides a pcie (pcie) bus based communication method, which is applied to a communication system including a master CPU (central processing unit), a slave FPGA (Field-Programmable Gate Array), a state monitoring highly-reliable antifuse FPGA, a controllable DC _ DC module for supplying power to the master CPU, and a slave FPGA boot program storage chip, and the method includes:
step 1: starting the state monitoring high-reliability antifuse FPGA and the main control CPU, and establishing PCIe connection between the slave device FPGA and the main control CPU;
step 2: and monitoring the communication state between the master control CPU and the slave device FPGA through the state monitoring high-reliability antifuse FPGA.
Optionally, the method further comprises:
and step 3: and responding an external reset signal through the state monitoring high-reliability antifuse FPGA, and executing reset and restart of the main control CPU.
Optionally, the step 1 includes:
step 1.1: starting the state monitoring high-reliability antifuse FPGA;
step 1.2: if the slave device FPGA is powered on, loading a program in a starting program storage chip of the slave device FPGA into the slave device FPGA;
step 1.3: when the state monitoring high-reliability antifuse FPGA monitors that the FPGA of the slave device is successfully initialized, a power supply enabling control signal is sent to a power supply DC _ DC module of a main control CPU to control the power supply DC _ DC module of the main control CPU to supply power to the main control CPU, and the main control CPU starts to be started automatically;
step 1.4: after the master control CPU is started automatically, a PCIe link request is sent to the slave device FPGA to establish PCIe pairing with the slave device FPGA;
step 1.5: the slave device FPGA feeds back a PCIe link state to the state monitoring high-reliability antifuse FPGA through a state monitoring signal, so as to prompt that the master control CPU is successfully started, the slave device FPGA is successfully started and PCIe connection is successfully established;
step 1.6: loading a slave device FPGA from a slave device FPGA starting program storage chip program to start counting, if the set overtime duration is exceeded and the starting failure register count of the state monitoring high-reliability antifuse FPGA is less than 3, returning to execute the step 1.2, and adding 1 to the starting failure register count of the state monitoring high-reliability antifuse FPGA;
step 1.7: and if the count of the starting failure register of the state monitoring high-reliability antifuse FPGA is 3, stopping the starting process and sending starting failure prompt information.
Optionally, the step 2 includes:
step 2.1: the master control CPU writes the accumulated number into a system state register appointed by the slave equipment FPGA at fixed time;
step 2.2: the state monitoring high-reliability antifuse FPGA acquires the accumulated number from the slave FPGA periodically through state monitoring;
step 2.3: and if the master control CPU or the slave device FPGA fails, the accumulation of the accumulated number is stopped, the PCIe link is set to be invalid through the state monitoring high-reliability antifuse FPGA, and the step 1.6 is executed in a return mode.
Optionally, the step 2.1 comprises:
step 2.1.1: initiating a PCIe link request to a slave device FPGA;
step 2.1.2: reading state telemetering from the equipment FPGA at fixed time;
step 2.1.3: and judging the state telemetering state of the slave equipment FPGA, and if the state telemetering state of the slave equipment FPGA is normal, writing the accumulated number into a system state register appointed by the slave equipment FPGA at regular time.
Optionally, the method further comprises any one or any of the following steps:
the method comprises the steps that a master control CPU obtains an initiated DMA (Direct Memory Access) remote measurement of a slave device FPGA;
the master control CPU actively initiates a DMA interrupt request to the slave device FPGA;
and the master control CPU calculates or stores the DMA data of the slave equipment FPGA.
Optionally, the method further comprises any one or any of the following steps:
the slave device FPGA responds to a PCIe link request of the master control CPU;
the slave device FPGA sends out a corresponding state signal or interrupt after the PCIe link is established successfully;
the slave device FPGA sends self state telemetering to the master control CPU at regular time;
the slave device FPGA sends the accumulated number of the system state register to the state monitoring high-reliability antifuse FPGA at regular time;
the slave device FPGA responds to the overload instruction;
and the slave device FPGA responds to the DMA interrupt request of the master control CPU.
In a second aspect, the present invention provides a PCIe bus-based communication system to which the PCIe bus-based communication method described in any one of the first aspects is applied, where the system includes: the system comprises a master control CPU, a slave device FPGA, a state monitoring high-reliability antifuse FPGA, a controllable master control CPU power supply DC _ DC module and a slave device FPGA starting program storage chip; the controllable main control CPU power supply DC _ DC module is used for monitoring a power supply enabling signal sent by the high-reliability antifuse FPGA according to the state and supplying power to the main control CPU; the slave device FPGA is in communication connection with the master control CPU through a PCIe bus; the state monitoring high-reliability antifuse FPGA is in communication connection with a storage chip of a starting program of the FPGA of the slave device through an interface.
Optionally, the method further comprises: an AC coupling capacitor; the AC coupling capacitor is arranged on the PCIe bus and used for preventing the slave device FPGA from backward flowing voltage to the master control CPU.
Optionally, the state monitoring highly reliable antifuse FPGA is connected to an external circuit, and is configured to receive an external reset signal, so that the communication system reloads according to the reset signal.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a communication method and a system based on PCIe bus,
according to the communication method and system based on the PCIe bus, the transmission speed of the data transmission interface in the data transmission product is improved through the targeted reliability design, the compatibility and the universality of the data transmission interface are improved, the reliability of the data transmission product is not reduced on the basis, the method and system have positive reference significance for improving the transmission speed and the reliability guarantee of the satellite borne data transmission system, and have good practical engineering application value in the aerospace field.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a functional block diagram of a PCIe bus based communication system in accordance with the present invention;
FIG. 2 is a schematic diagram illustrating an initialization process of a PCIe bus based communication system according to the present invention;
fig. 3 is a flowchart illustrating an operation process of a PCIe bus based communication system according to the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Fig. 1 is a schematic block diagram of a PCIe bus based communication system according to the present invention, as shown in fig. 1, the system includes: the system comprises a master control CPU, a slave device FPGA, a state monitoring high-reliability antifuse FPGA, a controllable master control CPU power supply DC _ DC module and a slave device FPGA starting program storage chip; the controllable main control CPU power supply DC _ DC module is used for monitoring a power supply enabling signal sent by the high-reliability antifuse FPGA according to the state and supplying power to the main control CPU; the slave device FPGA is in communication connection with the master control CPU through a PCIe bus; and the state monitoring high-reliability antifuse FPGA is in communication connection with the FPGA starting program storage chip of the slave device through an interface.
Optionally, the method further comprises: an AC coupling capacitor; the AC coupling capacitor is arranged on the PCIe bus and used for preventing the slave device FPGA from backward flowing voltage to the master control CPU.
Optionally, the state monitoring highly reliable antifuse FPGA is connected to an external circuit for receiving an external reset signal, so that the communication system reloads according to the reset signal.
Illustratively, the slave device FPGA is provided with a high speed PCIe transport interface; an initialization success signal or interrupt can be sent; responding to a PCIe link request of the main control CPU, and sending a corresponding state signal or interruption after the PCIe link is successfully established; the self state is telemetered and sent to a main control CPU at regular time; the accumulated number of the system state register is sent to a state monitoring high-reliability antifuse FPGA at regular time; may respond to a reload instruction; may respond to DMA interrupt requests from the master CPU.
For an exemplary state monitoring high-reliability antifuse FPGA, the main functional requirements are as follows: the wide-temperature high-reliability antifuse Field Programmable Gate Array (FPGA) with space amplitude resistance index is selected, and has the characteristic of long-term reliable work in a space environment with high radiation and high temperature difference; capable of responding to an external reset signal; the starting program stored in the FPGA starting program storage chip of the external slave equipment can provide a starting program loading function for the slave equipment in a parallel or serial communication mode supported by the slave equipment; the relevant status of the slave FPGA is obtained and responded to as described in claim one.
For example, the controllable master CPU supplies DC _ DC, and the main functional requirements are: the corresponding power supply can be controlled by controlling the enable signal, if the power supply is not enabled, the power supply output is low, and if the power supply is enabled, the corresponding power supply is output; the power-up and power-down sequences that should meet the requirements of the master CPU.
Illustratively, the master CPU and slave FPGA should only have PCIe common circuitry, and the PCIe bus needs to be isolated by AC coupling capacitors to prevent a back-flowing voltage that may exist when the master CPU is not powered while the slave FPGA is powered up. And power supply isolation is designed among the master control CPU, the slave device FPGA and the state monitoring high-reliability antifuse FPGA, so that the system reliability is improved.
Illustratively, the status monitoring signal between the slave device FPGA and the monitoring high-reliability antifuse FPGA can be realized by, but is not limited to, a parallel bus, an RS422 or a total interruption signal, and the like. And starting a successful overtime count, wherein the count is not accumulated and cleared after the PCIe link is valid, and the count is accumulated if the PCIe link is invalid. In this embodiment, the timeout duration is related to the transmission speed of the slave device FPGA initiator memory chip, and the slave device FPGA initiator loading duration plus 20s is generally selected as the timeout duration.
Illustratively, the system can realize the overloading of the PCIe system through self state monitoring; the system can respond to an external reset signal to realize the overloading of the PCIe system; the system state monitoring and the heavy load control are realized through a high-reliability antifuse FPGA; the system carries out power supply isolation design on the PCIe main device and the PCIe slave device, and if one of the PCIe main device and the slave device fails and cannot be recovered, the other part of functions are saved.
The invention discloses a PCIe bus-based communication method which is applied to a communication system comprising a master control CPU, a slave device FPGA, a state monitoring high-reliability antifuse FPGA, a controllable master control CPU power supply DC _ DC module and a slave device FPGA start program storage chip, and the method comprises the following steps:
step 1: starting a state monitoring high-reliability antifuse FPGA and a main control CPU, and establishing PCIe connection between the slave device FPGA and the main control CPU;
step 2: and monitoring the communication state between the master control CPU and the slave device FPGA through the state monitoring high-reliability antifuse FPGA.
In the embodiment, a PCIe bus communication mode with the highest application degree in the industrial and commercial data transmission fields is adopted as a basis, and the characteristics of high speed, universality and expandability are utilized; simultaneously, the requirements of the master device and the slave device on the power-on sequence and the hot plugging incapability are met; aiming at the characteristics of high-temperature and high-radiation working environment in the aerospace field; the on-orbit irreparable characteristic of an aerospace product is considered, partial working modes of system faults are added, and a high-reliability PCIe summary architecture design which can be used in the aerospace field is designed.
Fig. 2 is a schematic diagram illustrating an initialization process of a communication system based on a PCIe bus according to the present invention, and fig. 3 is a schematic diagram illustrating an operation process of the communication system based on the PCIe bus according to the present invention. Referring to fig. 2 and 3, step 1 may include:
step 1.1: starting the state monitoring high-reliability antifuse FPGA;
step 1.2: if the slave device FPGA is powered on, loading a program in a starting program storage chip of the slave device FPGA into the slave device FPGA;
step 1.3: when the state monitoring high-reliability antifuse FPGA monitors that the FPGA of the slave device is successfully initialized, a power supply enabling control signal is sent to a power supply DC _ DC module of the master control CPU to control the power supply DC _ DC module of the master control CPU to supply power to the master control CPU, and the master control CPU starts to be started automatically;
step 1.4: after the master control CPU is started automatically, a PCIe link request is sent to the FPGA of the slave equipment so as to establish PCIe pairing with the FPGA of the slave equipment;
step 1.5: the slave device FPGA feeds back the PCIe link state to the state monitoring high-reliability antifuse FPGA through a state monitoring signal so as to prompt the master control CPU to be started successfully, the slave device FPGA to be started successfully and PCIe connection to be established successfully;
step 1.6: loading a slave device FPGA from a slave device FPGA starting program storage chip program to start counting, if the set overtime duration is exceeded and the starting failure register count of the state monitoring high-reliability antifuse FPGA is less than 3, returning to execute the step 1.2, and adding 1 to the starting failure register count of the state monitoring high-reliability antifuse FPGA;
step 1.7: and if the count of the starting failure register of the state monitoring high-reliability antifuse FPGA is 3, stopping the starting process and sending starting failure prompt information.
Optionally, step 2 above may include:
step 2.1: the master control CPU writes the accumulated number into a system state register appointed by the slave equipment FPGA at fixed time;
step 2.2: the state monitoring high-reliability antifuse FPGA acquires the accumulated number from the slave FPGA regularly through state monitoring;
step 2.3: and if the master control CPU or the slave device FPGA fails, the accumulation of the accumulated number is stopped, the PCIe link is set to be invalid through the state monitoring high-reliability antifuse FPGA, and the step 1.6 is executed in a return mode.
Optionally, step 2.1 comprises:
step 2.1.1: initiating a PCIe link request to a slave device FPGA;
step 2.1.2: reading state telemetering from the equipment FPGA at fixed time;
step 2.1.3: and judging the state telemetering state of the slave equipment FPGA, and if the state telemetering state of the slave equipment FPGA is normal, writing the accumulated number into a system state register appointed by the slave equipment FPGA at regular time.
Optionally, the method further comprises any one or any of the following steps:
the master control CPU obtains the initiated DMA remote measurement of the slave equipment FPGA;
the master control CPU actively initiates a DMA interrupt request to the slave device FPGA;
and the master control CPU calculates or stores the DMA data of the slave equipment FPGA.
Optionally, the method further comprises any one or any of the following steps:
the slave device FPGA responds to a PCIe link request of the master control CPU;
the slave device FPGA sends out a corresponding state signal or interrupt after the PCIe link is established successfully;
the slave device FPGA sends self state telemetering to the master control CPU at regular time;
the slave device FPGA sends the accumulated number of the system state register to the state monitoring high-reliability antifuse FPGA at regular time;
the slave device FPGA responds to the overload instruction;
and the slave device FPGA responds to the DMA interrupt request of the master control CPU.
The invention refers to a standard PCIe bus architecture to realize the PCIe high-speed data communication function under a standard protocol. Through function division, a master control CPU and a slave device FPGA are designed in a split mode, a high-reliability state monitoring high-reliability antifuse FPGA which is mature in technology and widely applied to aerospace products is independently established to monitor the state of the whole system, and a fault processing scheme of system overload or system part work is adopted for abnormal conditions.
It should be noted that, the steps in the PCIe bus-based communication method provided in the present invention may be implemented by using corresponding modules, devices, units, and the like in the PCIe bus-based communication system, and those skilled in the art may refer to the technical solution of the system to implement the step flow of the method, that is, the embodiment in the system may be understood as a preferred example of the implementation method, and details are not described herein.
Those skilled in the art will appreciate that, in addition to implementing the system and its various devices provided by the present invention in purely computer readable program code means, the method steps can be fully programmed to implement the same functions by implementing the system and its various devices in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices thereof provided by the present invention can be regarded as a hardware component, and the devices included in the system and various devices thereof for realizing various functions can also be regarded as structures in the hardware component; means for performing the functions may also be regarded as structures within both software modules and hardware components for performing the methods.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (8)
1. A communication method based on a PCIe bus is characterized in that the method is applied to a communication system comprising a master control CPU, a slave device FPGA, a state monitoring high-reliability antifuse FPGA, a controllable master control CPU power supply DC _ DC module and a slave device FPGA startup program storage chip, and the method comprises the following steps:
step 1: starting the state monitoring high-reliability antifuse FPGA and the main control CPU, and establishing PCIe connection between the slave device FPGA and the main control CPU;
step 1.1: starting the state monitoring high-reliability antifuse FPGA;
step 1.2: if the slave device FPGA is powered on, loading a program in a starting program storage chip of the slave device FPGA into the slave device FPGA;
step 1.3: when the state monitoring high-reliability antifuse FPGA monitors that the FPGA of the slave device is successfully initialized, a power supply enabling control signal is sent to a power supply DC _ DC module of a main control CPU to control the power supply DC _ DC module of the main control CPU to supply power to the main control CPU, and the main control CPU starts to be started automatically;
step 1.4: after the master control CPU is started automatically, a PCIe link request is sent to the slave device FPGA to establish PCIe pairing with the slave device FPGA;
step 1.5: the slave device FPGA feeds back a PCIe link state to the state monitoring high-reliability antifuse FPGA through a state monitoring signal, so as to prompt that the master control CPU is successfully started, the slave device FPGA is successfully started and PCIe connection is successfully established;
step 1.6: loading a slave device FPGA from a slave device FPGA starting program storage chip program to start counting, if the set overtime duration is exceeded and the starting failure register count of the state monitoring high-reliability antifuse FPGA is less than 3, returning to execute the step 1.2, and adding 1 to the starting failure register count of the state monitoring high-reliability antifuse FPGA;
step 1.7: if the count of the starting failure register of the state monitoring high-reliability antifuse FPGA is 3, stopping the starting process and sending starting failure prompt information;
step 2: and monitoring the communication state between the master control CPU and the slave device FPGA through the state monitoring high-reliability antifuse FPGA.
2. The PCIe bus based communication method of claim 1, the method further comprising:
and step 3: and responding an external reset signal through the state monitoring high-reliability antifuse FPGA, and executing reset and restart of the main control CPU.
3. The PCIe bus based communication method of claim 1, wherein the step 2 comprises:
step 2.1: the master control CPU writes the accumulated number into a system state register appointed by the slave equipment FPGA at fixed time;
step 2.2: the state monitoring high-reliability antifuse FPGA acquires the accumulated number from the slave FPGA regularly through state monitoring;
step 2.3: and if the master control CPU or the slave device FPGA fails, the accumulation of the accumulated number is stopped, the PCIe link is set to be invalid through the state monitoring high-reliability antifuse FPGA, and the step 1.6 is executed in a return mode.
4. The PCIe bus based communication method of claim 3, wherein the step 2.1 comprises:
step 2.1.1: initiating a PCIe link request to a slave device FPGA;
step 2.1.2: reading state telemetering from the equipment FPGA at fixed time;
step 2.1.3: and judging the state telemetering state of the slave equipment FPGA, and if the state telemetering state of the slave equipment FPGA is normal, writing the accumulated number into a system state register appointed by the slave equipment FPGA at regular time.
5. The PCIe bus based communication method of claim 1, wherein the method further comprises any one or any multiple of:
the master control CPU obtains the initiated DMA remote measurement of the slave equipment FPGA;
the master control CPU actively initiates a DMA interrupt request to the slave device FPGA;
and the master control CPU calculates or stores the DMA data of the slave equipment FPGA.
6. The PCIe bus based communication method of claim 1, wherein the method further comprises any one or any multiple of:
the slave device FPGA responds to a PCIe link request of the master control CPU;
the slave device FPGA sends out a corresponding state signal or interrupt after the PCIe link is established successfully;
the slave device FPGA sends self state telemetering to the master control CPU at regular time;
the slave device FPGA sends the accumulated number of the system state register to the state monitoring high-reliability antifuse FPGA at regular time;
the slave device FPGA responds to the overload instruction;
and the slave device FPGA responds to the DMA interrupt request of the master control CPU.
7. A PCIe bus based communication system applying the PCIe bus based communication method of any one of claims 1 to 6, the system comprising: the system comprises a master control CPU, a slave device FPGA, a state monitoring high-reliability antifuse FPGA, a controllable master control CPU power supply DC _ DC module and a slave device FPGA starting program storage chip; the controllable main control CPU power supply DC _ DC module is used for monitoring a power supply enabling signal sent by the high-reliability antifuse FPGA according to the state and supplying power to the main control CPU; the slave device FPGA is in communication connection with the master control CPU through a PCIe bus; the state monitoring high-reliability antifuse FPGA is in communication connection with a slave device FPGA starting program storage chip through an interface.
8. The PCIe bus based communication system of claim 7, wherein the status monitoring high reliability antifuse FPGA is coupled to an external circuit for receiving an external reset signal to enable reloading of the communication system based on the reset signal.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105490844A (en) * | 2015-12-05 | 2016-04-13 | 中国航空工业集团公司洛阳电光设备研究所 | PCIe port reconstruction method |
| CN105652780A (en) * | 2015-12-21 | 2016-06-08 | 深圳市立山信息技术有限公司 | Intelligent three-dimensional garage control system and method |
| CN205539488U (en) * | 2016-01-21 | 2016-08-31 | 航天恒星科技有限公司 | Miniaturized star carries global positioning system GPS receiver |
| CN106325900A (en) * | 2015-06-24 | 2017-01-11 | 赵智达 | Design of burner for anti-fuse FPGA (Field Programmable Gate Array) |
| CN206147603U (en) * | 2016-08-18 | 2017-05-03 | 四川赛狄信息技术有限公司 | Information processing apparatus that can monitor |
| CN106708545A (en) * | 2015-08-17 | 2017-05-24 | 卢骏 | Novel programmer design applied to anti-fuse FPGA |
| CN206489484U (en) * | 2017-02-28 | 2017-09-12 | 江西华东电气有限公司 | A kind of Embedded Hardware Platform client/server layout designs |
| CN109582626A (en) * | 2018-12-03 | 2019-04-05 | 郑州云海信息技术有限公司 | A kind of method, apparatus, equipment and readable storage medium storing program for executing accessing bus |
| CN110119112A (en) * | 2019-05-06 | 2019-08-13 | 上海航天电子有限公司 | A kind of autonomous recovery system of reliable SRAM type FPGA and method |
-
2020
- 2020-04-07 CN CN202010267176.9A patent/CN111400211B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106325900A (en) * | 2015-06-24 | 2017-01-11 | 赵智达 | Design of burner for anti-fuse FPGA (Field Programmable Gate Array) |
| CN106708545A (en) * | 2015-08-17 | 2017-05-24 | 卢骏 | Novel programmer design applied to anti-fuse FPGA |
| CN105490844A (en) * | 2015-12-05 | 2016-04-13 | 中国航空工业集团公司洛阳电光设备研究所 | PCIe port reconstruction method |
| CN105652780A (en) * | 2015-12-21 | 2016-06-08 | 深圳市立山信息技术有限公司 | Intelligent three-dimensional garage control system and method |
| CN205539488U (en) * | 2016-01-21 | 2016-08-31 | 航天恒星科技有限公司 | Miniaturized star carries global positioning system GPS receiver |
| CN206147603U (en) * | 2016-08-18 | 2017-05-03 | 四川赛狄信息技术有限公司 | Information processing apparatus that can monitor |
| CN206489484U (en) * | 2017-02-28 | 2017-09-12 | 江西华东电气有限公司 | A kind of Embedded Hardware Platform client/server layout designs |
| CN109582626A (en) * | 2018-12-03 | 2019-04-05 | 郑州云海信息技术有限公司 | A kind of method, apparatus, equipment and readable storage medium storing program for executing accessing bus |
| CN110119112A (en) * | 2019-05-06 | 2019-08-13 | 上海航天电子有限公司 | A kind of autonomous recovery system of reliable SRAM type FPGA and method |
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