CN111400109B - Dual-machine redundancy backup system based on PCIe high-speed bus interface - Google Patents
Dual-machine redundancy backup system based on PCIe high-speed bus interface Download PDFInfo
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- CN111400109B CN111400109B CN202010268062.6A CN202010268062A CN111400109B CN 111400109 B CN111400109 B CN 111400109B CN 202010268062 A CN202010268062 A CN 202010268062A CN 111400109 B CN111400109 B CN 111400109B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a dual-computer redundancy backup system based on a PCIe high-speed bus interface, which comprises: the system comprises a main control CPU of a machine A, a main control CPU of a machine B, a power supply module of the machine A, a power supply module of the machine B, a state monitoring high-reliability anti-fuse FPGA and a slave device FPGA; switching the cold backup of the PCIe bus double machines through the state monitoring high-reliability anti-fuse FPGA, and improving the reliability of the whole communication system and prolonging the service life of the system if the double machines are full-function backups; if the double machines are different functions, the function expansion can be realized through the cutting machine, and the system functionality and flexibility are improved.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a dual-machine redundancy backup system based on a PCIe high-speed bus interface.
Background
With the progress of the satellite-borne load technology, the load data volume is greatly increased. In the field of satellite-borne data transmission, the conventional Low-voltage differential signaling (Low-Voltage Differential Signaling, LVDS) data transmission link cannot meet the requirement of high-speed data transmission in terms of speed and generality. And there is an increasing demand for high-speed and reliable bus data transfer.
However, if a custom high-speed data bus communication scheme is developed alone, it is difficult to realize both in terms of cost and reliability. Therefore, the reliability of the conventional and universal high-speed bus is guaranteed to be one of the most feasible schemes.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a dual-machine redundancy backup system based on a PCIe high-speed bus interface.
The invention provides a dual-computer redundancy backup system based on PCIe (PCIexpress) high-speed bus interface, which comprises: the system comprises a main control CPU of a machine A, a main control CPU of a machine B, a power supply module of the machine A, a power supply module of the machine B, a state monitoring high-reliability anti-fuse FPGA (Field-Programmable GateArray, field programmable gate array) and a slave device FPGA; the A machine power supply module is used for monitoring a power supply enabling signal sent by the high-reliability anti-fuse FPGA according to the state and supplying power to a main control CPU (central processing unit) of the A machine; the B machine power supply module is used for monitoring a power supply enabling signal sent by the high-reliability anti-fuse FPGA according to the state and supplying power to the B machine main control CPU; the slave device FPGA is respectively in communication connection with the A machine main control CPU and the B machine main control CPU through PCIe high-speed buses; the A machine main control CPU and the B machine main control CPU are mutually backed up, and the A machine main control CPU and the B machine main control CPU are not powered on to work at the same time.
Optionally, the state monitoring high-reliability anti-fuse FPGA is in communication connection with the slave device FPGA starting A machine main control CPU program storage chip through a first interface, and the state monitoring high-reliability anti-fuse FPGA is in communication connection with the slave device FPGA starting B machine main control CPU program storage chip through a second interface.
Optionally, the state monitoring high-reliability anti-fuse FPGA is connected with an external circuit and is used for receiving an external reset signal or an external switching instruction;
when the state monitoring high-reliability anti-fuse FPGA receives an external reset signal, the current running states of the A machine main control CPU and the B machine main control CPU are maintained;
and when the state monitoring high-reliability anti-fuse FPGA receives an external machine cutting instruction, the current running states of the A machine main control CPU and the B machine main control CPU are switched.
Optionally, the method further comprises: an AC coupling capacitance; the AC coupling capacitor is arranged on the PCIe high-speed bus and used for preventing the slave device FPGA from flowing backward to the A machine main control CPU and the B machine main control CPU.
Optionally, when the main control CPU of the a machine is in a working state, the state monitoring high-reliability antifuse FPGA sends a power supply enabling signal of the a machine to the a machine power supply module to be disabled, and the main control CPU of the a machine is turned off; the state monitoring high-reliability anti-fuse FPGA sends a reload instruction to the slave device FPGA; the state monitoring high-reliability anti-fuse FPGA switches the slave device FPGA to start a program B, and a main control CPU program storage chip configures the slave device FPGA; after the configuration of the slave device FPGA is finished, the state monitoring high-reliability antifuse FPGA is informed of the state monitoring high-reliability antifuse to send a B machine power supply enabling signal to enable, and the B machine main control CPU is started; the B machine master control CPU initiates a PCIe link request and establishes PCIe bus connection with the FPGA; and the slave device FPGA sends PCIe link success state telemetry to the state monitoring high-reliability antifuse FPGA.
Optionally, when the B-machine main control CPU is in a working state, the state monitoring high-reliability antifuse FPGA sends a B-machine power supply enabling signal to the B-machine power supply module to disable, and closes the B-machine main control CPU; the state monitoring high-reliability anti-fuse FPGA sends a reload instruction to the slave device FPGA; the state monitoring high-reliability anti-fuse FPGA switches the slave device FPGA to start a program A machine to master a CPU program storage chip to configure the slave device FPGA; after the configuration of the slave device FPGA is finished, the state monitoring high-reliability antifuse FPGA is informed of the state monitoring high-reliability antifuse to send an A machine power supply enabling signal to enable, and the A machine main control CPU is started; the A machine main control CPU initiates a PCIe link request and establishes PCIe bus connection with the FPGA; and the slave device FPGA sends PCIe link success state telemetry to the state monitoring high-reliability antifuse FPGA.
Compared with the prior art, the invention has the following beneficial effects:
the dual-computer redundancy backup system based on the PCIe high-speed bus interface improves the reliability of products and prolongs the service life of the products through the dual-computer redundancy cold backup design, improves the expandability of the products under the condition of having requirements on the expandability of the products, has positive reference significance for improving the transmission rate, the reliability guarantee and the use flexibility of the satellite-borne data transmission system, and has good practical engineering application value in the field of aerospace.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a schematic block diagram of a dual-machine redundancy backup system based on a PCIe high-speed bus interface provided by the invention;
FIG. 2 is a schematic flow chart of switching a dual-machine redundancy backup system from an A machine to a B machine based on a PCIe high-speed bus interface;
fig. 3 is a schematic flow chart of switching a dual-machine redundancy backup system from a B machine to an a machine based on a PCIe high-speed bus interface.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.
Fig. 1 is a schematic block diagram of a dual-machine redundancy backup system based on a PCIe high-speed bus interface according to the present invention, where, as shown in fig. 1, the system in this embodiment includes: the system comprises a main control CPU of a machine A, a main control CPU of a machine B, a power supply module of the machine A, a power supply module of the machine B, a state monitoring high-reliability anti-fuse FPGA and a slave device FPGA; the A machine power supply module is used for monitoring a power supply enabling signal sent by the high-reliability anti-fuse FPGA according to the state and supplying power to the A machine main control CPU; the B machine power supply module is used for monitoring a power supply enabling signal sent by the high-reliability anti-fuse FPGA according to the state and supplying power to the B machine main control CPU; the slave device FPGA is respectively connected with the A machine main control CPU and the B machine main control CPU in a communication way through PCIe high-speed buses; the main control CPU of the A machine and the main control CPU of the B machine are mutually backup, and the main control CPU of the A machine and the main control CPU of the B machine do not power on at the same time.
In this embodiment, the main control CPU of the a machine and the main control CPU of the B machine form a main control CPU dual machine, and the power supply module of the a machine and the power supply module of the B machine form a controllable main control CPU power supply dc_dc (direct current-direct current) dual machine. The working mode of the current PCIe bus dual-machine redundancy cold backup architecture for aerospace is as follows: the main control CPU and the controllable main control CPU supply power DC_DC for dual-machine cold backup, namely, only the single machine can work at the same time, the dual machines are not related to each other, and the dual machines are not electrified at the same time; the slave device FPGA starts the program storage chip to be in a double-machine state, and the state monitoring high-reliability anti-fuse FPGA and the slave device FPGA are in a normally-open state.
In the embodiment, the functions of the A/B machine can be completely consistent, double redundancy backup of the whole system is realized, and the service life and reliability of the system are improved; the functions of the A/B machine can be inconsistent, the function expansion of the whole system is realized, the switching between different working modes can be realized according to the different states of the A/B machine at each moment, and the system functionality and the application flexibility are improved.
In this embodiment, whether corresponding power supply exists or not may be controlled by controlling the enable signal, if not, the power supply output is low, and if enabled, the corresponding power supply is output; the power-on time sequence and the power-off time sequence which are required by the main control CPU are required to be met.
Optionally, the state monitoring high-reliability anti-fuse FPGA is in communication connection with the slave device FPGA start-up A machine master control CPU program storage chip through a first interface, and the state monitoring high-reliability anti-fuse FPGA is in communication connection with the slave device FPGA start-up B machine master control CPU program storage chip through a second interface.
In the embodiment, two slave device FPGA start program memory chips are required, wherein one slave device FPGA start A master control CPU program is stored; the other storage slave device FPGA starts the B machine main control CPU program. The slave device FPGA starts the A machine main control CPU program storage chip and the slave device FPGA starts the B machine main control CPU program storage chip to form a slave device FPGA starting program storage chip double machine, and the slave device FPGA starting program storage chip double machine is used for realizing the starting of the A machine main control CPU and the B machine main control CPU.
Furthermore, because the data transmission interfaces for aerospace are mainly non-standard interfaces such as LVDS, TLK2711 and the like, the non-standard interfaces are provided for the system from the equipment FPGA to be converted into PCIe standard interface functions; and the slave device FPGA realizes the external interface of the system. In general, in an aerospace data transmission product, data transmission receives load data, and most of the load data is designed as a single machine, and a double data interface cannot be provided, so that a slave device FPGA product cannot be designed as a double machine in the invention, and the load data is designed as a single machine. In this embodiment, the slave FPGA should have two sets of PCIe slave interfaces.
The state monitoring high-reliability anti-fuse FPGA is characterized in that the state monitoring high-reliability anti-fuse FPGA is selected to be a wide-temperature high-reliability anti-fuse FPGA with a space amplitude resistance index and has the characteristic of long-term reliable operation in a space environment with high radiation and high temperature difference; capable of responding to an external reset signal; is capable of responding to a cut instruction and performing one of the cut steps of the claim according to the instruction to perform the relevant operation.
Optionally, the state monitoring high-reliability antifuse FPGA is connected to an external circuit, and is configured to receive an external reset signal or an external switching instruction. When the state monitoring high-reliability anti-fuse FPGA receives an external reset signal, the current running states of the main control CPU of the A machine and the main control CPU of the B machine are maintained. When the state monitoring high-reliability antifuse FPGA receives an external machine cutting instruction, the current running states of the main control CPU of the A machine and the main control CPU of the B machine are switched.
In this embodiment, when the dual-redundancy backup system based on the PCIe high-speed bus interface may respond to an external reset operation, a/B machine switching is not performed before and after the reset, and a state of the a/B machine before the reset is maintained.
Optionally, the method further comprises: an AC coupling capacitance; the AC coupling capacitor is arranged on the PCIe high-speed bus and used for preventing the slave device FPGA from flowing backward to the A machine main control CPU and the B machine main control CPU.
In this embodiment, the a/B master CPU and the slave FPGA should have only PCIe common circuits, and PCIe buses need to be isolated by AC coupling capacitors, so as to prevent reverse voltage that may exist when the slave FPGA starts and the master CPU is not powered on; the power supply isolation is designed between the master control CPU, the slave device FPGA and the state monitoring high-reliability anti-fuse FPGA, so that the reliability of the system is improved; the a/B master CPU related circuitry needs to be fully isolated.
Fig. 2 is a schematic flow chart of switching a dual-machine redundancy backup system from an a machine to a B machine based on a PCIe high-speed bus interface. As shown in fig. 2, when the main control CPU of the a machine is in a working state, the state monitoring high-reliability antifuse FPGA sends a power supply enabling signal of the a machine to the a machine power supply module to be disabled, and the main control CPU of the a machine is closed; the state monitoring high-reliability anti-fuse FPGA sends a reload instruction to the slave device FPGA; the state monitoring high-reliability anti-fuse FPGA switches the slave device FPGA to start the program B machine to master the CPU program storage chip to configure the slave device FPGA; after the configuration of the slave device FPGA is finished, the state monitoring high-reliability anti-fuse FPGA is informed of the state monitoring high-reliability anti-fuse FPGA to send a B machine power supply enabling signal to enable, and a B machine main control CPU is started; b, the main control CPU of the machine initiates a PCIe link request and establishes PCIe bus connection with the FPGA of the equipment; and sending PCIe link success state telemetry to the state monitoring high-reliability anti-fuse FPGA by the slave device FPGA.
Fig. 3 is a schematic flow chart of switching a dual-machine redundancy backup system from a B machine to an a machine based on a PCIe high-speed bus interface. As shown in fig. 3, when the B-machine main control CPU is in a working state, the state monitoring high-reliability antifuse FPGA sends a B-machine power supply enabling signal to the B-machine power supply module to be disabled, and the B-machine main control CPU is turned off; the state monitoring high-reliability anti-fuse FPGA sends a reload instruction to the slave device FPGA; the state monitoring high-reliability anti-fuse FPGA switches the slave device FPGA to start the program A machine to master the CPU program storage chip to configure the slave device FPGA; after the configuration of the slave device FPGA is finished, the state monitoring high-reliability anti-fuse FPGA is informed of the state monitoring high-reliability anti-fuse FPGA to send a power supply enabling signal of the A machine to be enabled, and a main control CPU of the A machine is started; the A machine master control CPU initiates a PCIe link request and establishes PCIe bus connection with the FPGA; and sending PCIe link success state telemetry to the state monitoring high-reliability anti-fuse FPGA by the slave device FPGA.
The invention adopts PCIe bus communication mode with highest application degree in the industrial and commercial data transmission fields as the basis, and utilizes the characteristics of high speed, universality and expandability; meanwhile, aiming at the requirements of the master-slave equipment on the power-on time sequence and the non-hot plug; aiming at the characteristics of high-temperature and high-radiation working environment in the aerospace field; the characteristic that an aerospace product cannot be repaired on orbit is considered, the dual-machine cold backup switching of PCIe equipment is realized, and the reliability and the service life of the system are improved; meanwhile, the invention can improve the expansibility and the use flexibility of the system on the basis of guaranteeing the reliability of the system.
Those skilled in the art will appreciate that the invention provides a system and its individual devices that can be implemented entirely by logic programming of method steps, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc., in addition to the system and its individual devices being implemented in pure computer readable program code. Therefore, the system and various devices thereof provided by the present invention may be considered as a hardware component, and the devices included therein for implementing various functions may also be considered as structures within the hardware component; means for achieving the various functions may also be considered as being either a software module that implements the method or a structure within a hardware component.
The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the invention. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily without conflict.
Claims (4)
1. A dual-machine redundancy backup system based on a PCIe high-speed bus interface, comprising: the system comprises a main control CPU of a machine A, a main control CPU of a machine B, a power supply module of the machine A, a power supply module of the machine B, a state monitoring high-reliability anti-fuse FPGA and a slave device FPGA; the A machine power supply module is used for monitoring a power supply enabling signal sent by the high-reliability anti-fuse FPGA according to the state and supplying power to the A machine main control CPU; the B machine power supply module is used for monitoring a power supply enabling signal sent by the high-reliability anti-fuse FPGA according to the state and supplying power to the B machine main control CPU; the slave device FPGA is respectively in communication connection with the A machine main control CPU and the B machine main control CPU through PCIe high-speed buses; the A machine main control CPU and the B machine main control CPU are mutually backed up, and the A machine main control CPU and the B machine main control CPU are not powered on to work at the same time;
the system is switched from the machine A to the machine B by the following steps: the state monitoring high-reliability anti-fuse FPGA sends an A machine power supply enabling signal to the A machine power supply module to be disabled, and the A machine main control CPU is closed; the state monitoring high-reliability anti-fuse FPGA sends a reload instruction to the slave device FPGA; the state monitoring high-reliability anti-fuse FPGA switching slave device FPGA starts a B machine main control CPU program storage chip to configure the slave device FPGA; after the configuration of the slave device FPGA is finished, the state monitoring high-reliability antifuse FPGA is informed of the state monitoring high-reliability antifuse to send a B machine power supply enabling signal to enable, and the B machine main control CPU is started; the B machine master control CPU initiates a PCIe link request and establishes PCIe bus connection with the FPGA; and the slave device FPGA sends PCIe link success state telemetry to the state monitoring high-reliability antifuse FPGA.
2. The PCIe high-speed bus interface based dual-machine redundancy backup system as set forth in claim 1 wherein the state monitoring high-reliability antifuse FPGA is in communication connection with the slave device FPGA start-up a master CPU program storage chip through a first interface and the state monitoring high-reliability antifuse FPGA is in communication connection with the slave device FPGA start-up B master CPU program storage chip through a second interface.
3. The PCIe high-speed bus interface based dual-machine redundancy backup system as set forth in claim 1 wherein the state monitoring high-reliability antifuse FPGA is connected to an external circuit for receiving an external reset signal or an external switch command;
when the state monitoring high-reliability anti-fuse FPGA receives an external reset signal, the current running states of the A machine main control CPU and the B machine main control CPU are maintained;
and when the state monitoring high-reliability anti-fuse FPGA receives an external machine cutting instruction, the current running states of the A machine main control CPU and the B machine main control CPU are switched.
4. The PCIe high-speed bus interface based dual-machine redundancy backup system as defined in any one of claims 1-3 wherein the system switching from B machine to a machine flow is: the state monitoring high-reliability anti-fuse FPGA sends a B machine power supply enabling signal to a B machine power supply module to be disabled, and a B machine main control CPU is closed; the state monitoring high-reliability anti-fuse FPGA sends a reload instruction to the slave device FPGA; the state monitoring high-reliability anti-fuse FPGA switching slave device FPGA starts an A machine main control CPU program storage chip to configure the slave device FPGA; after the configuration of the slave device FPGA is finished, the state monitoring high-reliability antifuse FPGA is informed of the state monitoring high-reliability antifuse to send an A machine power supply enabling signal to enable, and the A machine main control CPU is started; the A machine main control CPU initiates a PCIe link request and establishes PCIe bus connection with the FPGA; and the slave device FPGA sends PCIe link success state telemetry to the state monitoring high-reliability antifuse FPGA.
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