CN111400109A - Dual-computer redundancy backup system based on PCIe high-speed bus interface - Google Patents

Abstract

The invention provides a dual-computer redundancy backup system based on a PCIe high-speed bus interface, which comprises: the system comprises a machine A main control CPU, a machine B main control CPU, a machine A power supply module, a machine B power supply module, a state monitoring high-reliability antifuse FPGA and a slave device FPGA; the double-computer cold backup of the PCIe bus is switched through the state monitoring high-reliability antifuse FPGA, if the double computers are full-function backup, the reliability of the whole communication system can be improved, and the service life of the system is prolonged; if the double machines have different functions, function expansion can be realized through the cutter, and the functionality and the flexibility of the system are improved.

Description

Dual-machine redundant backup system based on PCIe high-speed bus interface

technical field

The invention relates to the field of communication technologies, in particular to a dual-machine redundant backup system based on a PCIe high-speed bus interface.

Background technique

With the advancement of spaceborne payload technology, the amount of payload data has greatly increased. In the field of spaceborne data transmission, the traditional Low-Voltage Differential Signaling (LVDS) data transmission link can no longer meet the needs of high-speed data transmission in terms of speed and versatility. The demand for high-speed and reliable bus data transmission is getting higher and higher.

However, if a self-defined high-speed digital bus communication scheme is developed alone, it is difficult to achieve both in terms of cost and reliability. Therefore, it is one of the most feasible solutions to carry out the corresponding reliability design for the traditional and general high-speed bus to ensure its reliability in the space environment.

SUMMARY OF THE INVENTION

In view of the defects in the prior art, the purpose of the present invention is to provide a dual-machine redundant backup system based on a PCIe high-speed bus interface.

A dual-machine redundant backup system based on PCIe (PCIexpress) high-speed bus interface provided according to the present invention includes: a main control CPU of machine A, a main control CPU of machine B, a power supply module of machine A, a power supply module of machine B, a state monitoring high Reliable anti-fuse FPGA (Field-Programmable GateArray, Field Programmable Gate Array), slave device FPGA; the A power supply module is used to monitor the power supply enable signal sent by the high-reliability anti-fuse FPGA according to the state, and send it to all The main control CPU (central processing unit) of the A machine is powered; the power supply module of the B machine is used to monitor the power supply enable signal sent by the high-reliability anti-fuse FPGA according to the state, and supply power to the main control CPU of the B machine; The slave device FPGA communicates with the main control CPU of the A machine and the main control CPU of the B machine respectively through the PCIe high-speed bus; wherein, the A machine main control CPU and the B machine main control CPU are mutually backup, and the The main control CPU of machine A and the main control CPU of machine B are not powered on and work at the same time.

Optionally, the state monitoring high-reliability anti-fuse FPGA is in communication connection with the slave device FPGA to start the A-machine main control CPU program storage chip through a first interface, and the state-monitoring high-reliability anti-fuse FPGA communicates with the slave device through a second interface. The device FPGA starts the communication connection of the main control CPU program memory chip of the B machine.

Optionally, the state monitoring high-reliability anti-fuse FPGA is connected to an external circuit for receiving an external reset signal or an external machine cutting instruction;

When the state monitoring high-reliability anti-fuse FPGA receives an external reset signal, the current operating states of the main control CPU of machine A and the main control CPU of machine B are maintained;

When the state monitoring high-reliability anti-fuse FPGA receives an external machine cutting instruction, it switches the current operating states of the main control CPU of the A machine and the main control CPU of the B machine.

Optionally, it also includes: an AC coupling capacitor; the AC coupling capacitor is arranged on the PCIe high-speed bus, to prevent the slave device FPGA from pouring back the main control CPU of the A machine and the main control CPU of the B machine Voltage.

Optionally, when the main control CPU of the A-machine is in a working state, the state monitoring high-reliability anti-fuse FPGA sends the A-machine power supply enable signal to the A-machine power supply module is disabled, and the A-machine main control is turned off. control CPU; the state monitoring high-reliability anti-fuse FPGA sends a reload instruction to the slave device FPGA; the state-monitoring high-reliability anti-fuse FPGA switches the slave device FPGA startup program B master control CPU program memory chip configuration slave The device FPGA; after the configuration of the slave device FPGA is completed, the state monitoring high-reliability anti-fuse FPGA is notified through the state monitoring signal to send the power supply enable signal of the B machine to enable, and the B machine main control CPU is started; the B machine main control The CPU initiates a PCIe link request to establish a PCIe bus connection with the slave device FPGA; the slave device FPGA sends a PCIe link successful state telemetry to the state monitoring high-reliability anti-fuse FPGA.

Optionally, when the main control CPU of the machine B is in a working state, the state monitoring high-reliability anti-fuse FPGA sends the power supply enable signal of the machine B to the power supply module of the machine B to be disabled, and the main control CPU of the machine B is turned off. The state monitoring high reliability anti-fuse FPGA sends a reload instruction to the slave device FPGA; the state monitoring high reliability anti-fuse FPGA switches the slave device FPGA startup program A machine master control CPU program memory chip configures the slave device FPGA; After the configuration of the slave device FPGA is completed, the state monitoring high-reliability anti-fuse FPGA is notified through the state monitoring signal to send the power supply enable signal of the A machine to enable, and the A machine main control CPU is started; the A machine main control CPU initiates the PCIe link Request to establish a PCIe bus connection with the slave device FPGA; the slave device FPGA sends the PCIe link successful state telemetry to the state monitoring high-reliability anti-fuse FPGA.

Compared with the prior art, the present invention has the following beneficial effects:

The dual-machine redundant backup system based on the PCIe high-speed bus interface provided by the present invention improves the reliability of the product, increases the life of the product through the design of the dual-machine redundant cold backup, and improves the product when there is a need for product scalability. It has positive reference significance for improving the transmission rate, reliability guarantee and use flexibility of the spaceborne data transmission system, and has good practical engineering application value in the aerospace field.

Description of drawings

Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings:

1 is a schematic block diagram of a dual-machine redundant backup system based on a PCIe high-speed bus interface provided by the present invention;

Fig. 2 is a kind of schematic flowchart of switching from machine A to machine B of a dual-machine redundant backup system based on PCIe high-speed bus interface provided by the present invention;

FIG. 3 is a schematic flowchart of switching from machine B to machine A in a dual-machine redundant backup system based on a PCIe high-speed bus interface provided by the present invention.

Detailed ways

The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the inventive concept. These all belong to the protection scope of the present invention.

Fig. 1 is a principle block diagram of a dual-machine redundant backup system based on PCIe high-speed bus interface provided by the present invention. As shown in Fig. 1, the system of this embodiment includes: a main control CPU of machine A, a main control CPU of machine B, A machine power supply module, B machine power supply module, state monitoring high-reliability anti-fuse FPGA, slave device FPGA; A machine power supply module is used to monitor the power supply enable signal sent by the high-reliability anti-fuse FPGA according to the state, to the A machine master control CPU power supply; the power supply module of machine B is used to monitor the power supply enable signal sent by the high-reliability anti-fuse FPGA according to the state, and supply power to the main control CPU of machine B; the slave device FPGA communicates with the main control CPU of machine A and machine B through PCIe high-speed bus respectively. Main control CPU communication connection; among them, the main control CPU of machine A and the main control CPU of machine B are mutually backup, and the main control CPU of machine A and the main control CPU of machine B are not powered on and work at the same time.

In this embodiment, the main control CPU of machine A and the main control CPU of machine B constitute dual main control CPUs, and the power supply module of machine A and the power supply module of machine B constitute a controllable main control CPU power supply DC_DC (direct current-direct current) dual machine. The current working mode of the PCIe bus dual-machine redundant cold backup architecture for aerospace is: the main control CPU and the controllable main control CPU power supply DC_DC is a dual-machine cold backup, that is, only a single machine can work at the same time, and the two machines are not related to each other. Power on at the same time; the slave device FPGA starts the program memory chip dual-computer, the state monitoring high-reliability anti-fuse FPGA and the slave device FPGA are in a normally-on state.

In this embodiment, the functions of the A/B machines can be completely consistent, realizing dual redundant backup of the entire system, improving the system life and reliability; the functions of the A/B machines can also be inconsistent, realizing the function expansion of the entire system, every moment According to the switch state of the A/B machine, switching between different working modes can be realized, which improves the system functionality and application flexibility.

In this embodiment, the presence or absence of the corresponding power supply can be controlled by the control enable signal. If it is not enabled, the power supply output is low, and if it is enabled, the corresponding power supply is output; it should meet the power-on sequence and power-off sequence required by the main control CPU. .

Optionally, the state-monitoring high-reliability anti-fuse FPGA is in communication connection with the slave device FPGA to start the main control CPU program memory chip of machine A through the first interface, and the state-monitoring high-reliability anti-fuse FPGA starts B with the slave device FPGA through the second interface. The main control CPU program memory chip communication connection.

In this embodiment, a total of two chips are required for the slave device FPGA to start the program storage chip, one of which stores the slave device FPGA to start the A-machine main control CPU program; The slave device FPGA starts the main control CPU program memory chip of machine A and the slave device FPGA starts the master control CPU program memory chip of machine B to form a dual-machine FPGA boot program memory chip from the device, which is used to realize the master control of the main control CPU of machine A and the main control of machine B. Startup of the CPU.

Further, because the aerospace data transmission interfaces are mainly non-standard interfaces such as LVDS and TLK2711, the slave device FPGA provides the system with non-standard interfaces and converts them into PCIe standard interface functions; and because the slave device FPGA realizes the external interface of the system. Generally, in aerospace data transmission products, the data transmission receives payload data, and most of the payload products are designed with a single machine and cannot provide dual data interfaces. Therefore, in the present invention, the slave device FPGA product cannot be designed for dual machines, and is a single machine design. In this embodiment, the slave device FPGA should have two sets of PCIe slave device interfaces.

It should be noted that the state monitoring high-reliability anti-fuse FPGA should choose a wide-temperature and high-reliability anti-fuse FPGA with a space resistance index, which has the characteristics of long-term reliable operation in a space environment with high radiation and high temperature difference; can respond to external The reset signal can respond to the machine cutting instruction, and execute the machine cutting step of claim one according to the instruction to complete the relevant operations.

Optionally, the state monitoring high-reliability anti-fuse FPGA is connected to an external circuit for receiving an external reset signal or an external machine cutting command. When the state monitoring high-reliability anti-fuse FPGA receives an external reset signal, it maintains the current running state of the main control CPU of machine A and the main control CPU of machine B. When the state monitoring high-reliability anti-fuse FPGA receives the external machine cutting command, it switches the current running state of the main control CPU of machine A and the main control CPU of machine B.

In this embodiment, when the dual-machine redundant backup system based on the PCIe high-speed bus interface can respond to an external reset operation, the A/B machine is not switched before and after the reset, and the state of the A/B machine before the reset is maintained.

Optionally, the method further includes: an AC coupling capacitor; the AC coupling capacitor is arranged on the PCIe high-speed bus to prevent the slave device FPGA from pouring voltage back into the main control CPU of machine A and the main control CPU of machine B.

In this embodiment, the A/B master CPU and the slave FPGA should only have a PCIe common circuit, and the PCIe bus needs to be isolated by an AC coupling capacitor to prevent possible backflow when the slave FPGA is started but the master CPU is not powered on voltage; and power supply isolation should be designed between the master control CPU and the slave device FPGA and state monitoring high-reliability anti-fuse FPGA to improve system reliability; A/B master control CPU related circuits need to be completely isolated.

FIG. 2 is a schematic flowchart of switching from a machine A to a machine B in a dual-machine redundant backup system based on a PCIe high-speed bus interface provided by the present invention. As shown in Figure 2, when the main control CPU of machine A is in the working state, the state monitoring high-reliability anti-fuse FPGA sends the power supply enable signal of machine A to the power supply module of machine A as disabled, and the main control CPU of machine A is turned off; Monitoring high-reliability anti-fuse FPGA sends reload command to slave device FPGA; status monitoring high-reliability anti-fuse FPGA switches slave device FPGA startup program B master CPU program memory chip configures slave device FPGA; after the slave device FPGA configuration is completed, pass The status monitoring signal informs the status monitoring high-reliability anti-fuse FPGA to send the power supply enable signal of machine B to enable, and starts the main control CPU of machine B; the main control CPU of machine B initiates a PCIe link request to establish a PCIe bus connection with the slave device FPGA; the slave device The FPGA sends PCIe link success status telemetry to the status monitoring high-reliability antifuse FPGA.

FIG. 3 is a schematic flowchart of switching from machine B to machine A in a dual-machine redundant backup system based on a PCIe high-speed bus interface provided by the present invention. As shown in Figure 3, when the main control CPU of machine B is in the working state, the state monitoring high-reliability anti-fuse FPGA sends the power supply enable signal of machine B to the power supply module of machine B as disabled, and shuts down the main control CPU of machine B; Monitoring high-reliability anti-fuse FPGA sends reload command to slave device FPGA; status monitoring high-reliability anti-fuse FPGA switches slave device FPGA startup program A machine master CPU program memory chip configures slave device FPGA; after the slave device FPGA configuration is completed, pass The status monitoring signal informs the status monitoring high-reliability anti-fuse FPGA to send the power supply enable signal of machine A to enable, and starts the main control CPU of machine A; the main control CPU of machine A initiates a PCIe link request to establish a PCIe bus connection with the slave device FPGA; the slave device The FPGA sends PCIe link success status telemetry to the status monitoring high-reliability antifuse FPGA.

The invention adopts the PCIe bus communication mode, which is one of the most widely used in the field of industrial and commercial data transmission, as the basis, and utilizes its high-speed, general-purpose and expandable characteristics; requirements; aiming at the high temperature and high radiation working environment characteristics in the aerospace field; taking into account the non-repairable characteristics of aerospace products in orbit, realizing dual-machine cold backup switching of PCIe devices, improving system reliability and system life; at the same time, this invention can also be used in the system. On the basis of guaranteed reliability, the scalability and flexibility of use of the system are improved.

Those skilled in the art know that, in addition to implementing the system provided by the present invention and its respective devices in the form of pure computer-readable program codes, the system provided by the present invention and its respective devices can be made by logic gates, Switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers are used to achieve the same function. Therefore, the system and its various devices provided by the present invention can be regarded as a kind of hardware components, and the devices for realizing various functions included in the system can also be regarded as structures in the hardware components; The means for implementing various functions can be regarded as either a software module implementing a method or a structure within a hardware component.

The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above-mentioned specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essential content of the present invention. The embodiments of the present application and features in the embodiments may be arbitrarily combined with each other without conflict.

Claims (5)

1. A dual-computer redundancy backup system based on PCIe high-speed bus interface is characterized in that the system comprises: the system comprises a machine A main control CPU, a machine B main control CPU, a machine A power supply module, a machine B power supply module, a state monitoring high-reliability antifuse FPGA and a slave device FPGA; the machine A power supply module is used for monitoring a power supply enabling signal sent by the high-reliability antifuse FPGA according to the state and supplying power to the machine A main control CPU; the B machine power supply module is used for monitoring a power supply enabling signal sent by the high-reliability antifuse FPGA according to the state and supplying power to the B machine main control CPU; the slave device FPGA is respectively in communication connection with the A main control CPU and the B main control CPU through a PCIe high-speed bus; the main control CPU of the machine A and the main control CPU of the machine B are mutually backup, and the main control CPU of the machine A and the main control CPU of the machine B are not electrified to work at the same time.

2. The dual redundant backup system based on PCIe high speed bus interface of claim 1, wherein the state monitoring high reliability antifuse FPGA is in communication connection with a slave device FPGA start-up A main control CPU program storage chip through a first interface, and the state monitoring high reliability antifuse FPGA is in communication connection with a slave device FPGA start-up B main control CPU program storage chip through a second interface.

3. The dual redundancy backup system based on the PCIe high speed bus interface of claim 1, wherein the state monitoring high reliability antifuse FPGA is connected to an external circuit, for receiving an external reset signal or an external switch instruction;

when the state monitoring high-reliability antifuse FPGA receives an external reset signal, the current running states of the main control CPU A and the main control CPU B are kept;

and when the state monitoring high-reliability antifuse Field Programmable Gate Array (FPGA) receives an external cutter cutting instruction, switching the current running states of the main control CPU of the machine A and the main control CPU of the machine B.

4. The dual-computer redundancy backup system based on the PCIe high-speed bus interface according to any one of claims 1 to 3, wherein when the A-computer main control CPU is in a working state, the state monitoring high-reliability antifuse FPGA sends an A-computer power supply enabling signal to the A-computer power supply module to be disabled, and the A-computer main control CPU is turned off; the state monitoring high-reliability antifuse FPGA sends a heavy-load instruction to the slave device FPGA; the state monitoring high-reliability antifuse FPGA switching slave device FPGA starting program B is used for configuring a slave device FPGA by a master control CPU program storage chip; after the configuration of the slave device FPGA is finished, the state monitoring high-reliability antifuse FPGA is informed through a state monitoring signal to send a B machine power supply enabling signal to be enabled, and a B machine main control CPU is started; the B master control CPU initiates a PCIelink request to establish PCIe bus connection with the FPGA of the slave device; and the slave device FPGA sends PCIe link success state telemetry to the state monitoring high-reliability antifuse FPGA.

5. The dual-computer redundancy backup system based on the PCIe high-speed bus interface according to any one of claims 1 to 3, wherein when the B-computer main control CPU is in a working state, the state monitoring high-reliability antifuse FPGA sends a B-computer power supply enabling signal to the B-computer power supply module to be disabled, and the B-computer main control CPU is turned off; the state monitoring high-reliability antifuse FPGA sends a heavy-load instruction to the slave FPGA; the state monitoring high-reliability antifuse FPGA switching slave device FPGA starting program A is used for configuring a slave device FPGA by a master control CPU program storage chip; after the configuration of the FPGA of the slave equipment is finished, the FPGA of the state monitoring high-reliability antifuse is informed through a state monitoring signal to send an A machine power supply enabling signal to enable, and a main control CPU of the A machine is started; the A master control CPU initiates a PCIe link request to establish PCIe bus connection with the FPGA; and the slave device FPGA sends PCIe link success state telemetry to the state monitoring high-reliability antifuse FPGA.

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