CN108762970A - A kind of highly reliable spaceborne computer program storage device - Google Patents
A kind of highly reliable spaceborne computer program storage device Download PDFInfo
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- CN108762970A CN108762970A CN201810602293.9A CN201810602293A CN108762970A CN 108762970 A CN108762970 A CN 108762970A CN 201810602293 A CN201810602293 A CN 201810602293A CN 108762970 A CN108762970 A CN 108762970A
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- eeprom
- data
- sram
- highly reliable
- fpga
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Abstract
The invention discloses a kind of highly reliable spaceborne computer program storage devices, including CPU, FPGA, PROM, EEPROM, SRAM and watchdog circuit；FPGA is connected CPU and each memory, the control sequential for matching each memory；PROM is for storing monitoring programme and security procedure；EEPROM is used for storage system applications program；When computer is run, during program is from EEPROM remove furniture to SRAM, and it is resident and runs in sram；EEPROM is stored by the way of triplication redundancy, is stored in independent three EEPROM to each part of data；Watchdog circuit is used for the reset to EEPROM and controls.The present invention uses tri- kinds of memories of PROM, EEPROM, SRAM, gives full play to the own characteristic of three kinds of memories, is effectively managed using FPGA technology, realizes the highly reliable program storage of spaceborne computer.
Description
Technical field
The invention belongs to aerospace craft electronic technology more particularly to a kind of highly reliable spaceborne computer program storage to set
It is standby.
Background technology
Spaceborne computer has the characteristics that the highly reliable, long-life, is wanted to the reliability of memory especially program storage
Ask stringent, the error in data of program storage will directly affect the operation of spaceborne computer, or even influence the safety of whole satellite.
The method that the program storage of spaceborne computer mostly uses " PROM+SRAM " at present, reliability is higher, but PROM monolithic memory spaces
It is small, it is big to expand carrying cost height, hardware consumption；Software upgrading in-orbit simultaneously can only be used and be carried out in sram, be turned back on
The software data upgraded afterwards is lost, and in-orbit application is unfavorable for.EEPROM has monolithic capacity big, what rewritable and power down was not lost
Feature, but there are the risk that data are written over, in-orbit application must eliminate rewriting harm.
Invention content
To meet the needs of spaceborne computer large capacity program's memory space, and upgrade energy with highly reliable in-orbit program
Power, the present invention propose a kind of highly reliable spaceborne computer program storage device.
The technical solution adopted in the present invention is：
A kind of highly reliable spaceborne computer program storage device, including CPU, FPGA, PROM, EEPROM, SRAM and guard the gate
Dog circuit；The FPGA is connected the CPU and each memory, the control sequential for matching each memory；The PROM
For storing monitoring programme and security procedure, minimum security system can be safeguarded, it is non-rewritable；The EEPROM is for storing system
System application program, it is rewritable；When computer is run, program resides in described from the EEPROM remove furnitures to the SRAM
It is run in SRAM；Allow in the case where not influencing spaceborne computer operation, upgrading EEPROM stores program；EEPROM storages are adopted
With the mode of triplication redundancy, each part of data are stored in independent three EEPROM；The watchdog circuit is used for
The EEPROM is set to reset state by the variation for detecting the supply voltage of the EEPROM when less than preset threshold value, is prohibited
Only read-write operation.
Optionally, the CPU accesses memory and carries out address decoding selection control by the FPGA, wherein the FPGA
Interior design EEPROM instruction sequences lock sequential coupling logic, and output timing feedback control signal, the CPU is according to the sequential
Feedback control signal adjusts the read-write sequence of itself, realizes the sequential coupling with accessed memory.
Optionally, the EEPROM is in writes lock-out state by default, need to be sent to the EEPROM and write unlock
Instruction sequence, unlock EEPROM, which writes lock-out state, could carry out write operation.
Optionally, preset EEPROM inside the FPGA is set and writes permission state, it, should for opening EEPROM write signals
Mode bit is controlled by surface instruction, and when writing permission state in EEPROM, sending default write command sequence could effectively reach
The EEPROM realizes write operation.
Optionally, during reading program, the PROM reads three parts of EEPROM data and is compared, three parts of data one
It is run in remove furniture to the SRAM when cause；When there are portion EEPROM data different from other two parts of EEPROM data, then sentence
Two parts of identical EEPROM data of breaking are correct, by correct data remove furniture to the SRAM, while judging another EEPROM number
According to mistake, the address of this part of EEPROM error in data is recorded, processing of selecting a good opportunity；When being all different there are three parts of EEPROM data,
It will stop remove furniture, misregistration runs the minimum system program in the PROM.
Compared with prior art, the beneficial effects of the invention are as follows：
The present invention has merged three kinds of different types of memory PROM, EEPROM and SRAM, is distinguished according to reliability characteristic
It is stored for different programs, and for the characteristic of EEPROM using reliabilities such as watchdog technique, instruction sequence unlocking technologies
Technology is realized the functions such as the anti-power on and off of watchdog circuit is rewritten, anti-software error is rewritten and anti-system mistake is rewritten, is solved
The application demands such as spaceborne computer is highly reliable, the upgrading of large capacity, in-orbit program, providing height for spaceborne computer program storage can
The solution leaned on.
Certainly, it implements any of the products of the present invention and does not necessarily require achieving all the advantages described above at the same time.
Description of the drawings
Fig. 1 is a kind of composition frame chart of highly reliable spaceborne computer program storage device of one embodiment of the invention；
Fig. 2 is a kind of program operational process of highly reliable spaceborne computer program storage device of one embodiment of the invention
Figure；
Fig. 3 is that a kind of EEPROM of highly reliable spaceborne computer program storage device of one embodiment of the invention writes flow
Figure.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to each reality of the present invention
The mode of applying is explained in detail.
Fig. 1 be spaceborne computer program storage device of the present invention composition frame chart, including CPU, FPGA, PROM, EEPROM,
SRAM and watchdog circuit；FPGA is connected CPU and each memory, the control sequential for matching each memory；PROM is used
In storage monitoring programme and security procedure, minimum security system can be safeguarded；EEPROM is used for storage system applications program；It calculates
When machine is run, during program is from EEPROM remove furniture to SRAM, and it is resident and runs in sram；EEPROM storages are using triplication redundancy
Mode is stored in independent three EEPROM each part of data；CPU accesses memory and carries out address decoding choosing by FPGA
Control is selected, wherein FPGA interior designs EEPROM instruction sequences lock sequential coupling logic, output timing feedback control signal, CPU
Signal is controlled according to sequence feedback and adjusts the read-write sequence of itself, realizes the sequential coupling with accessed memory；House dog electricity
EEPROM is set to reset state, forbidden by the variation for the supply voltage that road is used to detect EEPROM when less than preset threshold value
Read-write operation.
Using tri- kinds of memories of PROM, EEPROM and SRAM, the own characteristic of three kinds of memories is given full play to, using FPGA
Technology is effectively managed, and realizes the highly reliable program storage of spaceborne computer.
Tri- kinds of memory pools of PROM, EEPROM, SRAM use, and PROM has reliability height, single burning non-rewritable
But the small characteristic of capacity stores monitoring programme and security procedure using PROM, is used for the minimum safe system of maintenance system application,
In the case where EEPROM programs are lost, running minimized for system is still ensured that；EEPROM has capacity big data power down portion
Lose but exist power on, power failure data batch rewrites the characteristic of risk, using EEPROM storage system applications programs, and can be into
The in-orbit program upgrading of row；The characteristic that SRAM has reading speed fast but data power down is lost, program is from EEPROM remove furniture to SRAM
In, and be resident and run in sram, it operates in the case of not influencing spaceborne computer operation, upgrading EEPROM stores program.
EEPROM is in writes lock-out state by default, need to be sent to EEPROM and write unlock instruction sequence, unlocked
EEPROM, which writes lock-out state, could carry out write operation.In the case where EEPROM is in and writes lock-out state, single write operation cannot achieve
Function is write, software or hardware run-time error is prevented and the write operation of mistake occurs, the program in EEPROM is caused to be written over；Using
FPGA technology is interacted with CPU, it is ensured that the output timing of writing of software meets specific timing requirements.
When system mistake, software may be caused to send EEPROM write command sequences, realize the rewriting to eeprom content,
Permission state is write using preset EEPROM is arranged inside FPGA, for opening EEPROM write signals, the mode bit is by ground
Instruction control, when writing permission state in EEPROM, EEPROM could effectively be reached by sending default write command sequence, and realization is write
Operation.It is mainly the state setting technology that FPGA is realized that EEPROM, which writes the setting of permission state, and FPGA is parsed in up-on command realization
The state of portion's quantity of state changes, and when the up-on command of transmission is that EEPROM writes permission, it is " 1 " that setting EEPROM, which writes permission state,
Allow to EEPROM write operations；When the up-on command of transmission is that EEPROM is forbidden to write, setting EEPROM writes permission state and is
" 0 " forbids to EEPROM write operations.
Fig. 2 is the flow chart of program operation, and spaceborne computer power-up routine starts from PROM, to spaceborne computer state
Be configured, after accomplishing the setting up by system program from EEPROM remove furniture to SRAM in.During remove furniture, respectively from EEPROM
A, EEPROM B, EEPROM C read data and carry out two from three comparison, when three parts of storage data are consistent, write data into
In SRAM, when a copy of it data are different from other storage data, identical data are written in SRAM, and record different numbers
According to address and data, until completing the remove furniture work of all EEPROM valid data；When three parts of data are all different, will remember
Three parts of different data and address are recorded, and stops current remove furniture work, is transferred to PROM operation minimum system programs.
Fig. 3 is that EEPROM writes flow chart, and when starting to carry out write operation to EEPROM, the data that will be written first are stored in
Into SRAM or other cachings, sending EEPROM and writing allows to instruct, and setting EEPROM is to write permission state；Software sends EEPROM
Unlock instruction sequence is write, unlock EEPROM writes lock-out state.The data in SRAM or other cachings are read, are sequentially written in
In EEPROM A, EEPROM B, EEPROM C, until data write-in is completed.After completing data write-in, software sends EEPROM and writes
Locking instruction sequence, sets EEPROM to write lock-out state；It sends EEPROM and writes and forbid instructing, setting EEPROM, which writes, to be forbidden.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims
Subject to.
Claims (5)
1. a kind of highly reliable spaceborne computer program storage device, which is characterized in that including CPU, FPGA, PROM, EEPROM,
SRAM and watchdog circuit；The FPGA is connected the CPU and each memory, when control for matching each memory
Sequence；The PROM can safeguard minimum security system for storing monitoring programme and security procedure；The EEPROM is for storing
System application；When computer is run, program is resided in from the EEPROM remove furnitures to the SRAM in the SRAM
Operation；EEPROM is stored by the way of triplication redundancy, is stored in independent three EEPROM to each part of data；Institute
The variation for stating supply voltage of the watchdog circuit for detecting the EEPROM will be described when less than preset threshold value
EEPROM is set to reset state, forbids read-write operation.
2. a kind of highly reliable spaceborne computer program storage device according to claim 1, which is characterized in that the CPU
It accesses memory and address decoding selection control is carried out by the FPGA, wherein the FPGA interior designs EEPROM instruction sequences
Sequential coupling logic, output timing feedback control signal are locked, the CPU controls signal according to the sequence feedback and adjusts itself
Read-write sequence realizes the sequential coupling with accessed memory.
3. a kind of highly reliable spaceborne computer program storage device according to claim 1, which is characterized in that described
EEPROM is in writes lock-out state by default, need to be sent to the EEPROM and write unlock instruction sequence, unlock EEPROM
Write operation could be carried out by writing lock-out state.
4. a kind of highly reliable spaceborne computer program storage device according to claim 1, which is characterized in that the FPGA
Inside is arranged preset EEPROM and writes permission state, and for opening EEPROM write signals, which is controlled by surface instruction, when
When writing permission state in EEPROM, the EEPROM could effectively be reached by sending default write command sequence, realize write operation.
5. a kind of highly reliable spaceborne computer program storage device according to claim 1, which is characterized in that reading journey
In program process, the PROM reads three parts of EEPROM data and is compared, and is transported in remove furniture to the SRAM when three parts of data are consistent
Row；When there are portion EEPROM data different from other two parts of EEPROM data, then two parts of identical EEPROM data are judged
Correctly, by correct data remove furniture to the SRAM, while judging another EEPROM error in data, record this part of EEPROM number
According to the address of mistake, processing of selecting a good opportunity；When being all different there are three parts of EEPROM data, remove furniture, misregistration, operation will be stopped
Minimum system program in the PROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810602293.9A CN108762970A (en) | 2018-06-12 | 2018-06-12 | A kind of highly reliable spaceborne computer program storage device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810602293.9A CN108762970A (en) | 2018-06-12 | 2018-06-12 | A kind of highly reliable spaceborne computer program storage device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109933340A (en) * | 2019-03-04 | 2019-06-25 | 北京空间飞行器总体设计部 | A kind of spacecraft EEPROM in-orbit write-in and self checking method based on page mode |
| CN111404750A (en) * | 2020-03-20 | 2020-07-10 | 上海航天测控通信研究所 | Centralized parameter management device and method for advanced on-orbit system |
| CN111400109A (en) * | 2020-04-07 | 2020-07-10 | 上海航天计算机技术研究所 | Dual-computer redundancy backup system based on PCIe high-speed bus interface |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6968487B1 (en) * | 2000-09-02 | 2005-11-22 | Actel Corporation | User available body scan chain |
| CN1306408C (en) * | 2003-12-24 | 2007-03-21 | 上海华虹集成电路有限责任公司 | Method capable of smartly implementing EEPROM simulation function in chip |
| CN103678175A (en) * | 2013-12-05 | 2014-03-26 | 长城信息产业股份有限公司 | Address concealing method and embedded equipment based on address concealing technology |
| CN106649173A (en) * | 2016-10-10 | 2017-05-10 | 上海航天控制技术研究所 | High-reliability in-orbit self-correction system and method for on-board computer on the basis of 1553B bus |
| CN107515800A (en) * | 2017-07-17 | 2017-12-26 | 上海卫星工程研究所 | On-board software dependability design system and method based on software redundancy |
-
2018
- 2018-06-12 CN CN201810602293.9A patent/CN108762970A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6968487B1 (en) * | 2000-09-02 | 2005-11-22 | Actel Corporation | User available body scan chain |
| CN1306408C (en) * | 2003-12-24 | 2007-03-21 | 上海华虹集成电路有限责任公司 | Method capable of smartly implementing EEPROM simulation function in chip |
| CN103678175A (en) * | 2013-12-05 | 2014-03-26 | 长城信息产业股份有限公司 | Address concealing method and embedded equipment based on address concealing technology |
| CN106649173A (en) * | 2016-10-10 | 2017-05-10 | 上海航天控制技术研究所 | High-reliability in-orbit self-correction system and method for on-board computer on the basis of 1553B bus |
| CN107515800A (en) * | 2017-07-17 | 2017-12-26 | 上海卫星工程研究所 | On-board software dependability design system and method based on software redundancy |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109933340A (en) * | 2019-03-04 | 2019-06-25 | 北京空间飞行器总体设计部 | A kind of spacecraft EEPROM in-orbit write-in and self checking method based on page mode |
| CN111404750A (en) * | 2020-03-20 | 2020-07-10 | 上海航天测控通信研究所 | Centralized parameter management device and method for advanced on-orbit system |
| CN111404750B (en) * | 2020-03-20 | 2022-11-01 | 上海航天测控通信研究所 | Centralized parameter management device and method for advanced on-orbit system |
| CN111400109A (en) * | 2020-04-07 | 2020-07-10 | 上海航天计算机技术研究所 | Dual-computer redundancy backup system based on PCIe high-speed bus interface |
| CN111400109B (en) * | 2020-04-07 | 2023-08-01 | 上海航天计算机技术研究所 | Dual-machine redundancy backup system based on PCIe high-speed bus interface |
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Application publication date: 20181106 |