CN102841634A - Server mainboard - Google Patents

Abstract

The invention provides a server mainboard. The server mainboard comprises a South Bridge chip and a BMC (baseboard management controller) chip, wherein the South Bridge chip is coupled with the BMC chip by virtue of an LPC (low in count) bus, the mainboard is provided with a plurality of BIOSs and a plurality of BMCFWs, the server mainboard also comprises a pair of programmers, a pair of reverse tubes and a pair of gating devices, and the South Bridge chip and the BMC chip respectively send a chip selection signal to the gating devices, so as to select one BIOS or one BMCFW. According to the server mainboard, a level value output by each programmer is changed by programming to control on and off of each gating device, thus switching between two BIOSs or two BMCs is realized.

Description

Server master board

[technical field]

The present invention relates to a kind of server master board.

[background technology]

Generally have only a BMC FW and a BIOS on the present server master board; In case the user goes wrong or sudden power in upgrading BMC FW or BIOS process; Possibly cause the BMC FW or the BIOS of system to damage, thereby system can not normally start, and at this moment must take off BMC FW or BIOS chip; Carry out burning with CD writer, operation is very inconvenient.

[summary of the invention]

For addressing the above problem; The invention provides a kind of server master board, scheme is following: a kind of server master board comprises a South Bridge chip and a BMC chip; This South Bridge chip couples through lpc bus and this BMC chip; It is characterized in that this mainboard includes a plurality of BIOS and a plurality of BMC FW, this server master board also includes:

First programmable device is in order to programming output one level;

First reversing tube is coupled to this first programmable device, in order to export reverse level;

First gate is respectively coupled to above-mentioned first programmable device and above-mentioned first reversing tube;

Second programmable device is in order to programming output one level;

Second reversing tube is coupled to this second programmable device, in order to export reverse level;

Second gate is respectively coupled to above-mentioned second programmable device and above-mentioned second reversing tube,

Wherein, this first and second gate is respectively coupled to a plurality of BIOS and a plurality of BMC FW, and said South Bridge chip and said BMC chip select signal to first gate and second gate transmission a slice respectively, to select a BIOS or a BMC FW.

Preferably, said gate is the low level conducting, and high level ends.

Preferably, said programmable device is PCA9556PWPW.

The present invention changes the level value of programmable device output through programming, the conducting of control gate or end, thus when wherein BIOS or BMC FW damaged, system just can be from the BIOS or the BMC FW startup of backup.

For the object of the invention, structural attitude and function thereof are had further understanding, conjunction with figs. specifies as follows now:

[description of drawings]

Fig. 1 illustrates the structural representation into server master board preferred embodiment of the present invention.

[embodiment]

See also Fig. 1, Fig. 1 illustrates the structural representation into server master board preferred embodiment of the present invention.This server master board comprises a South Bridge chip 14 and a BMC chip 24; This South Bridge chip 14 couples through lpc bus and this BMC chip 24; This mainboard includes a plurality of BIOS and a plurality of BMC FW, and this server master board also includes a pair of programmable device, i.e. first programmable device 11 and second programmable device 21; In order to programming output one level, this programmable device can be the PCA9556PWPW chip respectively; A pair of reversing tube, i.e. first reversing tube 12 and second reversing tube 22, respectively in order to export reverse level, wherein this first reversing tube 12 is coupled to these first programmable device, 11, the second reversing tubes 22 and is coupled to this second programmable device 21; A pair of gate, i.e. first gate 13, its input end are coupled to above-mentioned first programmable device 11 and above-mentioned first reversing tube 12; Second gate 23, its input end are coupled to above-mentioned second programmable device 21 and above-mentioned second reversing tube 22, and this gate can be the low level conducting, and high level ends.

Wherein, These first gate, 13 output terminals and second gate, 23 output terminals are respectively coupled to above-mentioned a plurality of BIOS and a plurality of BMC FW; Said South Bridge chip 14 selects signal to first gate 13 and second gate, 23 transmission a slices respectively with said BMC chip 24, to select a BIOS or a BMC FW.

In one embodiment, to programmable device PCA9556PW1 programming, make its output level be defaulted as low level; This low level is passed to gate; Simultaneously this level through the reverse back output of reversing tube NMOS one reverse level be high level to gate, South Bridge chip 14 and BMC chip 24 select signal to gate transmission a slice respectively through bus, this conduction device is the low level conducting; Thereby chip selection signal is chosen corresponding BIOS or BMC FW chip through conduction device.

Usually, after the normal startup of system, BIOS chip and BMC FW have a process of confirming each other; Through lpc bus communication, inform that the other side normally starts, in the above-described embodiments; Two BIOS chips are arranged, i.e. a BIOS chip 152 and 151, two BMC FW of the 2nd BIOS chip on the mainboard; I.e. a BMC FW252 and the 2nd BMC FW251, when a BIOS chip 152 occurs unusually, system can not start from a BIOS chip 152; At this moment, BMC does not receive BIOS delivered confirmation information, and then BMC can be known through lpc bus; Send a reset signal to mainboard, through the control system bus the first programmable device PCA9556PW1 is programmed simultaneously, make on its pin and export high level; This high level converts low level into after being delivered to phase-reversing tube NMOS, and this high level and low level are delivered to the input end of gate respectively, and gate is the low level conducting here; Chip selection signal from South Bridge chip 14 is just chosen the 2nd BIOS chip 151 through gate, and system starts from the 2nd BIOS chip 151.

BMC detects after the normal startup of system, can signal to make system switch to the BIOS chip of damage again, has warning message this moment and notifies user BIOS chip to damage, and the user just can repair the chip of damage under operating system.

In above-mentioned second embodiment, unusual if a BMC FW 252 occurs, system can not start from a BMC FW; At this moment; BIOS does not receive BMC delivered confirmation information, and then South Bridge chip 14 can be known through lpc bus, and through the control system bus second programmable device, 21 PCA9556PW1 is programmed; Make its output high level; This high level converts low level into after being delivered to second phase-reversing tube, 22 NMOS, and this high level and low level are delivered to the input end of second gate 23 respectively, and second gate 23 is low level conductings here; Chip selection signal from South Bridge chip 14 is just chosen the 2nd BMC FW 251 through second gate 23, and system is from the 2nd BMC FW 251 chip enables.

After the normal startup of system, BIOS can signal again and make system switch to the BMC FW of damage, has warning message this moment and notifies user BMC FW to damage, and the user just can repair the chip of damage through the BMC far-end.

The present invention changes the level value of programmable device output through programming, the conducting of control gate or end, thus when wherein BIOS or BMC FW damaged, system just can be from the BIOS or the BMC FW startup of backup.

Claims (3)

1. a server master board comprises a South Bridge chip and a BMC chip, and this South Bridge chip couples through lpc bus and this BMC chip, it is characterized in that, this mainboard includes a plurality of BIOS and a plurality of BMC FW, and this server master board also includes:

First programmable device is in order to programming output one level;

First reversing tube is coupled to this first programmable device, in order to export reverse level;

First gate is respectively coupled to above-mentioned first programmable device and above-mentioned first reversing tube;

Second programmable device is in order to programming output one level;

Second reversing tube is coupled to this second programmable device, in order to export reverse level;

Second gate is respectively coupled to above-mentioned second programmable device and above-mentioned second reversing tube,

Wherein, this first and second gate is respectively coupled to a plurality of BIOS and a plurality of BMC FW, and said South Bridge chip and said BMC chip select signal to first gate and second gate transmission a slice respectively, to select a BIOS or a BMC FW.

2. server master board as claimed in claim 1 is characterized in that said gate is the low level conducting, and high level ends.

3. server master board as claimed in claim 1 is characterized in that, said programmable device is PCA9556PWPW.

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