CN102768561A - Design method for twinbridge piece mainboard redundancy - Google Patents
Design method for twinbridge piece mainboard redundancy Download PDFInfo
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- CN102768561A CN102768561A CN2012101725292A CN201210172529A CN102768561A CN 102768561 A CN102768561 A CN 102768561A CN 2012101725292 A CN2012101725292 A CN 2012101725292A CN 201210172529 A CN201210172529 A CN 201210172529A CN 102768561 A CN102768561 A CN 102768561A
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Abstract
The invention relates to a design method for twinbridge piece mainboard redundancy. A twinbridge piece mainboard adopted in the method comprises a CPU (central processing unit)-south and north bridge system 1, a CPU-south and north bridge system 2 and a monitoring circuit, wherein the CPU-south and north bridge system 1 and the CPU-south and north bridge system 2 are symmetrically arranged at two sides of the monitoring circuit. The method comprises the following steps that an initial state is determined, the CPU-south and north bridge system 1 is electrified, in addition, pulse signals and signal codes are sent to the monitoring circuit; whether the signals of a serial port and a lead wire of the CPU-south and north bridge system 1 are normal or not is judged; the signal codes are sent to the monitoring circuit; whether the signals of a lead wire interface, a serial port and an Internet access are normal or not is judged; and the states of the CPU-south and north bridge system 1 and the CPU-south and north bridge system 2 are transmitted to remote control terminal equipment. The design method for twinbridge piece mainboard redundancy provided by the invention has the advantages that the reliable and stable operation of a loongson CUP is ensured in the aspect of redundancy design, and the normal operation of the reliable data and business under the accident suffering condition is ensured.
Description
Technical field
The present invention relates to a kind of method for designing, specifically relate to the redundant method for designing of a kind of doube bridge sheet mainboard.
Background technology
No. 3 serial CPU of Godson comprise 4 core 3A, 8 core 3B, the CPU of 8 cores or 16 core 3C, and other serial CPU of subsequent development.Godson 3A CPU is volume production, and other two kinds of CPU also are in development.
No. 3 CPU of Godson are CPU of a general multinuclear, adopt the MIPS framework, can realize the function of Intel and AMD X86 framework CPU fully, although also more backward a little than X86CPU at aspect of performance, can replace X86CPU fully in most fields.
Although Godson 3A and 3B CPU emerge, never solve the key issue of " usefulness ", promptly never find the north and south bridge chipsets and the peripherals of and ability operate as normal supporting with Godson CPU.For solving the practical problems of Godson CPU, once inquired into " the Godson 3CPU+SIS chipsets of company ", the possibility of " the Godson 3CPU+NVIDIA chipsets of company ", and researched and developed the mainboard sample, but final not success.
Godson 3 serial CPU are limited to technical protection, can't share the X86CPU successful experience, therefore exist bug unavoidable.
The difficult situation of Chinese high-performance server field centreless has been broken in the appearance of No. 3 serial CPU of Godson, China IT industry band on a new height.But the problem that next faces a sternness is exactly the industrialization problem of CPU, if solve the problem of bad industrialization, it can not practicality be the CPU of conceptual that Godson CPU is still one, can only stop under lab.Because the time that No. 3 serial CPU of Godson emerge is short, various supporting application schemes have to be designed and create.
The operation that how to guarantee Godson CPU platform reliable and stable is the problem of pendulum on Godson CPU road for development.The X86 platform has the mechanism of various maturation to guarantee the operation of X86 platform stable, and Godson CPU platform can be described as the stage at the early-stage at present.
Summary of the invention
Deficiency to prior art; The present invention provides a kind of doube bridge sheet mainboard redundant method for designing; The method for designing that doube bridge sheet mainboard provided by the invention is redundant; Guarantee the reliable and stable operation of Godson CPU from the Redundancy Design aspect, the assurance authentic data still can normally be moved under the situation of having an accident with professional.The present invention equally also is applicable to the X86CPU platform.
The objective of the invention is to adopt following technical proposals to realize:
The method for designing that a kind of doube bridge sheet mainboard is redundant, its improvements are that the doube bridge sheet mainboard that said method is used comprises CPU-north and south bridge system 1, CPU-north and south bridge system 2 and supervisory circuit; Said CPU-north and south bridge system 1 and CPU-north and south bridge system 2 are symmetricly set on the both sides of said supervisory circuit;
Said method comprises the steps:
A, confirm original state;
B, the said CPU-north and south bridge system 1 concurrent pulse signal of energising and signal code are given said supervisory circuit;
Whether the signal of C, the lead-in wire of judging said CPU-north and south bridge system 1 and serial ports is normal;
D, transmission signal code are given said supervisory circuit;
Whether the signal of E, judgement lead-in wire interface, serial ports and network interface is normal;
F, give remote control terminal equipment with the state transfer of said CPU-north and south bridge system 1 and CPU-north and south bridge system 2.
A kind of optimized technical scheme provided by the invention is: the original state in the said steps A is that said CPU-north and south bridge system 1 is in off position with CPU-north and south bridge system 2, prepares to give said CPU-north and south bridge system 1 energising.
Second optimized technical scheme provided by the invention is: among the said step B, said supervisory circuit is controlled power-on and power-off control, the reset circuit 1 in the said CPU-north and south bridge system 1, gives said CPU-north and south bridge system 1 energising;
The CPU1 of said CPU-north and south bridge system 1 begins the BIOS operation phase, and the lead-in wire GPIO1 that controls CPU1 in the said BIOS operation phase sends out pulse signal to said supervisory circuit; The serial ports of controlling simultaneously in the CPU-north and south bridge system 11 sends signal code for said supervisory circuit.
The 3rd optimized technical scheme provided by the invention is: among the said step C, whether the signal that said supervisory circuit detects said lead-in wire GPIO1 and serial ports 1 is normal;
If detect lead-in wire GPIO1 and serial ports 1 arbitrary road abnormal signal; Then by said supervisory circuit control said power-on and power-off control, reset circuit 1 shuts down down; And the power-on and power-off control in the control CPU-north and south bridge system 2, reset circuit 2 gives CPU-north and south bridge system 2 energisings, makes said CPU-north and south bridge system 2 carry out work.
A kind of more preferably technical scheme provided by the invention is: when said CPU-north and south bridge system 2 carries out work, and lead-in wire GPIO4 and serial ports 3 in the said CPU-of the said monitor circuit monitors north and south bridge system 2;
If lead-in wire GPIO4 and serial ports 3 arbitrary road signals occur unusual; Carry out step F; Give doube bridge sheet mainboard medium-long range control terminal with the state transfer of the operation irregularity of said CPU-north and south bridge system 1 and CPU-north and south bridge system 2, the said BIOS operation phase starts completion.
The 4th optimized technical scheme provided by the invention is: among the said step D, after the BIOS operation phase started completion, said CPU-north and south bridge system 1 got into the operating system OS operation phase; Said CPU1 enable to go between GPIO2 and GPIO3, network interface 1 and serial ports 2 sends signal code for said supervisory circuit.
The 5th optimized technical scheme provided by the invention is: in the said step e, judge whether the signal of lead-in wire GPIO1, GPIO2 and GPIO3, network interface 1, serial ports 1 and serial ports 2 is normal;
If detect lead-in wire GPIO1, GPIO2 and GPIO3, network interface 1, serial ports 1 and serial ports 2 arbitrary road abnormal signals; Then by said supervisory circuit control said power-on and power-off control, reset circuit 1 shuts down down; And the power-on and power-off control in the control CPU-north and south bridge system 2, reset circuit 2 gives CPU-north and south bridge system 2 energisings, makes said CPU-north and south bridge system 2 carry out work.
Provided by the invention another more preferably technical scheme be: when said CPU-north and south bridge system 2 carries out work, lead-in wire GPIO4 and serial ports 3 in the said CPU-of the said monitor circuit monitors north and south bridge system 2;
If lead-in wire GPIO4 and serial ports 3 arbitrary road signals occur unusual; Carry out step F; Give doube bridge sheet mainboard medium-long range control terminal with the state transfer of the operation irregularity of said CPU-north and south bridge system 1 and CPU-north and south bridge system 2, the said operating system OS operation phase starts completion.
The 6th optimized technical scheme provided by the invention is: said CPU-north and south bridge system 1 comprises and connects Godson CPU1, north bridge 1 and south bridge 1 successively; Said north bridge 1 is connected with south bridge 1 through A-Link bus;
Said CPU-north and south bridge system 2 comprises and connects Godson CPU2, north bridge 2 and south bridge 2 successively; Said north bridge 2 is connected with south bridge 2 through A-Link bus;
Said Godson CPU1 and Godson CPU2 include data collecting card and memory bank.
The 7th optimized technical scheme provided by the invention is: said doube bridge mainboard comprises non-volatile memory medium and remote control terminal equipment; Said non-volatile memory medium is connected with south bridge 2 with south bridge 1 respectively; Said remote control terminal equipment is connected with said supervisory circuit.
A kind of more preferably technical scheme provided by the invention is: said remote control terminal equipment through 100,000,000 or gigabit Ethernet be connected with supervisory circuit.
Provided by the invention another more preferably technical scheme be: said CPU-north and south bridge system 1 comprises serial ports 1, serial ports 2 and network interface 1; Said serial ports 1 is connected with said CPU1; Said network interface 1 is connected with said north bridge 1 through the PCIE bus; Said serial ports 2 is connected with said south bridge 1;
Said CPU-north and south bridge system 2 comprises serial ports 3, serial ports 4 and network interface 2; Said serial ports 3 is connected with said CPU2; Said network interface 2 be connected through the said north bridge 2 of PCIE bus; Said serial ports 4 is connected with said south bridge 2.
Provided by the invention also one more preferably technical scheme be: said north bridge 1 includes AMD chipset SR5690, SR5670, SR5650 with north bridge 2; Comprise AMD chipset SP5100, SP5100R, SP5100RS with said north bridge 1 and north bridge 2 corresponding south bridges 1 with south bridge 2;
Said north bridge 1 also comprises AMD chipset RS780, RS780C, RS780D, RS780E, RS780G, RS780M, RS780MC, RX781, RS785G and RD790 with north bridge 2; The south bridge 1 corresponding with it comprises AMD chipset SB700, SB710, SB750 and SB600 with south bridge 2.
Provided by the invention again one more preferably technical scheme be: said serial ports 1, serial ports 2, network interface 1, serial ports 3, serial ports 4 are connected with said supervisory circuit respectively with network interface 2.
Provided by the invention also one more preferably technical scheme be: said CPU-north and south bridge system 1 comprises power-on and power-off control, reset circuit 1; Said CPU-north and south bridge system 2 comprises power-on and power-off control, reset circuit 2; Said power-on and power-off control, reset circuit 1 and power-on and power-off control, reset circuit 2 are connected with said supervisory circuit respectively.
Another more preferably technical scheme provided by the invention is: said CPU1 is connected with north bridge 1 through HT1bus; Said CPU2 is connected with north bridge 2 through HT1bus.
Another more preferably technical scheme provided by the invention is: said CPU1 is connected with said CPU2 through HT0bus; Said CPU1 and CPU2 are the CPU of No. 3 series of Godson, comprise Godson 3A, 3B and 3C.
Another more preferably technical scheme provided by the invention is: draw a line GPIO1 at least from said CPU1 and be connected to said supervisory circuit; At least draw a line GPIO2 from said north bridge 1 and be connected to said supervisory circuit; At least draw a line GPIO3 from the said south bridge 1 and be connected to said supervisory circuit;
At least draw a line GPIO4 from said CPU2 and be connected to said supervisory circuit; At least draw a line GPIO5 from said north bridge 2 and be connected to said supervisory circuit; At least draw a line GPIO6 from the said south bridge 2 and be connected to said supervisory circuit.
Another more preferably technical scheme provided by the invention is: said supervisory circuit adopts the baseboard management controller chip to build or adopt singlechip chip to build; Said supervisory circuit adopts the accessory power supply power supply; The default conditions of said supervisory circuit are power-up states.
Another more preferably technical scheme provided by the invention is: said remote monitoring terminal unit comprises remote console.
With the prior art ratio, the beneficial effect that the present invention reaches is:
1, the redundant method for designing of doube bridge sheet mainboard provided by the invention; Redundant each other, the backup of 2 covers " CPU-north and south bridge system " that relate to; When a cover " CPU-north and south bridge system " breaks down or occurs unusually, supervisory circuit is turned off this cover system immediately, and opens another set of " CPU-north and south bridge system " immediately; Guarantee the key business operation that in the shortest time, is restored, strengthened the robustness of mainboard operation.
2, go between and serial ports through the GPIO that draws CPU, and (Basic Input Output System BIOS) writes relevant function in the program, realized the monitoring in BIOS stage in Basic Input or Output System (BIOS); Conventional system can only be implemented in operating system (Operating System, OS) stage monitoring.
3, realized topmost three chip in the support doube bridge sheet mainboard, promptly CPU, north bridge, south bridge can both be monitored.
4, two approach designs are all adopted in the monitoring of every money chip, and guaranteed the accuracy of monitor message: for example CPU1 adopts GPIO1 and 1 two kinds of approach of serial ports.
5, " non-volatile memory mediums such as hard disk or flash " design of sharing is that the transmission of the business information between 2 covers " CPU-north and south bridge system 1 " and " CPU-north and south bridge system 2 " provides information assurance the most accurately.
6, ' remote control terminal equipment ' can obtain the ruuning situation of 2 covers " CPU-north and south bridge system " constantly.
7, the redundant method for designing of doube bridge sheet mainboard provided by the invention realizes simply accomplishing complicated workflow, guarantees the operation of Godson CPU platform reliable and stable.
Description of drawings
Fig. 1 is a doube bridge sheet mainboard schematic diagram provided by the invention.
Embodiment
Do further to specify below in conjunction with the accompanying drawing specific embodiments of the invention.
As shown in Figure 1, Fig. 1 is a doube bridge sheet mainboard schematic diagram provided by the invention; Doube bridge sheet mainboard comprises CPU-north and south bridge system 1, CPU-north and south bridge system 2 and supervisory circuit; CPU-north and south bridge system 1 and CPU-north and south bridge system 2 are symmetricly set on the both sides of supervisory circuit;
CPU-north and south bridge system 1 comprises and connects Godson CPU1, north bridge 1 and south bridge 1 successively; North bridge 1 is connected with south bridge 1 through A-Link bus; CPU-north and south bridge system 2 comprises and connects Godson CPU2, north bridge 2 and south bridge 2 successively; Said north bridge 2 is connected with south bridge 2 through A-Link bus; A-Link bus is that AMD improves the bus that develops the connection north and south bridge that forms to PCIE bus.The north and south bridge here is meant a series of north and south bridge of AMD's research and development.North bridge comprises AMD chipset RS780, RS780C, RS780D, RS780E, RS780G, RS780M, RS780MC, RX781, RS785G, RD790; AMD chipset SR5690, SR5670, SR5650.South bridge comprises AMD chipset SB700, SB710, SB750, SB600; AMD chipset SP5100, SP5100R, SP5100RS.
Godson CPU1 and Godson CPU2 include data collecting card and memory bank.
Godson CPU1 is connected with north bridge 1 through HT1bus; Godson CPU2 is connected with north bridge 2 through HT1bus.Godson CPU1 is connected with Godson CPU2 through HT0bus.
The bus of HT (Hyper Transport) bus:AMD CPU, the perhaps bus of Godson CPU.Above-mentioned CPU is meant the CPU that has HT bus of AMD, and perhaps the Godson series CPU of Chinese Academy of Sciences's research and development comprises Godson 3A, 3B, 3C.
At least draw a line GPIO1 from Godson CPU1 and be connected to supervisory circuit; At least draw a line GPIO2 from north bridge 1 and be connected to supervisory circuit; At least draw a line GPIO3 from the south bridge 1 and be connected to supervisory circuit;
At least draw a line GPIO4 from Godson CPU2 and be connected to supervisory circuit; At least draw a line GPIO5 from north bridge 2 and be connected to supervisory circuit; At least draw a line GPIO6 from the south bridge 2 and be connected to supervisory circuit.GPIO (General Purpose Input Output) refers to general I/O.
2 cover CPU-north and south bridge systems are redundant each other, backup each other, and its inner connecting way is identical with outside connected mode.
Doube bridge sheet mainboard also comprises non-volatile memory medium and remote control terminal equipment; Non-volatile memory medium is connected with south bridge 2 with south bridge 1 respectively; Remote control terminal equipment comprises remote console, supervisory circuit through 100,000,000 or the gigabit Ethernet network link to each other with long-range terminal, can be constantly to remote console transmission monitor message.
CPU-north and south bridge system 1 comprises serial ports 1, serial ports 2 and network interface 1; Serial ports 1 is connected with Godson CPU1; Network interface 1 is connected with north bridge 1 through the PCIE bus; Serial ports 2 is connected with south bridge 1;
CPU-north and south bridge system 2 comprises serial ports 3, serial ports 4 and network interface 2; Serial ports 3 is connected with Godson CPU2; Network interface 2 be connected through PCIE bus north bridge 2; Serial ports 4 is connected with south bridge 2.
Serial ports 1, serial ports 2, network interface 1, serial ports 3, serial ports 4 and network interface 2 are connected with supervisory circuit respectively.
CPU-north and south bridge system 1 also comprises power-on and power-off control, reset circuit 1; Said CPU-north and south bridge system 2 also comprises power-on and power-off control, reset circuit 2; Power-on and power-off control, reset circuit 1 and power-on and power-off control, reset circuit 2 are connected with supervisory circuit respectively.Power-on and power-off control, reset circuit are controlled by supervisory circuit.
Supervisory circuit can adopt BMC (Baseboard Management Controller, baseboard management controller) chip (the for example AST2300 of Aspeed company, perhaps AST2050) to build, and also can adopt simple single-chip microcomputer (MCU) chip to build.This circuit need be used standby (accessory power supply) power supply, and under the situation that promptly 2 cover CPU-north and south bridge systems are not also started shooting, supervisory circuit must have.Supervisory circuit through 100,000,000 or the gigabit Ethernet network link to each other with long-range terminal, can be constantly to remote console transmission monitor message.
Non-volatile memory medium such as hard disk or flash is that 2 cover CPU-north and south bridge systems are shared.
The redundant method for designing of provided by the invention-doube bridge sheet mainboard comprises the steps:
Redundant each other, the backup of 2 cover CPU-north and south bridge systems; When a cover system breaks down or occurs unusually, supervisory system is turned off this cover system immediately, and opens another set of system immediately; Guarantee the key business operation that in the shortest time, is restored, strengthened the robustness of system's operation.
A, confirm original state;
B, the said CPU-north and south bridge system 1 concurrent pulse signal of energising and signal code are given said supervisory circuit;
Whether the signal of C, the lead-in wire of judging said CPU-north and south bridge system 1 and serial ports is normal;
D, transmission signal code are given said supervisory circuit;
Whether the signal of E, judgement lead-in wire interface, serial ports and network interface is normal;
F, give remote control terminal equipment with the state transfer of said CPU-north and south bridge system 1 and CPU-north and south bridge system 2.
Wherein practical implementation is following:
(1) restrictive condition: 2 cover CPU-north and south bridge systems can only 1 be enclosed within work with the time.Original state: 2 cover systems all do not have work, prepare to give CPU-north and south bridge system 1 to power on now, and it is started working.
(2) the power on signal line in supervisory circuit control power-on and power-off control, the reset circuit 1 powers on for CPU-north and south bridge system 1.
CPU1 begins Basic Input or Output System (BIOS) (Basic Input Output System; BIOS) operation; And give supervisory circuit at the pulse signal that the GPIO1 that the BIOS operation phase is controlled CPU1 sends out rule; Show that bridge system 1 operation in CPU-north and south is normal, and control serial ports 1 simultaneously and in the time interval of agreement, send the signal code (for example FE) of agreement for supervisory circuit;
If it is normal that supervisory circuit detects the signal of GPIO1 and serial ports 1 simultaneously, can not intervene the start-up course of CPU-north and south bridge system 1 so;
Occur unusually if detect any one road signal, will control power-on and power-off control, reset circuit 1 and shut down down electricly, and control power-on and power-off control, reset circuit 2 immediately, make CPU-north and south bridge system 2 carry out work.
If this moment, it is unusual that supervisory circuit finds that through monitoring GPIO4 and serial ports 3 bridge system 2 work in CPU-north and south have also occurred, and will notify remote control terminal equipment whole C PU-north and south bridge system to collapse.
(3) BIOS starts completion, and (Operating System OS) after the stage, enables GPIO2, GPIO3, network interface 1, serial ports 2 signal code that transmission is appointed in advance to supervisory circuit to get into operating system;
And the GPIO1 that the unloading phase of BIOS, enables, serial ports 1 still works on.
If (the detection interface comprises GPIO1 to find to go wrong any detection interface; GPIO2, GPIO3, network interface 1; Serial ports 1 and serial ports 2); Will control power-on and power-off control, reset circuit 1 electricity that shuts down down, and control power-on and power-off control, reset circuit 2 immediately, make CPU-north and south bridge system 2 carry out work.
If this moment, it is unusual that supervisory circuit finds that through monitoring GPIO4 and serial ports 3 bridge system 2 work in CPU-north and south have also occurred, and will notify remote control terminal equipment whole C PU-north and south bridge system to collapse.
Redundant each other, the backup of 2 cover CPU-north and south bridge systems that the redundant method for designing of doube bridge sheet mainboard provided by the invention relates to; When a cover system breaks down or occurs unusual; Supervisory system is turned off this cover system immediately; And open another set of system immediately, and guaranteed the key business operation that in the shortest time, is restored, strengthened the robustness of system's operation.
Should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not to its restriction; Although the present invention has been carried out detailed explanation with reference to the foregoing description; Under the those of ordinary skill in field be to be understood that: still can specific embodiments of the invention make amendment or be equal to replacement; And do not break away from any modification of spirit and scope of the invention or be equal to replacement, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (20)
1. the method for designing that doube bridge sheet mainboard is redundant is characterized in that the doube bridge sheet mainboard that said method is used comprises CPU-north and south bridge system 1, CPU-north and south bridge system 2 and supervisory circuit; Said CPU-north and south bridge system 1 and CPU-north and south bridge system 2 are symmetricly set on the both sides of said supervisory circuit;
Said method comprises the steps:
A, confirm original state;
B, the said CPU-north and south bridge system 1 concurrent pulse signal of energising and signal code are given said supervisory circuit;
Whether the signal of C, the lead-in wire of judging said CPU-north and south bridge system 1 and serial ports is normal;
D, transmission signal code are given said supervisory circuit;
Whether the signal of E, judgement lead-in wire interface, serial ports and network interface is normal;
F, give remote control terminal equipment with the state transfer of said CPU-north and south bridge system 1 and CPU-north and south bridge system 2.
2. method for designing as claimed in claim 1 is characterized in that, the original state in the said steps A is that said CPU-north and south bridge system 1 is in off position with CPU-north and south bridge system 2, prepares to give said CPU-north and south bridge system 1 energising.
3. method for designing as claimed in claim 1 is characterized in that, among the said step B, said supervisory circuit is controlled power-on and power-off control, the reset circuit 1 in the said CPU-north and south bridge system 1, gives said CPU-north and south bridge system 1 energising;
The CPU1 of said CPU-north and south bridge system 1 begins the BIOS operation phase, and the lead-in wire GPIO1 that controls CPU1 in the said BIOS operation phase sends out pulse signal to said supervisory circuit; The serial ports of controlling simultaneously in the CPU-north and south bridge system 11 sends signal code for said supervisory circuit.
4. method for designing as claimed in claim 1 is characterized in that, among the said step C, whether the signal that said supervisory circuit detects said lead-in wire GPIO1 and serial ports 1 is normal;
If detect lead-in wire GPIO1 and serial ports 1 arbitrary road abnormal signal; Then by said supervisory circuit control said power-on and power-off control, reset circuit 1 shuts down down; And the power-on and power-off control in the control CPU-north and south bridge system 2, reset circuit 2 gives CPU-north and south bridge system 2 energisings, makes said CPU-north and south bridge system 2 carry out work.
5. method for designing as claimed in claim 4 is characterized in that, when said CPU-north and south bridge system 2 carries out work, and lead-in wire GPIO4 and serial ports 3 in the said CPU-of the said monitor circuit monitors north and south bridge system 2;
If lead-in wire GPIO4 and serial ports 3 arbitrary road signals occur unusual; Carry out step F; Give doube bridge sheet mainboard medium-long range control terminal with the state transfer of the operation irregularity of said CPU-north and south bridge system 1 and CPU-north and south bridge system 2, the said BIOS operation phase starts completion.
6. method for designing as claimed in claim 1 is characterized in that, among the said step D, after the BIOS operation phase started completion, said CPU-north and south bridge system 1 got into the operating system OS operation phase; Said CPU1 enable to go between GPIO2 and GPIO3, network interface 1 and serial ports 2 sends signal code for said supervisory circuit.
7. method for designing as claimed in claim 1 is characterized in that, in the said step e, judges whether the signal of lead-in wire GPIO1, GPIO2 and GPIO3, network interface 1, serial ports 1 and serial ports 2 is normal;
If detect lead-in wire GPIO1, GPIO2 and GPIO3, network interface 1, serial ports 1 and serial ports 2 arbitrary road abnormal signals; Then by said supervisory circuit control said power-on and power-off control, reset circuit 1 shuts down down; And the power-on and power-off control in the control CPU-north and south bridge system 2, reset circuit 2 gives CPU-north and south bridge system 2 energisings, makes said CPU-north and south bridge system 2 carry out work.
8. method for designing as claimed in claim 7 is characterized in that, when said CPU-north and south bridge system 2 carries out work, and lead-in wire GPIO4 and serial ports 3 in the said CPU-of the said monitor circuit monitors north and south bridge system 2;
If lead-in wire GPIO4 and serial ports 3 arbitrary road signals occur unusual; Carry out step F; Give doube bridge sheet mainboard medium-long range control terminal with the state transfer of the operation irregularity of said CPU-north and south bridge system 1 and CPU-north and south bridge system 2, the said operating system OS operation phase starts completion.
9. method for designing as claimed in claim 1 is characterized in that, said CPU-north and south bridge system 1 comprises and connects Godson CPU1, north bridge 1 and south bridge 1 successively; Said north bridge 1 is connected with south bridge 1 through A-Link bus;
Said CPU-north and south bridge system 2 comprises and connects Godson CPU2, north bridge 2 and south bridge 2 successively; Said north bridge 2 is connected with south bridge 2 through A-Link bus;
Said Godson CPU1 and Godson CPU2 include data collecting card and memory bank.
10. method for designing as claimed in claim 1 is characterized in that, said doube bridge mainboard comprises non-volatile memory medium and remote control terminal equipment; Said non-volatile memory medium is connected with south bridge 2 with south bridge 1 respectively; Said remote control terminal equipment is connected with said supervisory circuit.
11. method for designing as claimed in claim 10 is characterized in that, said remote control terminal equipment through 100,000,000 or gigabit Ethernet be connected with supervisory circuit.
12. method for designing as claimed in claim 9 is characterized in that, said CPU-north and south bridge system 1 comprises serial ports 1, serial ports 2 and network interface 1; Said serial ports 1 is connected with said CPU1; Said network interface 1 is connected with said north bridge 1 through the PCIE bus; Said serial ports 2 is connected with said south bridge 1;
Said CPU-north and south bridge system 2 comprises serial ports 3, serial ports 4 and network interface 2; Said serial ports 3 is connected with said CPU2; Said network interface 2 be connected through the said north bridge 2 of PCIE bus; Said serial ports 4 is connected with said south bridge 2.
13. method for designing as claimed in claim 9 is characterized in that, said north bridge 1 includes AMD chipset SR5690, SR5670, SR5650 with north bridge 2; Comprise AMD chipset SP5100, SP5100R, SP5100RS with said north bridge 1 and north bridge 2 corresponding south bridges 1 with south bridge 2;
Said north bridge 1 also comprises AMD chipset RS780, RS780C, RS780D, RS780E, RS780G, RS780M, RS780MC, RX781, RS785G and RD790 with north bridge 2; The south bridge 1 corresponding with it comprises AMD chipset SB700, SB710, SB750 and SB600 with south bridge 2.
14. method for designing as claimed in claim 12 is characterized in that, said serial ports 1, serial ports 2, network interface 1, serial ports 3, serial ports 4 are connected with said supervisory circuit respectively with network interface 2.
15. method for designing as claimed in claim 9 is characterized in that, said CPU-north and south bridge system 1 comprises power-on and power-off control, reset circuit 1; Said CPU-north and south bridge system 2 comprises power-on and power-off control, reset circuit 2; Said power-on and power-off control, reset circuit 1 and power-on and power-off control, reset circuit 2 are connected with said supervisory circuit respectively.
16. method for designing as claimed in claim 9 is characterized in that, said CPU1 is connected with north bridge 1 through HT1 bus; Said CPU2 is connected with north bridge 2 through HT1 bus.
17. method for designing as claimed in claim 9 is characterized in that, said CPU1 is connected with said CPU2 through HT0 bus; Said CPU1 and CPU2 are the CPU of No. 3 series of Godson, comprise Godson 3A, 3B and 3C.
18. method for designing as claimed in claim 9 is characterized in that, draws a line GPIO1 at least from said CPU1 and is connected to said supervisory circuit; At least draw a line GPIO2 from said north bridge 1 and be connected to said supervisory circuit; At least draw a line GPIO3 from the said south bridge 1 and be connected to said supervisory circuit;
At least draw a line GPIO4 from said CPU2 and be connected to said supervisory circuit; At least draw a line GPIO5 from said north bridge 2 and be connected to said supervisory circuit; At least draw a line GPIO6 from the said south bridge 2 and be connected to said supervisory circuit.
19. method for designing as claimed in claim 1 is characterized in that, said supervisory circuit adopts the baseboard management controller chip to build or adopt singlechip chip to build; Said supervisory circuit adopts the accessory power supply power supply; The default conditions of said supervisory circuit are power-up states.
20., it is characterized in that said remote monitoring terminal unit comprises remote console like each described method for designing in the claim 10 and 11.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210172529.2A CN102768561B (en) | 2012-05-30 | 2012-05-30 | Design method for twinbridge piece mainboard redundancy |
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| CN201210172529.2A CN102768561B (en) | 2012-05-30 | 2012-05-30 | Design method for twinbridge piece mainboard redundancy |
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| Publication Number | Publication Date |
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| CN102768561A true CN102768561A (en) | 2012-11-07 |
| CN102768561B CN102768561B (en) | 2015-02-04 |
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| CN201210172529.2A Active CN102768561B (en) | 2012-05-30 | 2012-05-30 | Design method for twinbridge piece mainboard redundancy |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103064476A (en) * | 2013-01-18 | 2013-04-24 | 浪潮电子信息产业股份有限公司 | Design method of mainboard with dual CPUs (central processing units) with asymmetric memories |
| CN104182307A (en) * | 2014-08-25 | 2014-12-03 | 浪潮集团有限公司 | Serial port redundancy switching method on basis of independent redundancy server |
| CN105446833A (en) * | 2013-09-29 | 2016-03-30 | 华为技术有限公司 | Control method and control equipment of server |
| US10241868B2 (en) | 2013-09-29 | 2019-03-26 | Huawei Technologies Co., Ltd. | Server control method and server control device |
| CN110597159A (en) * | 2019-09-06 | 2019-12-20 | 浙江无极互联科技有限公司 | Computer remote monitoring control system |
| CN112988659A (en) * | 2021-05-07 | 2021-06-18 | 湖南华自信息技术有限公司 | PCIE bridge chip redundant mainboard, design method and computer storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060087822A1 (en) * | 2004-10-21 | 2006-04-27 | Via Technologies, Inc. | Integrated structure with CPU and north bridge chip |
| CN102214132A (en) * | 2011-05-16 | 2011-10-12 | 曙光信息产业股份有限公司 | Method and device for debugging Loongson central processing unit (CPU), south bridge chip and north bridge chip |
-
2012
- 2012-05-30 CN CN201210172529.2A patent/CN102768561B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060087822A1 (en) * | 2004-10-21 | 2006-04-27 | Via Technologies, Inc. | Integrated structure with CPU and north bridge chip |
| CN102214132A (en) * | 2011-05-16 | 2011-10-12 | 曙光信息产业股份有限公司 | Method and device for debugging Loongson central processing unit (CPU), south bridge chip and north bridge chip |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103064476A (en) * | 2013-01-18 | 2013-04-24 | 浪潮电子信息产业股份有限公司 | Design method of mainboard with dual CPUs (central processing units) with asymmetric memories |
| CN105446833A (en) * | 2013-09-29 | 2016-03-30 | 华为技术有限公司 | Control method and control equipment of server |
| US10241868B2 (en) | 2013-09-29 | 2019-03-26 | Huawei Technologies Co., Ltd. | Server control method and server control device |
| CN105446833B (en) * | 2013-09-29 | 2020-04-14 | 华为技术有限公司 | Control method of server and control device of server |
| CN104182307A (en) * | 2014-08-25 | 2014-12-03 | 浪潮集团有限公司 | Serial port redundancy switching method on basis of independent redundancy server |
| CN110597159A (en) * | 2019-09-06 | 2019-12-20 | 浙江无极互联科技有限公司 | Computer remote monitoring control system |
| CN112988659A (en) * | 2021-05-07 | 2021-06-18 | 湖南华自信息技术有限公司 | PCIE bridge chip redundant mainboard, design method and computer storage medium |
| CN112988659B (en) * | 2021-05-07 | 2021-07-20 | 湖南华自信息技术有限公司 | PCIE bridge chip redundant mainboard, design method and computer storage medium |
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| CN102768561B (en) | 2015-02-04 |
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