CN102147640A - Server with a plurality of main boards - Google Patents
Server with a plurality of main boards Download PDFInfo
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- CN102147640A CN102147640A CN2010101139954A CN201010113995A CN102147640A CN 102147640 A CN102147640 A CN 102147640A CN 2010101139954 A CN2010101139954 A CN 2010101139954A CN 201010113995 A CN201010113995 A CN 201010113995A CN 102147640 A CN102147640 A CN 102147640A
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- mainboard
- management controller
- south bridge
- server
- baseboard management
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Abstract
The invention provides a server with a plurality of main boards, comprising a first main board, a second main board, a first main board switch, a second main board switch and a baseboard management controller. The baseboard management controller (BMC) comprises a pass through in pin, a pass through out pin, a first general purpose input/output (GPIO) pin and a second GPIO pin. The pass through in pin is used for receiving a first main board control signal transmitted by the first main board switch. The pass through out pin is used for outputting the first main board control signal to a south bridge chip of the first main board. The first GPIO pin is used for receiving a second main board control signal outputted by the second main board switch. When the first GPIO pin receives the second main board control signal, the BMC copies the second main board control signal to obtain a copy signal, and the second GPIO pin is used for outputting the copy signal to the south bridge chip of the second main board. In such a way, a plurality of main boards can be used on the server.
Description
Technical field
The present invention relates to a kind of server, relate in particular to a kind of server with a plurality of mainboards.
Background technology
In known server system, a baseboard management controller (Ba seboard Management Controller can be installed all on each mainboard with a plurality of mainboards; BMC).Known server system is promptly with the baseboard management controller on each mainboard, and its mainboard at place is separately controlled in management respectively.Yet, a baseboard management controller all is installed on each mainboard, can improve the manufacturing cost of many server systems.
Summary of the invention
Therefore, one object of the present invention is exactly that a kind of server with a plurality of mainboards is being provided, it utilizes a baseboard management controller to control a plurality of mainboards simultaneously, and the while is by general input and output pin (the General Purpose Input Output of baseboard management controller; GPIO) transmit the mainboard controlling signal, so that the mainboard number that server can use is not subject to the number of the through type pin of baseboard management controller.
The embodiment one of according to the present invention, this server comprises first mainboard, second mainboard, the first mainboard switch, second mainboard switch and the baseboard management controller.First mainboard comprises first central processing unit (Center Processing Unit; CPU) and first South Bridge chip, wherein first South Bridge chip is the opening and closing that are used to control first mainboard.Second mainboard comprises second central processing unit and second South Bridge chip, and wherein second South Bridge chip is the switch that is used to control second mainboard.The first mainboard switch is to be used to export the first mainboard controlling signal.The second mainboard switch is to be used to export the second mainboard controlling signal.Baseboard management controller is to be used to control the first mainboard switch and the second mainboard switch, and wherein baseboard management controller comprises straight-through input (passthrough in) pin, straight-through output (passthrough out) pin, the first general input and output pin and the second general input and output pin.Straight-through input pin is electrically connected to the first mainboard switch, is used to receive the first mainboard controlling signal.Straight-through output connecting pin is electrically connected to first mainboard, is used to export first mainboard controlling signal to the first South Bridge chip, so that first South Bridge chip is opened first mainboard.The first general input and output pin is electrically connected to the second mainboard switch, is used to receive the second mainboard controlling signal.The second general input and output pin is electrically connected to second South Bridge chip of second mainboard, wherein when the first general input and output pin receives the second mainboard controlling signal, baseboard management controller duplicates the second mainboard controlling signal, duplicate signal to obtain one, and export this by the second general input and output pin and duplicate signal to the second South Bridge chip, so that second South Bridge chip is opened second mainboard.
Like this, utilize baseboard management controller that the signal on the general input and output pin is copied on the general input and output pin of another root, function with the input and output of simulation through type, just realized transmitting the mainboard controlling signal by general input and output pin, make the employed mainboard number of server not be subject to the number of the through type pin of baseboard management controller, and then the usefulness of enhancement service device, just can increase the number of spendable mainboard in the server.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of appended accompanying drawing:
Fig. 1 is the function block schematic diagram with server of a plurality of mainboards of the present invention; And
Fig. 2 is the pin of baseboard management controller of the server with a plurality of mainboards of the present invention and the annexation synoptic diagram of each mainboard.
Wherein, Reference numeral
100: server 110: control panel
112: network interface card 114: baseboard management controller
114a: straight-through input pin 114b: straight-through input pin
114c: straight-through input pin 114d: straight-through output connecting pin
114e: straight-through output connecting pin 114f: straight-through output connecting pin
114g: general input and output pin 114h: general input and output pin
116a: mainboard switch 116b: mainboard switch
116c: mainboard switch 116d: mainboard switch
120: mainboard 121: network interface card
123: programmable chip 125: South Bridge chip
127: central processing unit 131: network interface card
130: mainboard 135: South Bridge chip
133: programmable chip
137: central processing unit 141: network interface card
140: mainboard 145: South Bridge chip
143: programmable chip
147: central processing unit 151: network interface card
150: mainboard 155: South Bridge chip
153: programmable chip
157: central processing unit
Embodiment
Below will and describe clear explaination spirit of the present invention in detail with accompanying drawing, any those of ordinary skill in the art is after understanding preferred embodiment of the present invention, when can be by the disclosed technology of the present invention, change and modification, and do not break away from spirit of the present invention and scope.
Please refer to the 1st figure, it has illustrated the function block schematic diagram of server 100 according to an embodiment of the invention.Server 100 comprises control panel 110 and mainboard 120-150.In server 100, mainboard 120-150 is the data operation that is used to carry out server 100, and control panel 110 then is used to manage these mainboards.
Each mainboard all includes network interface card, programmable chip, South Bridge chip and central processing unit.For example: mainboard 120 includes network interface card 121, programmable chip 123, South Bridge chip 125 and central processing unit 127; Mainboard 130 includes network interface card 131, programmable chip 133, South Bridge chip 135 and central processing unit 137; Mainboard 140 includes network interface card 141, programmable chip 143, South Bridge chip 145 and central processing unit 147; Mainboard 150 includes network interface card 151, programmable chip 153, South Bridge chip 155 and central processing unit 157.In the following description, will be the running that example illustrates mainboard with mainboard 120.Merit attention is that in the present embodiment, the function mode of each mainboard is all identical.
In mainboard 120, network interface card 121 is windows that mainboard 120 is connected to external system, in order to the external system exchange message.Central processing unit 127 is to be used to handle the data that network interface card 121 is received, and the data after will handling send by network interface card 121, to finish the groundwork of server 100.South Bridge chip 125 is intermediary's devices of network interface card 121 and central processing unit 127, is used in network interface card 121 and 127 transmission of central processing unit data.
By above explanation as can be known, in the present embodiment, each mainboard is to utilize its programmable chip that comprises to come and the control panel swap data, and so control panel just can be learnt the information of each mainboard by the programmable chip on each mainboard, manages mainboard according to these information simultaneously.
In the present embodiment, baseboard management controller 114 adopts the pilot2 processor of serverengines company, this processor only provides 3 groups of through types (passthrough) pin, and promptly 3 straight-through input pins and 3 straight-through output connecting pins come to be electrically connected to mainboard for the mainboard switch.Yet present embodiment has been used 4 mainboards and has been come the construction server, therefore, will have a mainboard and can't use the through type pin to be connected with the mainboard switch.In order to address this problem, present embodiment utilizes general input and output (the General Purpose Input Output on the baseboard management controller 114; GPIO) pin transmits the mainboard controlling signal that the mainboard switch is transmitted.
Please refer to the 2nd figure, it has illustrated the pin of baseboard management controller 114 and the annexation of each mainboard.In the present embodiment, baseboard management controller 114 includes straight-through input (passthrough in) pin 114a-114c, straight-through output (passthrough out) pin 114d-114f and general input and output pin 114g and 114h, and wherein straight-through input pin 114a is corresponding to straight-through output connecting pin 114d; Straight-through input pin 114b is corresponding to straight-through output connecting pin 114e; Straight-through input pin 114c is corresponding to straight-through output connecting pin 114f.
Straight-through input pin 114a and straight-through output connecting pin 114d are electrically connected to the South Bridge chip 125 of mainboard switch 116a and mainboard 120 respectively.Straight-through input pin 114b and straight-through output connecting pin 114e are electrically connected to the South Bridge chip 135 of mainboard switch 116b and mainboard 130 respectively.Straight-through input pin 114c and straight-through output connecting pin 114f are electrically connected to the South Bridge chip 145 of mainboard switch 116c and mainboard 140 respectively.General input and output pin 114g and 114h are electrically connected to the South Bridge chip 155 of mainboard switch 116d and mainboard 150 respectively.
For mainboard 120, the mainboard controlling signal that mainboard switch 116a is transmitted can be sent to South Bridge chip 125 by straight-through input pin 114a and straight-through output connecting pin 114d, is unlocked or closes to inform baseboard management controller 114 mainboards 120.
Similarly, for mainboard 130, the mainboard controlling signal that mainboard switch 116b is transmitted can be sent to South Bridge chip 135 by straight-through input pin 114b and straight-through output connecting pin 114e, is unlocked or closes to inform baseboard management controller 114 mainboards 130.For mainboard 140, the mainboard controlling signal that mainboard switch 116c is transmitted can be sent to South Bridge chip 145 by straight-through input pin 114c and straight-through output connecting pin 114f, is unlocked or closes to inform baseboard management controller 114 mainboards 140.
For mainboard 150, the mainboard controlling signal that mainboard switch 116b is transmitted is to input in the baseboard management controller 114 by general input and output pin 114g.When baseboard management controller 114 receives this mainboard controlling signal, baseboard management controller 114 can be known that the user looks on the bright side of things and open mainboard 150, duplicate this mainboard controlling signal simultaneously, the mainboard controlling signal of duplicating is sent to South Bridge chip 155 by general input and output pin 114h.
By above explanation as can be known, present embodiment is to utilize baseboard management controller 114 that the signal on the general input and output pin is copied on the general input and output pin of another root, with the function of simulation through type input and output.Transmit the mainboard controlling signal by general input and output pin, can make the server 100 employed mainboard numbers of present embodiment not be subject to the number of the through type pin of baseboard management controller 114 and then the usefulness of enhancement service device 100 (spendable mainboard number increases).
Though the present invention discloses as above with by way of example; right its is not in order to limit the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the scope that claims define.
Claims (9)
1. the server with a plurality of mainboards is characterized in that, described server comprises at least:
One first mainboard comprises one first central processing unit (Center Processing Unit; CPU) and one first South Bridge chip, wherein said first South Bridge chip is used to control the opening and closing of described first mainboard;
One second mainboard comprises one second central processing unit and one second South Bridge chip, and wherein said second South Bridge chip is used to control the opening and closing of described second mainboard;
One first mainboard switch is used to export one first mainboard controlling signal;
One second mainboard switch is used to export one second mainboard controlling signal;
One baseboard management controller (Baseboard Management Controller; BMC), be used to control described first mainboard switch and the described second mainboard switch, wherein said baseboard management controller comprises:
One straight-through input (passthrough in) pin is electrically connected to the described first mainboard switch, is used to receive the described first mainboard controlling signal;
One straight-through output (passthrough out) pin is electrically connected to described first mainboard, is used to export the described first mainboard controlling signal to described first South Bridge chip, so that described first South Bridge chip is opened described first mainboard;
One first general input and output (General Purpose Input Output; GPIO) pin is electrically connected to the described second mainboard switch, is used to receive the described second mainboard controlling signal;
One second general input and output pin, be electrically connected to described second South Bridge chip of described second mainboard, wherein when the described first general input and output pin receives the described second mainboard controlling signal, described baseboard management controller duplicates the described second mainboard controlling signal, duplicate signal to obtain one, and export the described signal that duplicates to described second South Bridge chip by the described second general input and output pin, so that described second mainboard is opened or closed to described second South Bridge chip.
2. the server with a plurality of mainboards according to claim 1 is characterized in that, described first mainboard more comprises:
One first network interface card is electrically connected to described first South Bridge chip, carries out data transmission for described first central processing unit and remote system; And
One first programmable chip is electrically connected between described first South Bridge chip and the described baseboard management controller, so that described baseboard management controller is controlled described first mainboard by described first programmable chip.
3. the server with a plurality of mainboards according to claim 2 is characterized in that, described second mainboard more comprises:
One second network interface card is electrically connected to described second South Bridge chip, carries out data transmission for described second central processing unit and remote system; And
One second programmable chip is electrically connected between described second South Bridge chip and the described baseboard management controller, so that described baseboard management controller is controlled described second mainboard by described second programmable chip.
4. the server with a plurality of mainboards according to claim 3, it is characterized in that, (Intelligent Platform Management Bus, IPMB) host-host protocol carries out communication by an intelligent platform management bus between described baseboard management controller and described first programmable chip.
5. the server with a plurality of mainboards according to claim 2 is characterized in that, described first programmable chip is CPLD (Complex Programmable LogicDevice; CPLD) or peripheral interface controller (Peripheral InterfaceController; PIC).
6. the server with a plurality of mainboards according to claim 3 is characterized in that, described second programmable chip is CPLD or programmable integrated circuit.
7. the server with a plurality of mainboards according to claim 1 is characterized in that described server more comprises a network interface card, is electrically connected to described baseboard management controller, is used for carrying out data transmission for described baseboard management controller and remote system.
8. the server with a plurality of mainboards according to claim 1 is characterized in that, the host-host protocol between described first mainboard and the described baseboard management controller is intelligent platform management bus.
9. the server with a plurality of mainboards according to claim 1 is characterized in that, the host-host protocol between described second mainboard and the described baseboard management controller is intelligent platform management bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101139954A CN102147640A (en) | 2010-02-05 | 2010-02-05 | Server with a plurality of main boards |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101139954A CN102147640A (en) | 2010-02-05 | 2010-02-05 | Server with a plurality of main boards |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102147640A true CN102147640A (en) | 2011-08-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101139954A Pending CN102147640A (en) | 2010-02-05 | 2010-02-05 | Server with a plurality of main boards |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120159035A1 (en) * | 2010-12-15 | 2012-06-21 | Hon Hai Precision Industry Co., Ltd. | System and method for switching use of serial port |
| CN103064769A (en) * | 2012-12-30 | 2013-04-24 | 长沙湘计海盾科技有限公司 | Dual hot standby server system |
| CN103425219A (en) * | 2012-05-18 | 2013-12-04 | 鸿富锦精密工业（深圳）有限公司 | Power supply control system and method |
| CN104503947A (en) * | 2014-12-16 | 2015-04-08 | 华为技术有限公司 | Multi-server and signal processing method thereof |
| CN106055361A (en) * | 2016-05-31 | 2016-10-26 | 深圳市国鑫恒宇科技有限公司 | Integrated firmware implementation method and system based on various different models of BMC (baseboard management controller) |
| CN109120143A (en) * | 2018-07-25 | 2019-01-01 | 郑州云海信息技术有限公司 | A kind of method, master controller and system controlling power-on and power-off |
| CN109213268A (en) * | 2017-07-04 | 2019-01-15 | 佛山市顺德区顺达电脑厂有限公司 | Server cabinet system and its signal transmission frequency method of adjustment |
-
2010
- 2010-02-05 CN CN2010101139954A patent/CN102147640A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120159035A1 (en) * | 2010-12-15 | 2012-06-21 | Hon Hai Precision Industry Co., Ltd. | System and method for switching use of serial port |
| US8819318B2 (en) * | 2010-12-15 | 2014-08-26 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | System and method for switching use of serial port |
| CN103425219A (en) * | 2012-05-18 | 2013-12-04 | 鸿富锦精密工业（深圳）有限公司 | Power supply control system and method |
| CN103064769A (en) * | 2012-12-30 | 2013-04-24 | 长沙湘计海盾科技有限公司 | Dual hot standby server system |
| CN104503947A (en) * | 2014-12-16 | 2015-04-08 | 华为技术有限公司 | Multi-server and signal processing method thereof |
| CN106055361A (en) * | 2016-05-31 | 2016-10-26 | 深圳市国鑫恒宇科技有限公司 | Integrated firmware implementation method and system based on various different models of BMC (baseboard management controller) |
| CN109213268A (en) * | 2017-07-04 | 2019-01-15 | 佛山市顺德区顺达电脑厂有限公司 | Server cabinet system and its signal transmission frequency method of adjustment |
| CN109120143A (en) * | 2018-07-25 | 2019-01-01 | 郑州云海信息技术有限公司 | A kind of method, master controller and system controlling power-on and power-off |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
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Application publication date: 20110810 |