CN118017805A

CN118017805A - Power supply system, vehicle, method, apparatus, and storage medium

Info

Publication number: CN118017805A
Application number: CN202410179170.4A
Authority: CN
Inventors: 李海
Original assignee: Black Sesame Intelligent Technology Co ltd
Current assignee: Black Sesame Intelligent Technology Co ltd
Priority date: 2024-02-07
Filing date: 2024-02-07
Publication date: 2024-05-10

Abstract

The application relates to a power supply system, a vehicle, a method, an apparatus and a storage medium. The power supply system is used for supplying power to a plurality of SOC chips, and comprises an MCU chip and a plurality of PMIC chips, and each of the plurality of SOC chips is connected with the MCU chip through at least one corresponding PMIC chip. The MCU chips are configured to write power-on parameters of a corresponding set of power rail signals of each SOC chip into a corresponding PMIC chip of each SOC chip when power is on; the power-up parameters include the power-up timing and voltage level of each power rail signal in the set of power rail signals. Each PMIC chip is configured to output a set of power rail signals having voltage levels to a corresponding one of the connected SOC chips in accordance with a power-up timing upon receiving power-up parameters of the set of power rail signals from the MCU chip to power the SOC chip. The system can realize proper power supply to a plurality of SOC chips.

Description

Power supply system, vehicle, method, apparatus, and storage medium

Technical Field

The present application relates to the field of power supply technologies, and in particular, to a power supply system, a vehicle, a method, an apparatus, and a storage medium.

Background

With the continuous development of automobile control technology, by mounting an advanced driving assistance system (ADVANCED DRIVING ASSISTANCE SYSTEM, ADAS) on an automobile, the automobile can sense the surrounding environment at any time in the driving process by utilizing various sensors (such as millimeter wave radar, laser radar, a single/double camera, a satellite navigation system and the like) mounted on the automobile, collect data, identify, detect and track static and dynamic objects, and combine navigation map data to perform systematic operation and analysis, thereby providing various driving reference information for a driver, enabling the driver to perceive possible danger in advance, and effectively increasing the comfort and safety of automobile driving.

In early ADAS systems, a System On Chip (SOC) is adopted, and the core task of the System on Chip is to process and process various data, and the SOC needs to be connected with various vehicle-mounted sensor devices, including vehicle-mounted laser radar sensors, vehicle-mounted high-definition camera sensors, vehicle-mounted millimeter wave sensors, vehicle-mounted integrated navigation sensors and the like. Along with development of ADAS system technology, the numerous vehicle-mounted sensors bring about massive data transmission and data processing, and for this reason, the number of SOC chips in an ADAS system is continuously increased, and ADAS systems adopting double SOC chips and four or more SOC chips are more and more common.

For a single SOC chip, it is often necessary to use multiple independent dc power rail lines to provide multiple power rail signals to the device cores, RAM, internal cache, external expansion input-output interfaces, and other ports in the SOC chip for power. These power rail signals may be of different specifications, and the required voltage and current may vary, such as 0.8V/5A, 1.1V/3A, and 1.8V/2.5A, etc., which can complicate the power management system of the system if a single power chip is used. In ADAS system design, a SOC chip may be equipped with a Power MANAGEMENT INTEGRATED Circuit (PMIC) chip to provide Power for each path.

ADAS systems with a single SOC chip can employ one PMIC chip to power the SOC chip, however, with the advent of ADAS systems with multiple SOC chips, power management has become more complex. On the basis that each SOC chip needs to be powered by using a plurality of different power rails, the power-on time sequences and the power levels of a plurality of power rail signals used by the power supply of the different SOC chips can be different from each other, and how to manage and control a plurality of power rail signals related to the plurality of SOC chips becomes a difficult problem. Therefore, how to reasonably supply power to a plurality of SOC chips is a problem to be solved.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a power supply system, a vehicle, a method, an apparatus, and a storage medium capable of supplying power to a plurality of SOC chips.

A power supply system for supplying power to a plurality of SOC chips, the power supply system comprising an MCU chip and a plurality of PMIC chips, and each SOC chip of the plurality of SOC chips being connected to the MCU chip via a corresponding at least one PMIC chip, wherein the MCU chip is configured to: when power is on, the power-on parameters of a corresponding group of power rail signals of each SOC chip are written into a corresponding PMIC chip of each SOC chip; the power-on parameters comprise power-on time sequence and voltage level of each power rail signal in the group of power rail signals; each PMIC chip is configured to: upon receiving a power-up parameter of a set of power rail signals from the MCU chip, a set of power rail signals having a voltage level in the power-up parameter is output to a corresponding one of the connected SOC chips in accordance with a power-up timing in the power-up parameter to supply power to the SOC chip.

A vehicle comprises the power supply system, a plurality of SOC chips and a plurality of vehicle-mounted sensors, wherein the power supply system is connected with the plurality of SOC chips and used for supplying power to the plurality of SOC chips, and the plurality of SOC chips are connected with the plurality of vehicle-mounted sensors.

The power supply system is used for supplying power to a plurality of SOC chips, the power supply system comprises an MCU chip and a plurality of PMIC chips, and each of the plurality of SOC chips is connected with the MCU chip through at least one corresponding PMIC chip, wherein the method comprises the following steps: when the MCU chip is electrified, the electrifying parameters of a group of power rail signals corresponding to each SOC chip are written into a PMIC chip corresponding to each SOC chip; the power-on parameters comprise power-on time sequence and voltage level of each power rail signal in the group of power rail signals; and outputting, by each PMIC chip, upon receiving a power-on parameter of a set of power rail signals from the MCU chip, the set of power rail signals having a voltage level in the power-on parameter to a corresponding one of the connected SOC chips in accordance with a power-on timing in the power-on parameter to supply power to the SOC chip.

The utility model provides a power supply device, is applied in the power supply system, and the power supply system is used for supplying power to a plurality of SOC chips, and the power supply system includes MCU chip and a plurality of PMIC chip, and each SOC chip in a plurality of SOC chips is connected the MCU chip via corresponding at least one PMIC chip, wherein this device includes: the MCU chip control module is used for enabling the MCU chips to write the power-on parameters of a group of power rail signals corresponding to each SOC chip into a PMIC chip corresponding to each SOC chip when the MCU chips are powered on; the power-on parameters comprise power-on time sequence and voltage level of each power rail signal in the group of power rail signals; and a PMIC chip control module for enabling each PMIC chip to output a set of power rail signals with voltage levels in the power-on parameters to a corresponding one of the connected SOC chips according to the power-on time sequence in the power-on parameters when the power-on parameters of the set of power rail signals are received from the MCU chip to supply power to the SOC chips.

A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the method as above.

According to the power supply system, the vehicle, the method, the device and the storage medium, the MCU chip is utilized to enable and control the PMIC chips, the MCU chip can respectively control the PMIC chips to supply power to the power rails of the corresponding SOC chips through the flow and design meeting the functional safety, each SOC chip is controlled by the MCU chip to supply power through at least one corresponding PMIC chip, therefore, under the condition that different power rails are required by different power rail power-on time sequences and power levels, the MCU chip can also conveniently and respectively control the PMIC chips to supply power to the corresponding SOC chips by using the corresponding power-on parameters, the power rails of the different SOC chips are not affected by each other, the management and control of complex power-on time sequences and power level differences among the different SOC chips are not needed, the reasonable power supply to the plurality of SOC chips can be realized, and the scheme is easy to realize.

Drawings

FIG. 1 is a schematic diagram of a power supply system in one embodiment;

FIG. 2 is a schematic diagram of power-on parameters of a set of power rail signals of the MCU chip 1 according to one embodiment;

FIG. 3 is a schematic diagram of power-on parameters of a set of power rail signals of the MCU chip 3 in one embodiment;

FIG. 4 is a schematic diagram of the power down parameters of a set of power rail signals of the MCU chip 3 in one embodiment;

FIG. 5 is a schematic diagram of a power supply system according to another embodiment;

FIG. 6 is a schematic diagram of a PMIC chip 1 in one embodiment consisting of a PMIC sub-chip 1a and a PMIC sub-chip 1b instead;

FIG. 7 is a schematic diagram of a fast-port signal line between the MCU chip and the PMIC chip 1 according to one embodiment;

FIG. 8 is a schematic diagram of a power supply system provided with a redundant power supply structure in one embodiment;

FIG. 9 is a schematic diagram of a power supply system with a redundant power supply structure in another embodiment;

FIG. 10 is a schematic diagram of a vehicle provided with a power supply system in one embodiment;

FIG. 11 is a flow chart of a method of power supply in one embodiment;

FIG. 12 is a flowchart of a power supply method according to another embodiment;

fig. 13 is a block diagram of a power supply device in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

Conventional ADAS systems typically involve only a single SOC chip and use one PMIC chip to power the SOC chip. However, with the advent of ADAS systems with multiple SOC chips, power management becomes more complex, and how to reasonably supply power to multiple SOC chips becomes a problem to be solved.

One solution is considered to adopt a design scheme in which multistage PMIC chips are cascaded, for example, one master PMIC chip is set in a plurality of PMIC chips, a plurality of slave PMIC chips are connected through special control lines, and the master PMIC chip sends control commands to the slave PMIC chips to control the power supply to each SOC chip. However, this scheme is only suitable for the case of SOC chips and fewer PMIC chips to be used, when the number of SOC chips to be supplied and PMIC chips to be used is large, the control program to be burned into the master PMIC chip will become complicated and huge, but because the ROM area inside the PMIC chip is small, only a simple design file can be burned, and a complex program for multiple logic control cannot be written, so that the master PMIC chip is difficult to realize the control of more slave PMIC chips, and the requirement of supplying power to more SOC chips cannot be satisfied.

In view of at least one of the above-mentioned technical problems, the present application provides a power supply system for supplying power to a plurality of SOC chips. Referring to fig. 1, the power supply system includes a micro control unit (Microcontroller Unit, MCU chip) chip and a plurality of PMIC chips, and each of the plurality of SOC chips is connected to the MCU chip via a corresponding at least one PMIC chip. In the example shown in fig. 1, four or more PMIC chips 1,2, 3 … … n and four or more SOC chips 1,2, 3 … … n connected in one-to-one correspondence with PMIC chips 1,2, 3 … … n are shown, however, it is understood that the total number of SOC chips and the total number of PMIC chips set accordingly may be changed according to actual needs, for example, 2 or 3. Further, in the example shown in fig. 1, each SOC chip is connected to one PMIC chip, however, in other examples, one SOC chip may be connected to two or more PMIC chips to which power is supplied simultaneously or by switching, which will be described in the subsequent examples.

When power needs to be supplied to each SOC chip, the MCU chip can respectively control the PMIC chip corresponding to each SOC chip to supply power to each SOC chip. Wherein, the MCU chip is configured as: when power is on, the power-on parameters of a corresponding group of power rail signals of each SOC chip are written into a corresponding PMIC chip of each SOC chip; wherein the power-up parameters include a power-up timing and a voltage level of each power rail signal in the set of power rail signals; each PMIC chip is configured to: upon receiving a power-up parameter of a set of power rail signals from the MCU chip, a set of power rail signals having a voltage level contained in the received power-up parameter is output to a corresponding one of the connected SOC chips in accordance with a power-up timing contained in the received power-up parameter to supply power to the SOC chip.

The MCU chip of the application can be internally provided with a programmable memory for storing the starting configuration information of a plurality of SOC chips, for example, the corresponding relation between each SOC chip and the PMIC chip, the power-on parameters of each SOC chip and other information can be stored. Therefore, when the power is on, the MCU chip can write the power-on parameters of each SOC chip into the corresponding PMIC chip according to the information stored by the MCU chip. Therefore, the MCU chip is used for storing and processing information, each PMIC chip is comprehensively controlled to supply power to each SOC chip, external components which are usually used for setting output voltage and power supply time sequence are greatly reduced, the stability of the whole power supply structure is much higher than that of ADAS systems matched by using a separation device, but the product cost can be reduced, and the power supply scheme for reducing the cost and enhancing the efficiency is realized for the vehicle-mounted ADAS equipment.

Because the requirement of the whole power supply of the SOC chip on power is strict, a chip control logic module, a microprocessor/microcontroller kernel module, a digital signal processor module, an embedded memory module, an interface module for external communication and the like are included in the SOC chip, the necessary condition of normal starting of each module is that the power supply on power has a correct sequence, one condition can be switched to the next step after being met, and if one link in the SOC chip has a fault, the whole power supply process of the SOC chip cannot be continued. The set of power rail signals output by the PMIC chip must meet the overall power-on timing of the SOC chip.

The number and variety of voltages, power-on timing and voltage levels of the power rail signals of each set to be used by each SOC chip may be the same or different from each other. Accordingly, the power-up parameters of the respective SOC chips may be the same or different from each other. In one embodiment, the power-on parameters of at least two of the plurality of SOC chips are different from each other.

For example, a set of power rail signals to be used by SOC chip 1 in fig. 1 includes vddio_sdio1, vddio_soc1, USB20_vdd1, DDR0_vdd1/DDR1_vdd1, mipi_vph1, mipi_vp1, rst_n1. The VDDIO_SDIO1, VDDIO_SOC1, USB20_VDD1 and DDR0_VDD1/DDR1_VDD1 belong to switching power supplies, the switching tubes work in a high-speed alternating on-off state to convert direct current into power supplies, the power consumption is very small, the electric energy conversion efficiency can reach more than 90%, and the switching tubes are mainly used for providing power supplies with high current consumption for the SOC chip 1; VDDIO_SDIO1 is used to power a General-purpose input/output (GPIO) interface of the SOC chip 1; the VDDIO_SOC1 is used for supplying power to a core arithmetic unit of the SOC chip 1; the USB20_VDD1 is used for supplying power to the USB interface unit of the SOC chip 1; the DDR0_VDD1/DDR1_VDD1 is used for supplying power to a memory interface unit of the SOC chip 1; MIPI_VPH2 and MIPI_VP1 belong to linear voltage stabilizer power supplies, the power consumption is small, the electric energy conversion efficiency is lower than 90%, the linear voltage stabilizer power supplies are mainly used for providing power supplies with small current consumption for the SOC chip 1, ripple waves are small, and the MIPI_VPH2 and MIPI_VP1 can supply power for a sensor data interface unit of the SOC chip 1. Rst_n1 is a signal for resetting the SOC chip 1 by the PMIC chip 1, belongs to a level control signal, and low-level hardware resets the SOC chip 1 as an enable signal for the PMIC chip 1 to start the SOC chip 1. Since the voltage and current of the power rail signals vddio_sdio1, vddio_soc1, USB20_vdd1, DDR0_vdd1/DDR1_vdd1, mipi_vph1, mipi_vp1, rst_n1 are different, they cannot be used in a mixed manner, and they can only be output to the SOC chip 1 by the PMIC chip 1 at a certain timing, and these different power output signals are collectively referred to as a set of power rail signals output by the PMIC chip 1. Normally, the SOC chip 1 is started and operated normally, and the PMIC chip 1 needs to output the set of power rail signals according to a correct starting manner and a correct output specification to meet the requirements.

Accordingly, as an example, the power-up parameters of a set of power rail signals of the SOC chip 1 are shown in fig. 2. As can be seen from fig. 2, the voltage levels of the power rail signals of the paths output from the PMIC chip 1 to the SOC chip 1 are different from each other: the voltage level of vddiosdio 1 is 3.0V; the voltage level of VDDIO_SOC1 is 1.8V; the voltage level of USB20 VDD1 is 3.3V; the voltage level of DDR0_VDD1/DDR1_VDD1 is 0.8V; the voltage level of mipi_vph1 is 1.8V; the voltage level of mipi_vp is 0.8V; the voltage level of RST_N is 1.8V. The power-on time sequence of each path of power rail signal output by the PMIC chip 1 is different: VDDIO_SDIO1 and VDDIO_SOC1 are powered on simultaneously, and the power-on time is T1; the power-on time of the USB20_VDD is T2; the power-on time of DDR0_VDD1/DDR1_VDD1 is T3; MIPI_VPH and MIPI_VP are powered on simultaneously, and the power-on time is T4; the pull-up time of RST_N is T5. The time interval between T1 and T3 is 20ms and the time interval between T2 and T3 is 10ms, so the time interval between T1 and T2 is 10ms. The time interval between T3 and T4 is 10us; the time interval between T4 and T5 is 40ms. Therefore, the power-on timing of the set of power rail signals output from the PMIC chip 1 to the SOC chip 1 includes T1 to T5, and the overall time interval is time interval between T1 to T5=60.01 ms. After RST_N is pulled up, SOC chip 1 is started.

The SOC chip 2 has, for example, the same set of power rail signals and power-up parameters as the SOC chip 1 described above. Specifically, the set of power rail signals that the SOC chip 2 needs to use includes vddio_sdio2, vddio_soc2, USB20_vdd2, DDR0_vdd2/DDR1_vdd2, mipi_vph2, mipi_vp2, rst_n2. The power-up parameters of the set of power rail signals of the SOC chip 2 may be similarly shown as the power-up parameters of the SOC chip 1 in fig. 2.

The SOC chip 3 has, for example, a different set of power rail signals and power-up parameters than the SOC chip 1 and SOC chip 2 described above. Specifically, the set of power rail signals that the SOC chip 3 needs to use includes vddio_sdio3, vddio_soc3, USB3.0_vdd3, DDR0_vdd3/DDR1_vdd3, mipi_vph3, mipi_vp3, rst_n3. As an example, the power-up parameters of a set of power rail signals that the SOC chip 3 needs to use are shown in fig. 3. As can be seen from fig. 3, the voltage levels of the power rail signals of the paths output from the PMIC chip 3 to the SOC chip 3 are different from each other: the voltage level of USB3.0_vdd is 3.3V; the voltage level of VDDIO_SOC is 3.0V; the voltage level of mipi_vph is 1.8V; the voltage level of vddiosdio is 1.8V; the voltage level of DDR0_VDD/DDR1_VDD is 1.1V; the voltage level of mipi_vp is 0.8V; the voltage level of RST_N is 1.8V. The power-on time sequence of each path of power rail signal output by the PMIC chip 3 is different: USB3.0_VDD and VDDIO_SOC are powered on simultaneously, and the power-on time is T1; MIPI_VPH and VDDIO_SDIO are powered on simultaneously, and the power-on time is T2; DDR0_VDD/DDR1_VDD and MIPI_VP are powered on simultaneously, and the power-on time is T3; the pull-up time of RST_N is T4. The time interval between T1 and T2 is 10ms, the time interval between T2 and T3 is 13ms, and the time interval between T3 and T4 is 20ms. Therefore, the power-on timing of the set of power rail signals output from the PMIC chip 3 to the SOC chip 3 includes T1 to T4, and the overall time interval is time interval=43 ms between T1 to T4. After rst_n pull-up, SOC chip 3 is started.

The SOC chip n has, for example, the same set of power rail signals and power-up parameters as the SOC chip 3 described above. Specifically, the set of power rail signals that the SOC chip n needs to use includes vddio_sdio on, vddio_socn, USB3.0_vddn, DDR0_vddn/DDR1_vddn, mipi_vphn, mipi_vpn, rst_nn. The power-up parameters of the set of power rail signals of SOC chip n may be similarly shown as the power-up parameters of SOC chip 3 in fig. 3.

According to the power supply system, the MCU chip is utilized to enable and control the plurality of PMIC chips, the MCU chip can respectively control the plurality of PMIC chips to supply power to the corresponding plurality of SOC chips through meeting the flow and design of functional safety, each SOC chip is controlled by the MCU chip to supply power through at least one corresponding PMIC chip, therefore, under the condition that different SOC chips have the power-on time sequence and the level requirement of different groups of power rail signals, the MCU chip can also conveniently and respectively control the PMIC chips to supply power to the corresponding SOC chips by using the corresponding power-on parameters, management and control among the power rail signals of the different SOC chips do not influence each other, and the management and control on the complicated power-on time sequence and the level difference among the different SOC chips are not required to be considered, so that the reasonable power supply to the plurality of SOC chips can be realized, and the scheme is easy to realize.

In addition, when it is necessary to power down the respective SOC chips, the MCU chip may control the PMIC chips corresponding to the respective SOC chips to power down the respective SOC chips, respectively. In one embodiment, the MCU chip is further configured to: when power is turned off, a power-off instruction is sent to each PMIC chip which is supplying power to the SOC chip; and each PMIC chip is further configured to: when a power-down instruction is received from the MCU chip, the reverse time sequence of the power-up time sequence is used as the power-down time sequence, and the output of a group of power rail signals to a corresponding SOC chip is closed according to the power-down time sequence.

For example, when the SOC chip needs to be normally turned off, each SOC chip stores various data first, turns off the communication of various external devices (for example, various sensors connected to the SOC chip itself), and then notifies the MCU chip of ready power-off, at this time, the MCU chip checks the working condition of each PMIC chip first, notifies each PMIC chip through the I2C bus of ready power-off signal output, the MCU chip sends out an instruction to turn off each power rail line again after obtaining a response reply of each PMIC chip, and after obtaining the instruction, each PMIC chip turns off the output of each group of power rail signals according to a reverse timing of the power-on timing sequence of each group of power rail signals that is being output by itself.

The power-down time sequence of a group of power rail signals needed by the SOC chip can be the reverse time sequence of the power-up time sequence. For example, referring to fig. 4, an example of the power-down parameter corresponding to the power-up parameter of the SOC chip 3 shown in fig. 3 is shown in fig. 4. As can be seen from fig. 4, the power-down timing of the SOC chip 3 is the reverse timing of the power-up timing of the SOC chip 3. Accordingly, the PMIC chip 3 may perform the power-down operation on the SOC chip 3 that it is powering up in the following order: firstly, the PMIC chip 3 pulls down RST_N, at the moment, the SOC chip 3 starts to be powered down and is closed, and the pulling down moment of the RST_N is T5; the DDR0_VDD/DDR1_VDD and the MIPI_VP are powered down simultaneously, and the power down time is T6; MIPI_VPH and VDDIO_SDIO are powered down simultaneously, and the power down time is T7; USB3.0_VDD and VDDIO_SOC are powered down simultaneously, and the power down time is T8. Wherein the time interval between T5 and T6 is 20ms, the time interval between T6 and T7 is 13ms, and the time interval between T7 and T8 is 10ms. Thus, the power-down timing of the set of power rail signals output by the PMIC chip 3 to the SOC chip 3 includes T5 to T8, and the overall time interval is time interval=43 ms between T5 to T8. Just opposite to the power-on timing of a set of power rail signals output by the PMIC chip 3 to the SOC chip 3.

It will be appreciated that the above power-up and power-down parameters in fig. 2-4 are merely examples, and the power-up and power-down parameters used by each set of power rail signals may be configured according to the actual use needs of each SOC chip.

Wherein the MCU chip is connected to each PMIC chip via a suitable communication line. In one embodiment, referring to fig. 5, the MCU chip may connect the respective PMIC chips via an I2C bus. The PMIC chip generally meets the requirements of the vehicle regulations and can support an I2C bus protocol, and the I2C bus protocol can support communication between a plurality of communication hosts and a plurality of communication slaves. In the application, the MCU chip can be used as a communication host of the I2C bus protocol, and each PMIC chip is used as a communication slave of the I2C bus protocol, so that the MCU chip can control each PMIC chip through the I2C bus. Referring to fig. 5, the I2C bus may include a clock line i2c_scl of the I2C bus protocol and a data line i2c_sda of the I2C bus protocol, which are connected to the respective PMIC chips, respectively. The clock line I2C_SCL is a unidirectional line supporting the transmission of clock signals from the MCU chip to the PMIC chip, and the data line I2C_SDA is a bidirectional line supporting the transmission of data from the MCU chip to the PMIC chip as well as the PMIC chip to the MCU chip. It will be appreciated that the I2C bus of fig. 5 is merely an example, and in other examples, the MCU chip and the PMIC chip may be connected via other suitable communication lines for transmitting time information and data information.

Wherein each SOC chip is connected to each PMIC chip corresponding thereto via an appropriate communication line. In one embodiment, each SOC chip may be connected to a corresponding each PMIC chip via a corresponding set of power rail lines.

For example, referring to fig. 5, corresponding to the foregoing examples of the respective sets of power rail signals of SOC chips 1,2, 3, N, in this example, respectively, PMIC chip 1 may be connected to SOC chip 1 via a set of power rail lines vddio_sdio1, vddio_soc1, USB20_vdd1, DDR0_vdd1/DDR1, mipi_vph1, mipi_vp1, rst_n1, PMIC chip 2 may be connected to SOC chip 1 via a set of power rail lines vddio_sdio2, vddio_soc2, USB20_vdd2, DDR0_vdd2/DDR1_vdd2, mipi_vph2, mipi_vp2, rst_n2, and SOC chip 2, and PMIC chip 3 may be connected to vddio_sdio3, vddio_soc3, USB 3.0_3, DDR 0/DDR 1_vdd_vph3, mipi_vph3, mipi_nmic3, and vddion_song3, vddion_song2. Each PMIC chip may transmit a corresponding kind of power rail signal via each power rail line, respectively, e.g., PMIC chip 1 may transmit VDDIO SDIO1 signal to SOC chip 1 via VDDIO SDIO1 line. It will be appreciated that the set of power rail lines of fig. 5 is merely an example, and in other examples, the set of power rail lines connected between the PMIC chip and the SOC chip may have different types of configurations, depending on the sensor to which the SOC chip is connected, and the like.

In one embodiment, at least one PMIC chip is composed of a plurality of PMIC sub-chips, i.e., a plurality of PMIC sub-chips may be utilized instead of the aforementioned one PMIC chip to realize the function of the one PMIC chip. Correspondingly, the plurality of PMIC sub-chips are respectively connected with the MCU chip via the I2C bus, and a corresponding set of power supply rail lines connected between the replaced one PMIC chip and the SOC chip are arranged between the plurality of PMIC sub-chips and the SOC chip in a scattered manner. In some cases, when the number of a set of power rail signals that a certain SOC chip needs to use is large, it may be difficult for a single PMIC chip to take such a huge number of output tasks of the power rail signals, and thus, it may be considered to use two or more PMIC chips to compose and act as one PMIC chip to share the output of a set of power rail signals of one SOC chip together. In the present application, each of a plurality of PMIC chips that thus share the output of a set of power rail signals of one SOC chip is referred to as a PMIC sub-chip for ease of understanding and distinction. It can be understood that the power rail lines connected to each of the plurality of PMIC sub-chips sharing one SOC chip are different from each other, and the union of the power rail lines connected to each of the plurality of PMIC sub-chips is a set of power rail lines corresponding to the one SOC chip.

For example, referring to fig. 6, the PMIC chip 1 may alternatively be composed of a PMIC sub-chip 1a and a PMIC sub-chip 1b, the PMIC sub-chip 1a and the PMIC sub-chip 1b being connected to the MCU chip via the I2C bus, respectively, and the PMIC sub-chip 1a being connected to the SOC chip 1 via vddio_sdio1, vddio_soc1, USB20_vdd1 lines, the PMIC sub-chip 1b being connected to the SOC chip 1 via the remaining DDR0_vdd1/DDR1_vdd1, mipi_vph1, mipi_vp1, rst_n1 lines, the PMIC sub-chip 1a and the PMIC sub-chip 1b being combined to realize the function of one PMIC chip 1 instead of one PMIC chip 1. It will be appreciated that fig. 6 is only an example, and in other examples, one PMIC chip may be composed of three or more PMIC sub-chips, and two or more PMIC chips may be composed of a plurality of PMIC sub-chips in the power supply system.

In order to facilitate the MCU chip to perform individual operation and control on each PMIC chip, a unique address may also be set for each PMIC chip. In one embodiment, each PMIC chip has a unique address, the MCU chip is further configured to: each PMIC chip is addressed with a unique address for each PMIC chip.

Taking the SOC chip as an example, each PMIC chip is connected via an I2C bus, each PMIC chip may have an independent address on the I2C bus. Although all the PMIC chips are connected to the I2C bus, the MCU chip performs addressing and transmission of control information, data information, respectively, to each PMIC chip according to a specific communication protocol. When transmitting data information, the MCU chip initializes the transmission of the data information once, and the MCU chip transmits communication data on the I2C_SDA line through the I2C protocol and simultaneously transmits clock information through the I2C_SCL line. The object and direction of data information transmission and the start and stop of information transmission are determined by the MCU chip. Thus, the MCU chip can control each PMIC chip, thereby controlling the states of each group of power rail signals output to each SOC chip.

The unique address of the PMIC chip may be set in different ways. For example, the unique address of each PMIC chip in the power supply system may be set by an internal register of the PMIC chip or by an external resistor of the PMIC chip.

In one embodiment, the unique address of the at least one PMIC chip is written in an internal register of the at least one PMIC chip, and the MCU chip is further configured to obtain the unique address of the at least one PMIC chip by reading the unique address written in the internal register of the at least one PMIC chip.

For example, referring to Table 1 below, the unique address of the PMIC chip may be written in the internal register of the PMIC chip by OTP_I2C_ADD [2:0] listed below:

OTP_I2C_ADD[2:0]	Unique address of PMIC chip
		000	0x08h
001	0x09h
		010	0x0Ah
011	0x0Bh
		100	0x0Ch
101	0x0Dh
		110	0x0Eh
111	0x0Fh

Table 1: unique address configuration list of PMIC chips written in internal registers

In the above table 2, 8 available unique addresses are set, however, it is to be understood that the numbers of the respective unique addresses of the PMIC chips and the total number of available unique addresses of 8 in the above table are merely examples, and different numbers may be set, or more or less available unique addresses may be set, as necessary.

In one embodiment, the unique address of the at least one PMIC chip is represented by a resistance value of an external resistor of the at least one PMIC chip, and the MCU chip is further configured to obtain the unique address of the at least one PMIC chip by reading the resistance value of the external resistor of the at least one PMIC chip.

For example, referring to fig. 5, the unique address of a PMIC chip may be represented by externally connecting two resistors to one PMIC chip, and by setting the resistance value of the resistor. Wherein, the unique address of the PMIC chip 1 is represented by the resistance values of the external resistors R11 and R12; the unique address of the PMIC chip 2 is represented by the resistance values of its external resistors R21 and R22; the unique address of the PMIC chip 3 is represented by the resistance values of its external resistors R31 and R32; the unique address of the PMIC chip n is represented by the resistance values of its external resistances Rn1 and Rn 2. The following table 2 shows that the two external resistors take the unique addresses of the PMIC chip represented by the different resistance values as follows:

Rn1(KΩ)	Rn2(KΩ)	Unique address of PMIC chip
			4.7	10	0x08h
4.7	15	0x09h
			4.7	20	0x0Ah
4.7	25	0x0Bh
			10	10	0x0Ch
10	15	0x0Dh
			10	20	0x0Eh
10	25	0x0Fh

Table 2: unique address configuration list of PMIC chip set through two external resistors

Wherein Rn1 and Rn2 represent resistance values of two resistors externally connected with any nth PMIC chip. The voltage division ADC inside the PMIC chip can recognize different resistance values through voltage variation, thereby obtaining a corresponding unique address.

In table 2 above, 8 available unique addresses are set so that the MCU chip can be supported to control up to 8 PMIC chips to service up to 8 SOC chips, with each SOC chip assuming a single PMIC chip to output a set of power rail signals thereto. It should be noted that in the case where each SOC chip uses multiple PMIC sub-chips to afford to output a set of power rail signals thereto, each PMIC sub-chip needs to be assigned a unique address to support addressing of each PMIC sub-chip. Thus, where each SOC chip uses two PMIC sub-chips to afford to output a set of power rail signals thereto, the MCU chip may be supported to control up to 4 pairs of PMIC sub-chips to serve up to 4 SOC chips. This can meet the use requirements of most ADAS systems.

It will be appreciated that the numbers of the individual unique addresses of the PMIC chips and the total number of available unique addresses in the above table are only examples, and that different numbers may be set, or more or fewer available unique addresses may be set, as desired. In addition, the number of resistors externally connected to one PMIC chip is two, which is also merely an example, and the unique address of the PMIC chip may be set by more or only one external resistor.

Taking the communication line between the MCU chip and the PMIC chip as an I2C bus as an example, the MCU chip immediately transmits an addressing byte after transmitting a start signal, and all PMIC chips on the I2C bus compare the 7-bit address in the addressing byte transmitted by the MCU chip with the unique address thereof. If the two are the same, the PMIC chip considers itself to be the PMIC chip addressed by the MCU chip, at this time, the selected PMIC chip automatically transmits a response signal, and the selected PMIC chip determines whether itself is used as a transmitter or a receiver according to a direction bit (D0 bit).

Because a plurality of SOC chips of the ADAS system can be connected with a large number of vehicle-mounted sensor devices, the large number of vehicle-mounted sensors bring mass data transmission and data processing, and a plurality of SOC chips need to carry out algorithm operation with a large number of tasks when processing the mass data, the consumed electric energy is also dynamically changed. This requires that the power rails of the PMIC chip be able to respond in real time to the dynamically changing power demands of the corresponding SOC chip. Moreover, for vehicle-mounted products, the real-time requirement is extremely high, and if the communication between the MCU chip and the PMIC chip is only dependent on the I2C bus, the data transmission and response requirements of the dynamic change electric energy of the SOC chip are difficult to meet.

In order to achieve fast data transmission of the PMIC chip to the SOC chip, in one embodiment, the MCU chip is further connected to a corresponding one of the PMIC chips via a corresponding set of fast port control signal lines, respectively. The MCU chip is further configured to be capable of transmitting a preset one of the quick port control signals to the connected one of the PMIC chips via each of the set of quick port control signal lines to enable a corresponding control operation of the one of the PMIC chips. In one embodiment, the set of fast-port control signals that can be sent via the set of fast-port control signal lines is selected from one or more of the following: a power enable signal, a low power control signal, a reset control signal, a watchdog control signal, and a power rail switching signal.

In order to achieve fast data feedback of the SOC chip to the PMIC chip, in one embodiment, the MCU chip is also connected to a corresponding one of the PMIC chips via a corresponding set of fast port feedback signal lines, respectively. The MCU chip is further configured to be capable of receiving a predetermined one of the fast port feedback signals from the connected one of the PMIC chips via each of the set of fast port feedback signal lines to obtain corresponding feedback information of the one of the PMIC chips. In one embodiment, the set of fast-port feedback signals that can be received via the set of fast-port feedback signal lines is selected from one or more of: the power supply normal output signal, the power supply fluctuation alarm signal, the power supply rail switching interrupt signal, the power supply threshold overrun signal and the power supply temperature control alarm signal.

In the above embodiment, through the fast port control/feedback signal line established between the MCU chip and the PMIC chip, the fast signal transmission and feedback between the MCU chip and the PMIC chip are realized, and a perfect power control mechanism may be established, when a plurality of SOC chips work, the MCU chip may effectively control the voltage fluctuation (rising/falling) condition of each power rail signal by monitoring the state of the power rail signal output by each PMIC chip in real time, and adopt the anti-failure program inside the MCU chip to solve various power rail problems such as power collapse, power abnormal fluctuation, dynamic power response, etc. that may occur in real time.

For example, referring to fig. 7, an example of a set of fast-port control signal lines and a set of fast-port feedback signal lines provided between the MCU chip and the PMIC chip 1 is shown in fig. 7. In fig. 7, when the MCU chip controls the PMIC chip 1, in addition to the internal registers of the PMIC chip 1 may be controlled using the I2C interface, a plurality of fast-port signal lines for guaranteeing a dynamic change power demand in response to the PMIC chip 1 are reserved for use, including a set of fast-port control signal lines for supporting transmission of fast-port control signals by the MCU chip to the PMIC chip 1 and a set of fast-port feedback signal lines for supporting transmission of fast-port feedback signals by the PMIC chip 1 to the MCU chip, for example, when an abnormal state of power supply occurs.

Wherein the set of fast port control signal lines comprises: a power supply enable signal 1 line, a low power consumption control signal 1 line, a reset control signal 1 line, a watchdog control signal 1 line, and a power supply rail switching signal 1 line. Accordingly, each line in the set of fast port control signal lines respectively supports the fast port control signals for transmission, including: a power supply enabling signal 1, a low power consumption control signal 1, a reset control signal 1, a watchdog control signal 1 and a power rail switching signal 1. The function examples of the respective fast port control signals are as follows: the power enable signal 1 represents a control signal for starting or stopping the operation of the PMIC chip 1 by the MCU chip, and when the signal is at a high level, the PMIC chip 1 starts to operate; when the signal is at low level, the PMIC chip 1 stops operating. The low-power consumption control signal 1 indicates whether the MCU chip starts or stops the PMIC chip 1 to enter a low-power consumption working mode control signal, when the signal is in a high level, the PMIC chip 1 enters the low-power consumption working mode to work, and is mainly used for keeping the lowest power consumption state after the automobile is flameout, most of functions of an ADAS system are not operated; when the signal is at a low level, the PMIC chip 1 exits the low power consumption operation mode. The reset control signal 1 indicates whether the MCU chip needs to reset and start the PMIC chip 1, and when the signal is a low level to high level change, the PMIC chip 1 is restarted. When the PMIC chip 1 is in an abnormal working state, the MCU chip resets and starts the PMIC chip 1. The watchdog control signal 1 represents a heartbeat signal output from the MCU chip to the PMIC chip 1, typically a PWM wave signal having a frequency of 20 hz. The power rail switching signal 1 represents a signal of change of a power rail output by the MCU chip to the PMIC chip 1, and when the signal is in a high level, the power rail of the PMIC chip 1 works for the SOC chip 1; when the signal is low, the power rail of the PMIC chip 1 works for the SOC chip 2.

Wherein the set of fast port feedback signal lines comprises: the power supply normal output signal 1 circuit, the power supply fluctuation alarm signal 1 circuit, the power supply rail switching interruption signal 1 circuit, the power supply threshold overrun signal 1 circuit and the power supply temperature control alarm signal 1 circuit. Accordingly, each line of the set of fast port feedback signal lines respectively supports the fast port feedback signals for transmission including: the power supply normal output signal 1, the power supply fluctuation alarm signal 1, the power supply rail switching interruption signal 1, the power supply threshold overrun signal 1 and the power supply temperature control alarm signal 1. The function examples of the respective fast-port feedback signals are as follows: the power normal output signal 1 represents a signal indicating whether or not the state of all output power rails of the PMIC chip 1 is normal at present. When the power normal output signal 1 is at a high level, it indicates that the state of all output power rails of the PMIC chip 1 is normal at present; when the power normal output signal 1 is at a low level, the state of the power rail of a certain phase of the PMIC chip 1 is abnormal, and the MCU chip is required to process immediately. The power fluctuation warning signal 1 indicates whether an unstable state exists in the output power rail of the PMIC chip 1. When the power normal output signal 1 is at a high level, it indicates that the state of all output power rails of the PMIC chip 1 is normal at present; when the power normal output signal 1 is at a low level, it indicates that the state of a certain phase of power rail of the PMIC chip 1 is fluctuated, but the power fluctuation is that the PMIC chip 1 can process by itself, and only the current power fluctuation is uploaded to the MCU chip for state preservation. The power rail switching interrupt signal 1 indicates whether the PMIC chip 1 has completed the power rail switching operation according to the control of the MCU chip. When the power rail switching interrupt signal 1 is at a high level, the PMIC chip 1 is indicated to have completed the power rail switching operation; when the power rail switching interrupt signal 1 is at a low level, it indicates that the PMIC chip 1 has not completed the power rail switching operation. The power threshold overrun signal 1 indicates whether the state of all output power rails of the PMIC chip 1 at present has the condition that the over-voltage exceeds a set threshold value, and when the power threshold overrun signal 1 is at a high level, the state of all output power rails of the PMIC chip 1 at present is normal; when the power threshold overrun signal 1 is at a low level, it indicates that the power supply rail of a certain phase has an over-voltage exceeding a set threshold value at present in the PMIC chip 1, and the MCU chip is required to immediately process. The power supply temperature control alarm signal 1 indicates whether the current temperature of the PMIC chip 1 exceeds the threshold set by the chip. When the power supply temperature control alarm signal 1 is at a high level, the current chip temperature of the PMIC chip 1 is indicated to be normal; when the power supply temperature control alarm signal 1 is at a low level, the current chip temperature of the PMIC chip 1 is abnormal, and the MCU chip is required to process immediately.

In the same manner as above, a set of fast-port control signal lines and/or a set of fast-port feedback signal lines may be respectively disposed between the MCU chip and the PMIC chip 2, and between … … and the PMIC chip 3, and between the PMIC chip n, for transmitting and/or receiving the fast-port control/feedback signals, which will not be described herein. It will be appreciated that the above set of fast-port control signal lines and/or the set of fast-port feedback signal lines are merely examples of the types and numbers of signals that may be varied as desired.

Through the quick port control/feedback signal lines, the MCU chip can check the working state of the PMIC chip in time and respond to the request of the PMIC chip in real time. The method comprises the steps of feeding back to the MCU chip in time when various anomalies of the PMIC chip occur and processing the anomalies in time by the MCU chip.

Because the ADAS system is mounted on an automobile, and the working environment of the automobile is very different and possibly very severe, the PMIC chip of the ADAS system needs to face the corresponding working environment when working, including, for example, external temperature changes, mass data transmission, various unusual vibrations, etc., which may occur, in which case the PMIC chip may not work due to an abnormal state.

In view of the above, the present application may also provide a system in which a plurality of PMIC chips are used to connect one SOC chip correspondingly, so as to perform PMIC chip redundancy redundant power supply on the SOC chip. By connecting one SOC chip with a plurality of PMIC chips for redundant power supply, one PMIC chip can be used for supplying power to the SOC chip by default, and when the PMIC chip which supplies power to the SOC chip at present is abnormal, the connected other PMIC chip can be switched to continue power supply to the SOC chip, so that the problem that the SOC chip cannot work normally due to abnormal power supply of the PMIC chip is avoided. By way of example, redundant power supply of one SOC chip by a plurality of PMIC chips may be set in the following two ways.

In one embodiment, in the first redundant power supply mode, at least one first SOC chip of the plurality of SOC chips is connected to the MCU chip via M PMIC chips dedicated to the first SOC chip; wherein M is a positive integer and M is more than or equal to 2. The MCU chip is configured to: determining a second PMIC chip other than the first PMIC chip from the M PMIC chips when a first PMIC chip power supply abnormality of the M PMIC chips that is supplying power to the first SOC chip is detected; and interrupting the power supply of the first PMIC chip to the first SOC chip, and starting the power supply of the second PMIC chip to the first SOC chip.

For example, referring to fig. 8, the MCU chip may be connected to the SOC chip 1 via the PMIC chip 1 and the PMIC chip 11, respectively, wherein the PMIC chip 1 is connected to the SOC chip 1 via a set of power rail signal lines, and the PMIC chip 11 is connected to the SOC chip 1 via a set of power rail signal lines, and both the PMIC chip 1 and the PMIC chip 11 may be dedicated to power the SOC chip 1, i.e., the SOC chip 1 is connected to the MCU chip via the PMIC chip 1 and the PMIC chip 11 dedicated to the SOC chip 1. Normally, the power supply to the SOC chip 1 may be defaulted by the PMIC chip 1, while the PMIC chip 11 is idle, and when the power supply to the PMIC chip 1 is abnormal, the MCU chip may control switching to the PMIC chip 11 to supply the power to the SOC chip 1. Similarly, the MCU chip may be connected to the SOC chip 2 via the PMIC chip 2 and the PMIC chip 21, respectively, and perform redundant power supply of the first redundant power supply mode to the SOC chip 2, which will not be described herein.

In one embodiment, in the second redundant power supply mode, at least one group of N SOC chips among the plurality of SOC chips is all connected to the MCU chip via P PMIC chips shared among the N SOC chips, wherein power-on parameters of the N SOC chips are identical to each other; n, P is a positive integer, N is not less than 2, and P is not less than 2. The MCU chip is configured to: when detecting that the third PMIC chip of the P PMIC chips which are supplying power to the second SOC chip of the N PMIC chips is abnormal, determining a fourth PMIC chip which is supplying power to the third SOC chip of the N PMIC chips except the third PMIC chip from the P PMIC chips, interrupting the power supply of the third PMIC chip to the second SOC chip, and causing the fourth PMIC chip to supply power to the second SOC chip while maintaining the power supply of the fourth PMIC chip to the third SOC chip.

Wherein, P PMIC chips are respectively connected to the MCU chip, and the N SOC chips and the P PMIC chips form full connection, wherein the full connection means that each SOC chip in the N SOC chips is respectively connected with the P PMIC chips. For example, referring to fig. 9, the power-on parameters of the SOC chip 1 and the SOC chip 2 are the same, and thus, the SOC chip 1 and the SOC chip 2 may share the same set of power rail signal lines. In fig. 9, the PMIC chip 1 is connected to the SOC chip 1 via a set of power rail signal lines, and the PMIC chip 1 is connected to the SOC chip 2 via a set of power rail signal lines, the PMIC chip 2 is connected to the SOC chip 1 via a set of power rail signal lines, and the PMIC chip 2 is connected to the SOC chip 2 via a set of power rail signal lines, that is, the SOC chip 1 and the SOC chip 2 are all connected to the MCU chip via the PMIC chip 1 and the PMIC chip 2 shared between the SOC chip 1 and the SOC chip 2. Under normal conditions, the PMIC chip 1 can supply power to the SOC chip 1 by default, and the PMIC chip 2 supplies power to the SOC chip 2, when the PMIC chip 1 is abnormal in power supply, the PMIC chip 1 can immediately alarm to the MCU chip through the power threshold overrun signal 1 or the power temperature control alarm signal 1, and the power normal output signal 1 also becomes low level, the MCU chip can timely respond to the alarm of the PMIC chip 1, and immediately interrupt the power supply of the PMIC chip 1 through the power rail switching signal 2, so that the PMIC chip 2 can supply power to the SOC chip 1 simultaneously while the PMIC chip 2 is kept supplying power to the SOC chip 2. When the PMIC chip 2 completes the switching of the power supply rail, after the power supply to the SOC chip 1 is already provided, the MCU chip is informed through the power supply rail switching interrupt 2, which indicates that the PMIC chip 2 has completed the power supply rail switching action according to the control of the MCU chip. At this time, the MCU chip turns off the PMIC chip 1 by the power enable signal 1, confirms the reason why the PMIC chip 1 cannot operate, and performs the subsequent processing. Thus, the MCU chip completes the switching task of the power rails of the PMIC chip 1 and the PMIC chip 2, ensures uninterrupted power supply of the SOC chip 1, and maintains the stability of the whole power system. Similarly, the MCU chip may be fully connected to the SOC chip 3 and the SOC chip n via the PMIC chip 3 and the PMIC chip n, and perform redundant power supply of the second redundant power supply manner to the SOC chip 3 and the SOC chip n, which will not be described herein.

It can be appreciated that in other embodiments, only one of the above redundant power supply modes may be used in the system, or both of the above two redundant power supply modes may be used, so as to flexibly set redundant power supply to each SOC chip according to the type, number, power supply requirement, and the like of the SOC chips included in the system.

Referring to fig. 10, the present application further provides a vehicle, where the vehicle may include the power supply system, the plurality of SOC chips, and the plurality of vehicle-mounted sensors according to any of the embodiments described above, the power supply system is connected to the plurality of SOC chips for supplying power to the plurality of SOC chips, and the plurality of SOC chips are connected to the plurality of vehicle-mounted sensors. The power supply system may be included in an on-board ADAS system, for example, the vehicle may include an ADAS system including the power supply system, the plurality of SOC chips, and the plurality of on-board sensors described above. Each SOC chip is respectively connected with a group of a plurality of sensors so as to control the sensors and collect data. It will be appreciated that the number and types of sensors to which each SOC chip is connected may be the same or different from one another, which may be flexibly altered depending on the application requirements. The in-vehicle sensor may be any suitable sensor for sensing information inside and outside the vehicle, such as ultrasonic radar, millimeter wave radar, lidar, single/dual camera and/or satellite navigation systems, and the like.

The application also provides a power supply method which can be applied to the power supply system in any embodiment, wherein the power supply system is used for supplying power to a plurality of SOC chips, the power supply system comprises an MCU chip and a plurality of PMIC chips, and each of the plurality of SOC chips is connected with the MCU chip through at least one corresponding PMIC chip. As shown in fig. 11, the method may include:

S100, when the MCU chip is electrified, the electrifying parameters of a group of power rail signals corresponding to each SOC chip are written into a PMIC chip corresponding to each SOC chip; the power-on parameters comprise power-on time sequence and voltage level of each power rail signal in the group of power rail signals;

S110, when each PMIC chip receives the power-on parameters of a group of power rail signals from the MCU chip, the group of power rail signals with voltage levels are output to a corresponding connected SOC chip according to the power-on time sequence to supply power to the SOC chip.

In other embodiments, the method may further include the steps performed by the various components described in the power supply system of any of the embodiments above.

In one embodiment, the method may further comprise the steps performed in the aforementioned mains power supply system of:

after all the plurality of SOC chips have been powered up and started normally, execute:

s210, each PMIC chip monitors fluctuation of a group of power rail signals output by the PMIC chip and adjusts the output group of power rail signals according to load consumption of the SOC chip supplied by the PMIC chip;

S220, each PMIC chip regularly judges whether the PMIC chip can successfully meet the signal output requirement of a group of power rails of the SOC chip supplied with power by the PMIC chip, and when judging that the PMIC chip can meet the signal output requirement, the PMIC chip returns to the step S210, and when judging that the PMIC chip cannot meet the signal output requirement, the PMIC chip executes the step S230;

S230, the PMIC chip reports the self-adjustment condition of the power rail signal to the MCU chip, and the MCU chip adjusts the internal parameters of the PMIC chip according to the adjustment condition of the power rail signal reported by the PMIC chip so that the PMIC chip successfully meets the power rail signal output requirement of the SOC chip.

S240, after adjusting the internal parameters of the PMIC chip, the PMIC chip again judges whether the PMIC chip can successfully meet the signal output requirement of a group of power rails of the SOC chip supplied by the PMIC chip, when judging that the PMIC chip can meet the signal output requirement, the step S210 is returned, and when judging that the PMIC chip cannot meet the signal output requirement, a power supply abnormality processing flow is executed to process and eliminate the power supply abnormality.

Further, in combination with the above embodiments, in a specific example, as shown in fig. 12, an example power supply method of the present application may include the steps of:

Step S1, the hardware of the power supply system is electrified, and the MCU chip is started and self-checking initialization is carried out.

When the power supply system is included in an ADAS system, power-up of the power supply system hardware can be achieved by, for example, power-up of the ADAS system. The self-checking initialization of the MCU chip comprises the following steps: initializing an internal clock of an MCU chip; closing the MCU chip watchdog; establishing an interrupt vector table configured by an internal register of the MCU chip; initializing an MCU chip stack register; initializing a memory FLASH of the MCU chip; initializing (clearing) the ZI domain; initializing a stack pointer; and initializing a C library environment, wherein the C library environment comprises memory space required by a C library, resources required by program execution and C library initialization. The MCU chip starts running program from the internal FLASH initial address segment, the self-checking initialization succeeds in the next step, the self-checking is unsuccessful to enter the power supply exception handling flow 1, the reason for the unsuccessful self-checking initialization is found out, and whether restarting is needed is judged according to the actual reason.

And S2, the MCU chip establishes handshake connection with each PMIC chip according to the address list.

The MCU chip may use the I2C bus to establish handshake connection with the PMIC chip 1, the PMIC chip 2, the MIC chip 3, the PMIC chip n and the like according to the unique address list in table 1 or table 2, and the connection is successful and continues to the next step, and the connection is unsuccessful to enter the power exception handling flow 2, so as to find out the reason why the handshake connection between the MCU chip and the PMIC chip is unsuccessful, and determine whether to perform handshake connection again according to the actual reason.

Step S3, the MCU chip enters the control program of each PMIC chip.

It should be noted here that if the PMIC chips controlled by the MCU chip are all identical output power rails, the control procedure is identical, and if the PMIC chips controlled by the MCU chip have different output power rails, the control procedure is inconsistent.

And S4, the MCU chips respectively control each PMIC chip to carry out safety self-inspection.

The MCU chip uses the I2C bus to sequentially communicate with the PMIC chip 1, the PMIC chip 2, the PMIC chip 3 and the PMIC chip n according to the unique address list of the table 1 or the table 2 and controls the PMIC chip to carry out safety self-checking. The secure self-test of the PMIC chip comprises: the input power supply detects whether the input power supply is within the range, whether the internal register parameters of the PMIC power supply chip are opened, whether each output power supply has short circuit, disconnection problems and the like. And the self-checking is successful and continues to the next step, the self-checking is unsuccessful and enters the power supply abnormality processing flow 3, the MCU chip finds out the reason of the unsuccessful self-checking of the PMIC chip, and judges whether the self-checking of the PMIC chip needs to be carried out again according to the actual reason.

And S5, the MCU chips respectively set starting parameters of the PMIC chips.

The MCU chip sets starting parameters of the PMIC chips in each PMIC chip sequentially through write commands of the I2C bus according to the unique address list of the table 1 or the table 2, wherein the starting parameters comprise values written into each function register of the PMIC chip and power-on parameters of a group of power rail signals of the corresponding SOC chip.

And S6, the MCU chip judges whether the starting parameters of each PMIC chip are successfully set.

The MCU chip acquires the starting parameters of the PMIC chip sequentially through the read command of the I2C bus, and confirms whether the read parameter value is consistent with the starting parameters written in the last step, so as to judge whether the starting parameters written in the PMIC chip are successful. If the next step is successful, if the startup parameters written into the PMIC chip by the MCU chip are unsuccessful, the power supply exception processing flow 4 is entered, the MCU chip finds out the reason that the startup parameters written into the PMIC chip are unsuccessful, and the MCU chip judges whether the startup parameters of the PMIC chip need to be rewritten according to the actual reason.

And S7, each PMIC chip outputs a group of power rail signals to the corresponding SOC chip according to the power-on time sequence according to the starting parameters set by the MCU chip.

Each PMIC chip outputs each path of power supply voltage value of a group of power supply rail signals to the corresponding SOC chip according to the starting parameters set by the MCU chip and the power-on time sequence requirement defined by the starting parameters so as to ensure that the SOC chip obtains the correct power supply rail signal power-on time sequence. For example, for SOC chip 1, pmic chip 1 may output vddio_sdio1, vddio_soc1, USB20_vdd1, DDR0_vdd1/DDR1_vdd1, mipi_vph1, mipi_vp1, rst_n1 signals to SOC chip 1 in order of the power-on timing and level shown in fig. 2. Different conditions may occur to the power-on time sequences of different SOC chips, but the MCU chip single-chip microcomputer can be independently matched and set so as to meet the requirements of power rails of different SOC chips.

Step S8, whether the SOC chip is successfully and normally started or not is confirmed.

After each PMIC chip completes outputting the power rail signal to the SOC chip according to the power-on sequence, including outputting the RST_N1 signal (i.e., the RESET RESET signal) to the SOC chip at last, the SOC chip is started when receiving the RESET RESET signal. If the SOC chip is started successfully, a timing heartbeat signal is sent to the MCU chip, connection with the MCU chip is established, if the MCU chip is started successfully and continues to the next step, if the power supply abnormality processing flow 5 is not started successfully, the MCU chip sends a starting command to the PMIC chip corresponding to the not-started SOC chip again, the PMIC chip corresponding to the command outputs a power supply rail signal again according to the power-on time sequence, if heartbeat data of the SOC chip cannot be obtained, the SOC chip starts the abnormality flow, and whether the SOC chip needs to be restarted is judged according to practical reasons.

Step S9, the MCU chip starts a monitoring program for the PMIC output power rail signal.

The MCU chip can regularly use the I2C bus to sequentially communicate with the PMIC chip 1, the PMIC chip 2, the PMIC chip 3 and the PMIC chip n, and regularly read the numerical value of the real-time output power rail signal of the PMIC to confirm whether the numerical value of the real-time output power rail signal is consistent with the numerical value of a preset power rail signal.

Step S10, the MCU chip starts a deadlock prevention program for the PMIC output power rail.

When the MCU chip detects that the I2C bus is pulled down to be low level for a preset time, namely the I2C bus is found to be pulled down for a period of time, the control on the I2C bus is automatically released. And adding an I2C bus recovery program in the MCU chip program.

Among them, the so-called deadlock is represented by that, when the MCU chip performs a write operation on the PMIC chip, the MCU chip controls the i2c_scl signal to generate a predetermined number (for example, 8 in this example) of clock pulses after generating the start signal, and then pulls down the i2c_scl signal to a low level, at this time, the PMIC chip outputs a response signal and pulls the i2c_sda signal to a low level. If the MCU chip is abnormally reset at this time, the I2C_SCL is released to the high level. At this time, if the PMIC chip is not reset, the I2C bus is continued to respond, the i2c_sda is pulled low until the i2c_scl becomes low, and the response signal is terminated. For the MCU chip, the i2c_scl signal and the i2c_sda signal are detected after reset, if the MCU chip finds that the i2c_sda signal is at a low level, the MCU chip considers that the I2C bus is occupied, and the MCU chip waits for the i2c_scl signal and the i2c_sda signal to become at a high level all the time. Thus, the MCU chip waits for the PMIC chip to release the I2C_SDA signal, and at the same time, the PMIC chip waits for the MCU chip to pull the I2C_SCL signal low to release the response signal, and the MCU chip and the PMIC chip wait for each other, so that the I2C bus may enter a bus data transmission abnormal deadlock state. Similarly, when the MCU chip performs a read operation on the PMIC chip, the PMIC chip outputs data after responding, and if the MCU chip is abnormally reset at the moment, the data bit output by the PMIC chip is exactly 0 at the moment, the I2C bus can be caused to enter a bus data transmission abnormal deadlock state.

In order to solve the problem that abnormal deadlock of data transmission may occur, the MCU chip may add an anti-deadlock function to a program for the PMIC chip, and the anti-deadlock function may be implemented in the following two aspects.

In a first aspect, when the MCU chip finds that the I2C bus (e.g., I2C_SDA in the I2C bus) is pulled low for a predetermined period of time, then control of the I2C bus is automatically released (e.g., released high). The predetermined time period may be set according to practical situations, for example, may be determined according to system test data or historical operation data, and when the I2C bus is pulled down to a low level, the time period during which abnormal deadlock occurs with a high probability is long, and it is understood that the predetermined time period should be appropriately longer than a normal time period required after the I2C bus is pulled down until the I2C bus is pulled up in normal operation, so as to avoid unnecessary interruption to normal operation. Therefore, when the I2C bus is found to be pulled down for too long, the MCU chip can timely release the control of the I2C bus so as to inhibit the occurrence of abnormal deadlock.

In a second aspect, an I2C bus resume procedure may be added to the MCU chip procedure. After each reset of the MCU chip, if i2c_sda is detected to be pulled low, i2c_scl is controlled to generate a predetermined number of clock pulses (which may be determined according to the number of data bits, for example, in the case of 8-bit data, the predetermined number is < = 9 clock pulses) and whether i2c_sda is released is monitored (for example, whether i2c_sda is released is detected every time one clock pulse is transmitted), and a stop signal is again simulated to be generated if i2c_sda is detected to have been released. Thus, the PMIC chip can complete the suspended read-write operation and recover from the abnormal deadlock state of data transmission.

It will be appreciated that the MCU chip may have the functions of one or both of the above aspects to inhibit the occurrence of abnormal deadlock conditions of data transfer and/or to facilitate a quick recovery from possible abnormal deadlock conditions of data transfer.

Step S11, judging whether all the SOC chips in the system are started normally.

The MCU chip judges whether all the plurality of SOC chips connected in the system are normally started or not, if the next step is successfully continued, the ADAS system successfully enters a normal working state and starts to process various sensor data, the MCU chip enters an automatic monitoring state and starts to protect the safe operation of a power rail of the whole system, and if the automatic monitoring state is started to enter a power abnormality processing flow 6, the ADAS system needs the cooperation of the plurality of SOC chips, the automatic monitoring system comprises power modules, sensor modules and the like, the MCU chip can only judge according to the abnormality of the power system, find out the reason of the unsuccessful starting of the ADAS system, and judge whether the plurality of SOC chips of the ADAS system need to be restarted according to the actual reason.

Step S12, the system enters a normal operation state and starts processing various sensor data.

At this time, the MCU chip enters an automatic monitoring state to start to protect the safe operation of the power rail of the whole system.

In step S13, the PMIC chip monitors fluctuation of the output power rail signal, and the PMIC automatically adjusts the output power rail signal according to the load consumption of the SOC chip.

When a plurality of SOC chips process various sensor data, the operation and analysis of mass data can be carried out, the SOC chips can carry out calculation power promotion to meet various data operation and analysis, and in the calculation power promotion process, the power load consumption of the SOC chips can be changed continuously, so that continuous fluctuation of a power rail is generated. In this step, the PMIC chip automatically monitors fluctuation of the power rail signal outputted from itself, and the PMIC chip automatically adjusts the power rail signal outputted from the PMIC chip according to load consumption of the power rail signal of the SOC chip. The MCU chip can control the PMIC chips to establish a perfect power control mechanism, when the SOC chips work, the MCU chip can effectively control the voltage fluctuation (rising/falling) condition of each power rail signal by monitoring the power rail signal state of each PMIC chip in real time, and various power rail problems of power collapse, power abnormal fluctuation and dynamic power response which possibly occur are solved in real time by adopting an anti-failure program inside the MCU chip.

The PMIC chip adopts a remote power supply rail feedback scheme, and a power supply feedback differential resistor is added and a remote feedback differential PCB wiring is used, so that a feedback end network sampling point of a power supply is directly set to a power supply load end, a voltage division value obtained by sampling an FB pin of the chip can be matched with a voltage value of the power supply load end, and even if a voltage difference occurs between the power supply output end and the power supply load end, the voltage value of the power supply output end can be dynamically ensured to be a required voltage value by adjusting the voltage value of the power supply output end in real time.

Step S14, the PMIC chip judges whether the PMIC chip can successfully meet the power rail signal output requirement of the SOC chip.

The PMIC chip can adjust the output of the power rail signal to cope with the power load consumption of the SOC chip and the fluctuation of the power rail signal, monitors whether the adjustment of the output of the power rail signal by the PMIC chip can successfully meet the output requirement of the power rail signal of the SOC chip in real time, and returns to the step S13 to continuously monitor and adjust the output power rail signal if the adjustment is successfully met; if not, proceeding to the next step.

And S15, the PMIC chip reports the adjustment condition of the PMIC chip to the power rail signal to the MCU chip.

The PMIC chip reports the adjustment condition of the PMIC chip to the power rail signal to the MCU chip through the I2C bus.

And S16, the MCU chip adjusts the internal parameters of the PMIC chip according to the adjustment condition of the power rail signal reported by the PMIC chip so that the PMIC chip can successfully meet the power rail signal output requirement of the SOC chip.

The MCU chip records the adjustment condition of the power rail signal reported by the PMIC chip, and dynamically adjusts the internal parameters of the PMIC chip through the I2C bus according to the adjustment condition of the power rail signal reported by the PMIC chip so as to adjust the output of the power rail signal of the PMIC chip, so that the adjusted PMIC chip can successfully meet the power rail signal output requirement of the SOC chip through the adjustment of the output of the power rail signal. Of course, this adjustment is minor and does not result in abnormal operation of the SOC chip.

Step S17, judging whether the PMIC chip can successfully meet the power rail requirement of the SOC after adjusting the internal parameters of the PMIC chip.

After the internal parameters of the PMIC chip are adjusted, whether the power rail signal re-output by the PMIC chip can meet the power rail signal requirement of the SOC chip is judged again, if so, the operation is returned to the step S13 again, if not, the power abnormality processing flow 7 is entered, so far, the whole MCU chip and the PMIC chip enter the working cycle from the step S13 to the step S17, and as long as the operation is not abnormal, the operation is always operated, so that the normal operation of the SOC chip is ensured.

Through the program flow, the MCU chip can reasonably control the PMIC chips to output power rail signals so as to supply power to the SOC chips and enable the SOC chips to work normally. A perfect power control mechanism can be established by controlling a plurality of PMIC chips through the MCU chip, when a plurality of SOC chips work, the MCU chip can effectively control the voltage fluctuation (rising/falling) condition of each power rail through monitoring the power rail state of each PMIC chip in real time, and various power rail problems of power collapse, abnormal fluctuation of power and dynamic power response which possibly occur are solved in real time by adopting an anti-failure program inside the MCU chip.

It should be understood that, although the steps in the flowchart are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or other steps.

As shown in fig. 13, the present application further provides a power supply apparatus 1300, applied to a power supply system, where the power supply system is used for supplying power to a plurality of SOC chips, the power supply system includes an MCU chip and a plurality of PMIC chips, and each SOC chip in the plurality of SOC chips is connected to the MCU chip via a corresponding at least one PMIC chip, the apparatus 1200 includes:

The MCU chip control module 1310 is configured to enable the MCU chip to write, when power is applied, power-on parameters of a set of power rail signals corresponding to each SOC chip into a PMIC chip corresponding to each SOC chip; the power-on parameters comprise power-on time sequence and voltage level of each power rail signal in the group of power rail signals;

The PMIC chip control module 1320 is configured to enable each PMIC chip to output a set of power rail signals having a voltage level to a corresponding one of the connected SOC chips according to a power-up timing when power-up parameters of the set of power rail signals are received from the MCU chip to supply power to the SOC chip.

For specific limitations of the power supply device, reference may be made to the above limitations of the power supply method, and no further description is given here. The above-described respective modules in the power supply device may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In an embodiment, a computer device is provided comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the method according to any of the embodiments above when the computer program is executed.

In one embodiment, a computer readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, implements the steps of the method as described in any of the embodiments above.

Terms such as MCU chip, PMIC chip, SOC chip, etc. are used in the present application, and these terms are not limited to the MCU chip, PMIC chip, SOC chip, etc. as generally known in the art, but should also cover other devices capable of equally performing functions similar to those of the components to which these terms refer. For example, the MCU chip of the present application may be a chip-level computer formed by properly reducing the frequency and specification of the cpu and integrating peripheral interfaces such as a memory, a counter (Timer), a USB, an a/D converter, UART, PLC, DMA, etc. on a single chip. However, other similar devices capable of performing equivalent functions to the above-described MCU chips of the present application should also be considered as falling within the scope of the MCU chips of the present application. For example, the functions of the MCU chip of the present application can be implemented using various other logic devices such as FPGA chips, CPLD chips, bridge chips, SOC chips, etc., and these alternatives are all within the scope of the MCU chip of the present application. For example, as for the PMIC chip, a vehicle-mounted data switch chip of a different name is adopted, and a vehicle-mounted data switch chip of a similar GMS port, MII port, RMII port, RGMII port, GMII port, SGMII port and other different interfaces is adopted. Also for example, for an SOC chip, it is possible to use other chips such as a CPU chip to connect the respective sensors instead of implementing the functions of the SOC chip, or it is also possible to use a large scale integrated circuit system of a plurality of SOCs in other systems of off-board applications, and such an alternative chip solution shall fall within the scope of the SOC chip of the present application.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (SYNCHLINK) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A power supply system for supplying power to a plurality of SOC chips, the power supply system comprising an MCU chip and a plurality of PMIC chips, and each of the plurality of SOC chips being connected to the MCU chip via a corresponding at least one PMIC chip, wherein,

The MCU chip is configured to: when power is on, the power-on parameters of a corresponding group of power rail signals of each SOC chip are written into a corresponding PMIC chip of each SOC chip; wherein the power-up parameters include a power-up timing and a voltage level of each power rail signal in the set of power rail signals;

Each of the PMIC chips is configured to: upon receiving a power-up parameter of a set of power rail signals from the MCU chip, outputting a set of power rail signals having the voltage level to a corresponding one of the connected SOC chips in accordance with the power-up timing to power the SOC chip.

2. The system of claim 1, wherein the MCU chips are connected to respective PMIC chips via an I2C bus, and each of the SOC chips is connected to a corresponding one of the PMIC chips via a corresponding set of power rail lines.

3. The system of claim 2, wherein at least one of the PMIC chips is comprised of a plurality of PMIC sub-chips that are respectively connected to the MCU chip via an I2C bus, and a corresponding set of power rail lines connected between the PMIC chip and the MCU chip are arranged in a dispersed manner between the plurality of PMIC sub-chips and the MCU chip.

4. The system of claim 1, wherein power-on parameters of at least two of the plurality of SOC chips are different from each other.

5. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

The MCU chip is further configured to: when power is turned off, a power-off instruction is sent to each PMIC chip which is supplying power to the SOC chip; and

Each of the PMIC chips is further configured to: and when the power-down instruction is received from the MCU chip, taking the reverse time sequence of the power-up time sequence as the power-down time sequence, and closing the output of the group of power rail signals to the corresponding SOC chip according to the power-down time sequence.

6. The system of claim 1, wherein each of the PMIC chips has a unique address, the MCU chip further configured to: addressing each of said PMIC chips with said unique address for each of said PMIC chips;

Wherein the unique address of at least one said PMIC chip is written in an internal register of the at least one said PMIC chip, and said MCU chip is further configured to acquire the unique address of the at least one said PMIC chip by reading the unique address written in the internal register of the at least one said PMIC chip.

7. The system of claim 1, wherein each of the PMIC chips has a unique address, the MCU chip further configured to: addressing each of said PMIC chips with said unique address for each of said PMIC chips;

Wherein the unique address of at least one of the PMIC chips is represented by a resistance value of an external resistor of the at least one of the PMIC chips, and the MCU chip is further configured to acquire the unique address of the at least one of the PMIC chips by reading the resistance value of the external resistor of the at least one of the PMIC chips.

8. The system of claim 2, wherein the MCU chips are further connected to a corresponding one of the PMIC chips via a corresponding set of fast-port control signal lines, respectively, and

The MCU chip is further configured to be capable of transmitting a preset one of the quick port control signals to the connected one of the PMIC chips via each of the set of quick port control signal lines to enable a corresponding control operation of the one of the PMIC chips.

9. The system of claim 2, wherein the MCU chips are further connected to a corresponding one of the PMIC chips via a corresponding set of fast-port feedback signal lines, respectively, and

The MCU chip is further configured to be capable of receiving a preset one of the fast port feedback signals from the connected one of the PMIC chips via each of the set of fast port feedback signal lines to obtain corresponding feedback information of the one of the PMIC chips.

10. The system of claim 1, wherein at least a first SOC chip of the plurality of SOC chips is connected to the MCU chip via M PMIC chips dedicated to the first SOC chip; m is more than or equal to 2;

The MCU chip is configured to: determining a second PMIC chip other than the first PMIC chip from among the M PMIC chips when a first PMIC chip power supply abnormality of the M PMIC chips that is supplying power to the first SOC chip is detected; and interrupting the power supply of the first PMIC chip to the first SOC chip, and starting the power supply of the second PMIC chip to the first SOC chip.

11. The system of claim 1, wherein at least one set of N SOC chips of the plurality of SOC chips is fully connected to the MCU chip via P PMIC chips shared among the N SOC chips, wherein power-on parameters of the N SOC chips are identical to each other; n is more than or equal to 2, and P is more than or equal to 2;

The MCU chip is configured to: when detecting that the third PMIC chip of the P PMIC chips which are supplying power to the second SOC chip of the N PMIC chips is abnormal, determining a fourth PMIC chip which is supplying power to the third SOC chip of the N SOC chips except the third PMIC chip from the P PMIC chips, interrupting the power supply of the third PMIC chip to the second SOC chip, and enabling the fourth PMIC chip to supply power to the second SOC chip while keeping the fourth PMIC chip supplying power to the third SOC chip.

12. A vehicle comprising the power supply system according to any one of claims 1 to 11, a plurality of SOC chips, and a plurality of in-vehicle sensors, the power supply system connecting the plurality of SOC chips for supplying power to the plurality of SOC chips, the plurality of SOC chips connecting the plurality of in-vehicle sensors.

13. The power supply method is applied to a power supply system for supplying power to a plurality of SOC chips, the power supply system comprises an MCU chip and a plurality of PMIC chips, each of the plurality of SOC chips is connected with the MCU chip through at least one corresponding PMIC chip, wherein,

The method comprises the following steps:

When the MCU chip is electrified, the electrifying parameters of a group of power rail signals corresponding to each SOC chip are written into a PMIC chip corresponding to each SOC chip; wherein the power-up parameters include a power-up timing and a voltage level of each power rail signal in the set of power rail signals;

When power-on parameters of a set of power rail signals are received from the MCU chips, the PMIC chips output the set of power rail signals with the voltage level to a corresponding one of the connected SOC chips according to the power-on time sequence so as to supply power to the SOC chips.

14. The method of claim 13, wherein the MCU chips are connected to respective PMIC chips via an I2C bus, and the method further comprises:

When the MCU chip detects that the I2C bus is pulled down to be low level for a preset time, the control on the I2C bus is automatically released; and/or

And after each time the MCU chip resets, if the I2C_SDA in the I2C bus is detected to be pulled down to be low level, controlling the I2C_SCL in the I2C bus to generate a preset number of clock pulses, monitoring whether the I2C_SDA is released, and if the I2C_SDA is detected to be released, simulating to generate a stop signal.

15. The method as recited in claim 13, further comprising:

after all of the plurality of SOC chips have been powered up and started up normally, execute:

each PMIC chip monitors fluctuation of a group of power rail signals output by the PMIC chip and adjusts the output group of power rail signals according to load consumption of the SOC chip supplied by the PMIC chip;

each PMIC chip regularly judges whether the PMIC chip can successfully meet the signal output requirement of a group of power rails of the SOC chip powered by the PMIC chip;

when any PMIC chip judges that the PMIC chip cannot successfully meet the output requirements of a group of power rail signals of the SOC chip supplied with power by the PMIC chip, the MCU chip reports the adjustment condition of the power rail signals by the PMIC chip, and the MCU chip adjusts the internal parameters of the PMIC chip according to the adjustment condition of the power rail signals reported by the PMIC chip so that the PMIC chip can successfully meet the output requirements of the power rail signals of the SOC chip.

16. A power supply device applied to a power supply system, wherein the power supply system is used for supplying power to a plurality of SOC chips, the power supply system comprises an MCU chip and a plurality of PMIC chips, and each SOC chip in the plurality of SOC chips is connected to the MCU chip via at least one PMIC chip corresponding thereto, the device comprising:

the MCU chip control module is used for enabling the MCU chip to write the power-on parameters of a group of power rail signals corresponding to each SOC chip into a PMIC chip corresponding to each SOC chip when the MCU chip is powered on; wherein the power-up parameters include a power-up timing and a voltage level of each power rail signal in the set of power rail signals;

And the PMIC chip control module is used for enabling each PMIC chip to output a group of power rail signals with the voltage level to a corresponding connected SOC chip according to the power-on time sequence when receiving the power-on parameters of the group of power rail signals from the MCU chip so as to supply power to the SOC chip.

17. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 13 to 15.