CN106708545A

CN106708545A - Novel programmer design applied to anti-fuse FPGA

Info

Publication number: CN106708545A
Application number: CN201510501182.5A
Authority: CN
Inventors: 卢骏
Original assignee: Individual
Current assignee: Individual
Priority date: 2015-08-17
Filing date: 2015-08-17
Publication date: 2017-05-24

Abstract

The invention discloses a novel programmer hardware design applied to an anti-fuse FPGA. The novel programmer hardware comprises an FPGA chip circuit used for communication with an upper computer, a multi-programming-voltage generation circuit used for anti-fuse programming, a multi-voltage acquisition circuit used for voltage acquisition, and a resistor detection circuit used for real-time detection of an anti-fuse resistor. The FPGA chip circuit is used for communicating with the upper computer and providing a control digital signal according to programming information of the upper computer; a memory is used for storing the programming information; the multi-programming-voltage generation circuit generates multiple programming voltages according to the control digital signal provided by an FPGA chip; and the resistor detection circuit is used for detecting a state of the anti-fuse resistor in real time.

Description

It is applied to the novel programmed device design of anti-fuse FPGA

Technical field

The present invention relates to a kind of FPGA programming hardware circuit designs, the volume of anti-fuse FPGA is particularly well-suited to Journey device hardware design.

Background technology

FPGA can be divided into the FPGA based on SRAM structures, base according to the difference for realizing logic function FPGA in anti-fuse structures etc..The FPGA structure of SRAM structures is simple, but a disadvantage is that after power down Configuration information is lost, after electricity is gone up next time, it is necessary to which re-downloading configuration information could work.And antifuse After FPGA power down, configuration information will not be lost, and can directly be worked after upper electricity.Other anti-fuse structures Flouride-resistani acid phesphatase Ability is strong, performance safety reliability, is adapted to military and aerospace level device.

Antifuse is a kind of semiconductor devices for adding a layer insulating to constitute between two conductting layers.Do not compiling Open-circuit condition is under journey state, the resistance between conductting layer is very big.Programmed when being added at antifuse two ends After voltage, antifuse will be changed into Low ESR from high impedance, realize the connection of conducting interlayer.

Anti-fuse FPGA is programmed needs anti-fuse FPGA programmable device.The programming of antifuse needs tight The sequential and voltage request of lattice.Programmable device needs to apply lasting high level arteries and veins in specified antifuse one end Punching, while programmable device needs the burning situation of real-time detection antifuse, will stop continuing after antifuse programming Programming, in case burning, has influence on other antifuse.

At present, antifuse programmable device relies primarily on import, on the one hand, expensive；On the other hand, program Process is uncontrollable, it is impossible to which the antifuse to wanting programming is programmed.

The content of the invention

In order to overcome the above-mentioned deficiencies of the prior art, the present invention proposes a kind of volume for anti-fuse FPGA Journey device is designed.

The technical solution used in the present invention includes：For the FPGA chip circuit communicated with host computer；With For the multiprogramming voltage generation circuit of antifuse programming；Electricity is gathered with the plurality of voltages for collection voltages Road；With the resistance detecting circuit for real-time detection antifuse resistance.

The FPGA chip circuit for wherein being communicated with host computer receives host computer programming information by USB interface. The programming information that FPGA will be received from host computer is preserved in memory, and then fpga chip is from memory Programming information is read, providing plurality of voltages control signal according to programming information gives multiprogramming voltage generation circuit. The signal that multiprogramming voltage generation circuit is provided according to fpga chip produces multiprogramming control voltage with right Anti-fuse FPGA chip is programmed.Because fpga chip is executed in parallel, it is possible to product simultaneously Raw multiprogramming voltage.Easily realize anti-fuse FPGA program timing sequence.

Voltage detecting circuit with real-time detection multi-channel control voltage, and can be sent to fpga chip, FPGA cores Piece is sending the data to host computer, allows host computer to know programming state.Resistance detecting circuit is really one Current detection circuit, by detecting electric current, and carries out related conversion, you can learn resistance.In antifuse not Under programming, resistance is very big, therefore electric current very little.After antifuse is programmed, resistance is smaller, thus electric current compared with Greatly, therefore by detecting current value can determine whether whether antifuse programs successfully.

According to an aspect of the present invention, the FPGA chip circuit communicated with host computer using USB with Host computer is communicated.According to the programming information of host computer, multiprogramming is produced on the program timing sequence of regulation Control signal.Memory, the programming information for storing host computer transmission, while fpga chip is therefrom read Take programming information.This memory realizes the pingpong operations to anti-fuse FPGA programming, when to antifuse When being programmed, while receiving programming information, the fpga chip in programming process can be greatly reduced Circuit and the call duration time of host computer, improve programming efficiency.

According to an aspect of the present invention, the multiprogramming voltage generation circuit for antifuse programming is used It is programmed in anti-fuse FPGA chip.The circuit provides program voltage to programming antifuse, by holding It is continuous to apply the burning that program voltage pulse realizes antifuse.

According to an aspect of the present invention, the electric current on resistance detecting circuit collection antifuse programming path is one The voltage produced on individual small resistor, when antifuse successful program, voltage changes.Voltage detecting circuit The real-time detection voltage, and be sent to host computer and judged, when voltage exceedes the threshold value of setting, judge Antifuse has been programmed successfully, stops sending burning voltage.

Brief description of the drawings

Fig. 1 is anti-fuse FPGA programmer system block diagram of the invention.

Fig. 2 is fpga chip of the invention and host computer circuit block diagram.

Fig. 3 is that multi-channel control voltage of the invention is produced and control circuit theory diagrams.

Fig. 4 is voltages Acquisition Circuit schematic diagram of the invention.

Fig. 5 is resistance detecting circuit schematic diagram of the invention.

Specific embodiment

The present invention will be described in detail below in conjunction with the accompanying drawings.

Fig. 1 show the anti-fuse FPGA programmer system block diagram of one embodiment of the present invention.The system Block diagram includes：Host computer PC, fpga chip, multiprogramming voltage generation circuit, plurality of voltages collection electricity Road, resistance detecting circuit and anti-fuse FPGA.Wherein fpga chip, multiprogramming voltage generation circuit, Voltages Acquisition Circuit and resistance detecting circuit are the major part of anti-fuse FPGA programmable device, such as Fig. 1 Shown in dotted line frame.Anti-fuse FPGA programmable device fpga chip receives the programming information of host computer PC, produces Give birth to multi-channel control data signal to multiprogramming voltage generation circuit.Wherein, multiprogramming voltage generation circuit Wherein voltage output is connected to anti-fuse FPGA program voltage interface by resistance detecting circuit all the way.It is many The output of road program voltage and resistance detecting circuit as voltages Acquisition Circuit input, plurality of voltages adopts The output of collector sends fpga chip to.Host computer is sent to after the fpga chip data processing.

Fig. 2 show the fpga chip and host computer telecommunication circuit block diagram of one embodiment of the present invention.As schemed Shown, host computer is communicated with fpga chip by USB interface.Fpga chip receives the programming of host computer Information.According to programming information, fpga chip produces multi-channel control data signal and is sent to multi-channel control voltage Produce circuit.Fpga chip receives the voltage that voltages Acquisition Circuit is collected simultaneously, after being processed It is sent to host computer.

Fig. 3 show the multiprogramming voltage generation circuit schematic diagram of one embodiment of the present invention.The circuit Schematic diagram includes：Multichannel DAC and multiplex arithmetric amplifier.The 1 control data signal provided for fpga chip. The control data signal of input is converted into analog signal output by DAC.Because DAC output voltage is unsatisfactory for programming Voltage request, so to add one-level amplifying circuit in rear class, output voltage is amplified.Amplifying circuit is adopted Designed with operational amplifier, in-phase amplifier is constituted with operational amplifier.The multiple of amplification is 1+R2/R1. The output 2 of operational amplifier is connected to voltage detecting circuit, resistance detecting circuit and anti-fuse FPGA chip and compiles Journey voltage relevant pins.More than be plurality of voltages produce wherein all the way, other several roads are also same original Reason.

Fig. 4 show the voltage acquisition schematic diagram of one embodiment of the present invention.The schematic diagram includes：Resistance Bleeder circuit, follow circuit and ADC.1 is the voltage of collection.The voltage that resistor voltage divider circuit is intended to collection enters Row partial pressure, because program voltage is comparing high, more than the maximum magnitude that ADC can change voltage, therefore needs Collection voltages are reduced.Voltage after partial pressure is the R2/ (R1+R2) of input voltage.Rear class is followed with one Circuit, output voltage follows the voltage of the positive input terminal of operational amplifier.Circuit is followed to keep apart front stage, Late-class circuit is set not cause load effect to prime.The output of circuit is followed directly to the input of ADC, ADC The analog voltage signal of input is converted into data signal output.ADC output ends 2 export fpga chip and enter Row collection.

Fig. 5 show the resistance detecting circuit schematic diagram of one embodiment of the present invention.1 is the volume of antifuse Journey voltage.Antifuse, in programming, can just have electric current and flow through R1, in R1 two with equivalent into a resistance End has a voltage, and differential precision amplifier is amplified to voltage, output to voltages Acquisition Circuit, Fpga chip feeds back to host computer after will collecting the signal and treatment for converting.Host computer passes through FPGA The data of feedback, by certain conversion it is known that the now resistance value of antifuse.

Claims

1. a kind of anti-fuse FPGA novel programmed device hardware circuit design, it is characterized in that including：Fpga chip electricity Road, multiprogramming voltage generation circuit, voltages Acquisition Circuit, resistance detecting circuit；By the programming Device, freely quickly can be programmed to antifuse.