CN107395190B - Circuit and driving system for rapidly responding to fault signals - Google Patents
Circuit and driving system for rapidly responding to fault signals Download PDFInfo
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- 230000002457 bidirectional effect Effects 0.000 description 3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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Abstract
The invention discloses a circuit and a driving system for rapidly responding to fault signals, which comprises a first NAND gate U11A, a second NAND gate U11C and a third NAND gate U11D, wherein one input end of the first NAND gate U11A is used as a low-level enabling end of the fault signals, the other input end of the first NAND gate U11A is respectively connected with one input end of the second NAND gate U11C and the output end of the third NAND gate U11D, the output end of the third NAND gate U11D is used as a fault signal uploading end, the other input end of the second NAND gate U11C is used as a control enabling end, the output end of the second NAND gate U11C is used as a low-level enabling end, the output end of the first NAND gate U11A is connected with one input end of the third NAND gate U11D, and the other input end of the third NAND gate U11D is used as a fault signal resetting end. The invention has the advantages that: the drive acquisition circuit is quickly acquired to be closed so as to protect the part to be driven and latch fault signals
Description
Technical Field
The present invention relates to the field of drivers in circuits, and more particularly, to a circuit and a driving system for rapidly responding to a fault signal.
Background
In industries such as a power supply or a motor driver, a circuit structure for driving a power device is shown in fig. 1, and the circuit comprises a singlechip MCU, a buffer, a driving acquisition circuit and a device to be driven. The MCU comprises a first output end, a second output end and a first input end. The buffer comprises a first input end, a second input end and a first output end. The drive acquisition circuit comprises a first input end, a second input end, a first output end and a second output end. The first output end of the MCU is connected with the first input end of the buffer, the first output end of the buffer is connected with the first input end of the drive acquisition circuit, and the drive acquisition circuit is in bidirectional connection with the device to be driven through the second input end and the second output end. The first output end of the drive acquisition circuit is used as a low-level enabling end of a fault signal to be connected with the first input end of the single chip microcomputer MCU, and the second output end of the single chip microcomputer MCU is used as a low-level enabling end to be connected with the second input end of the buffer.
In the figureFor fault signal +.>To enable signals.
The MCU outputs an enable signal from the low-level enable endThe signal A sent by the first output end of the MCU outputs a signal B through the first output end of the buffer, the signal B outputs a signal C through the first output end of the drive acquisition circuit, the signal C drives a power device (the power device comprises devices such as a MOS tube, an IGBT and a triode), the drive acquisition circuit judges whether the faults such as overcurrent and short circuit exist or not through sampling the signals of the power device, and therefore the fault signal sent by the low-level enable end of the fault signal is a fault signal->To the first input of the single chip microcomputer. In the figure->A low enable end for fault signal receives a fault signal,/for fault signal>An enable signal is sent out by the low level enable terminal.
In the prior art, the fault signalAccessing to a singlechip MCU, executing interrupt program by the singlechip MCU to set high enable signal +.>Thereby closing the drive acquisition circuit and further closing the work of the device to be driven. The MCU executes an interrupt program to respond to the fault signal>Is a relatively lengthy process because the single-chip MCU needs to push data onto the stack first and then execute the corresponding interrupt service routine, requiring at least ten instruction cycles. Even if a DSP which is more advantageous than a singlechip MCU is used for processing data, the running speed of 24MHz clock frequency is used with the current more advanced DSP TMS320F28335, one instruction period is 42ns, and the fault signal is received>To send out high enable signal to the buffer +.>This process requires at least 420ns time, which does not yet include a delay from the buffer signal to the power device. In such a process, once the device to be driven is short-circuited, the energy Q generated by the device to be driven is likely to burn itself. In addition, if the fault signal is->The duration is very short and less than 100ns, and the MCU is likely to not inquire fault signals +.>In summary, the response to a fault signal is very slow to implement by software. There is therefore a great need for a circuit that reacts rapidly to fault signals to solve this technical problem.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to solve the problems that the device to be driven is possibly burnt down due to the too slow corresponding speed of realizing the fault signal by software in the prior art, and the MCU is likely to not inquire the fault signal in the data processing processNumber (number)Accordingly, the present invention provides a circuit and a driving system for rapidly responding to a fault signal.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the circuit for rapidly responding to fault signals comprises a first NAND gate U11A, a second NAND gate U11C and a third NAND gate U11D, wherein one input end of the first NAND gate U11A is used as a low-level enabling end of the fault signals, the other input end of the first NAND gate U11A is respectively connected with one input end of the second NAND gate U11C and the output end of the third NAND gate U11D, the output end of the third NAND gate U11D is used as a fault signal uploading end, the other input end of the second NAND gate U11C is used as a control enabling end, the output end of the second NAND gate U11C is used as a low-level enabling end, the output end of the first NAND gate U11A is connected with one input end of the third NAND gate U11D, and the other input end of the third NAND gate U11D is used as a fault signal resetting end.
The power supply VDD is connected with the ground through the resistor R1 and the capacitor C1 in sequence, and the fault signal low-level enabling end is connected with a connecting point of the resistor R1 and the capacitor C1.
Preferably, the capacitance C1 is 100-1000pF.
Preferably, the first nand gate U11A, the second nand gate U11C, and the third nand gate U11D are integrated in the nand gate U11, and a chip of the nand gate U11 is 74LS00.
Optimally, the 1 st pin of the NAND gate U11 is used as a receiving end of a fault signal, the 2 nd pin, the 10 th pin and the 11 th pin of the NAND gate U11 are connected and then used as an uploading end of the fault signal, the 3 rd pin is connected with the 12 th pin, the 8 th pin is used as a low level enabling end, the 9 th pin is used as a control enabling end, the 7 th pin is connected with the ground, the 13 th pin is used as a reset end of the fault signal, and the 14 th pin is connected with the power supply VDD.
The driving system comprises the circuit for rapidly responding to the fault signal, and further comprises a singlechip MCU, a buffer and a driving acquisition circuit, wherein the singlechip MCU comprises a first input end, a first output end, a second output end and a third output end; the buffer comprises a first input end, a second input end, a first output end and a drive acquisition circuit, wherein the drive acquisition circuit comprises a first input end and a first output end;
the first output end of the MCU is connected with the first input end of the buffer, and the first output end of the buffer is connected with the first input end of the drive acquisition circuit;
the fault signal uploading end, the fault signal resetting end and the control enabling end are respectively connected with the first input end, the second output end and the third output end of the MCU, the low-level enabling end is connected with the second input end of the buffer, and the first output end of the driving acquisition circuit is connected with the low-level enabling end of the fault signal.
The driving acquisition circuit is connected with the device to be driven in a bidirectional manner through the second input end and the second output end.
Preferably, the device to be driven is a MOS tube, a grid electrode of the MOS tube is connected with a second output end of the driving acquisition circuit, and a source electrode of the MOS tube is connected with a second input end.
Preferably, the device to be driven is an IGBT tube, a grid electrode of the IGBT tube is connected with a second output end of the drive acquisition circuit, and a source electrode of the IGBT tube is connected with a second input end.
Preferably, the device to be driven is a triode, a base electrode of the triode is connected with a second output end of the driving acquisition circuit, and an emitting electrode of the triode is connected with a second input end.
The invention has the advantages that:
(1) The circuit of the invention can rapidly acquire the fault signalControl high enable signal +.>The drive acquisition circuit is closed,thereby protecting the component to be driven and the circuit is capable of latching a fault signal + ->Preventing fault signalsLost.
(2) The larger the value of the capacitor C1 is, the slower the value is correspondingly, but the better the burr filtering effect is, and the value of the C1 is determined according to multiple experimental detection.
Drawings
Fig. 1 is a block diagram of a prior art drive system.
Fig. 2 is a circuit diagram of a circuit for rapidly responding to a fault signal according to the present invention.
Fig. 3 is a block diagram of a drive system of the present invention.
The components in the figures are described as follows:
1-buffer 2-drive acquisition circuit 3-device to be driven 4-circuit of quick response fault signal.
Detailed Description
Example 1
As shown in fig. 2, a circuit for rapidly responding to a fault signal includes a power supply VDD, a resistor R1, a capacitor C1, a first nand gate U11A, a second nand gate U11C, and a third nand gate U11D. The first nand gate U11A, the second nand gate U11C, and the third nand gate U11D are integrated in the nand gate U11, and the model of the chip where the nand gate U11 is located is 74LS00.
One input terminal of the first nand gate U11A, i.e., the 1 st pin of the nand gate U11, is used as a low-level enable terminal of the fault signal. The other input end of the first NAND gate U11A is respectively connected with one input end of the second NAND gate U11C and the output end of the third NAND gate U11D, namely the 2 nd pin, the 10 th pin and the 11 th pin of the NAND gate U11 are connected and then serve as fault signal uploading ends. The other input end of the second nand gate U11C, namely the 9 th pin of the nand gate U11 is used as a control enabling end, the output end of the second nand gate U11C, namely the 8 th pin of the nand gate U11 is used as a low level enabling end, and the output end of the first nand gate U11A is connected with one input end of the third nand gate U11D, namely the 3 rd pin and the 12 th pin of the nand gate U11. The other input end of the third nand gate U11D, i.e. the 13 th pin of the nand gate U11, is used as a fault signal reset end. The 7 th pin of the NAND gate U11 is connected with the ground, and the 14 th pin is connected with the power supply VDD.
In order to filter burrs input by the low-level enabling end of the fault signal, the power supply VDD is connected with the ground through the resistor R1 and the capacitor C1 in sequence, and the low-level enabling end of the fault signal is connected with a connecting point of the resistor R1 and the capacitor C1. Since the larger the capacitance is, the slower the response speed is, but the better the burr filtering effect is, after a plurality of tests, the capacitance C1 is determined to be 100pF.
In the figureA reset signal received by the FAULT signal reset terminal for the FAULT signal low level enable terminal, a reset signal received by the fault_rst for the FAULT signal reset terminal, a control enable signal received by the control enable terminal for the control enable terminal, and->For the enable signal sent by the low level enable terminal, contrl OE is control +.>Enable, when->Under the condition that three signals of FAULT_RST and Contrl OE are high level, each pin randomly presents the following two states after being electrified:
state one:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 1 | 1 | 1 | 0 | 0 |
State two:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 1 | 1 | 0 | 1 | 1 |
After power-on, firstly, the 1 foot, the 9 foot and the 13 foot are set high through the control of an external circuit or a chip, then the 13 foot starts to reset, finally the 13 foot is set low, and finally the obtained state of each foot is changed into:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 1 | 0 | 1 | 0 | 0 |
And then the 13 feet are placed high, and each foot is changed into:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 1 | 1 | 1 | 0 | 0 |
At this time, the circuit for rapidly responding to the fault signal is in a monitoring state, onceAt low level, each foot state changes vertically and latches as:
the enable signal of the process from the beginning to the 8 th footThe set high lasts for a few nanoseconds, and then the fault signal is uploaded through the 11 th foot fault signal uploading end.
Even if the 1 st pin is changed to the high level again, the state remains the original state, namely, is latched as:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 0 | 1 | 1 | 0 | 1 | 1 |
If the monitoring state is to be restored, the FAULT_RST reset operation is repeated.
If the control chip is actively turned off, the control chip is enabled to be set highOnly the Contrl OE needs to be set low, the state changes as follows:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 0 | 1 | 0 | 1 | 1 |
Example 2
As shown in fig. 2-3, a driving system comprises a singlechip microcomputer MCU, a buffer 1, a driving acquisition circuit 2, a device to be driven 3 and a circuit 4 for rapidly responding to fault signals. The MCU comprises a first input end, a second input end, a first output end, a second output end and a third output end; the buffer 1 includes a first input terminal, a second input terminal, a first output terminal, and the drive acquisition circuit 2 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal.
The first output end of the singlechip MCU is connected with the first input end of the buffer 1, the first output end of the buffer 1 is connected with the first input end of the drive acquisition circuit 2, and the drive acquisition circuit 2 is in bidirectional connection with the device to be driven 3 through the second input end and the second output end. The driving acquisition circuit 2 judges whether faults such as overcurrent and short circuit exist or not by sampling signals of the power device, so that fault signals sent by the low-level enabling end of the fault signals are sent to the first input end of the singlechip.
The device 3 to be driven is a power device, the part 3 to be driven can be an MOS tube, the grid electrode of the MOS tube is connected with the second output end of the drive acquisition circuit, and the source electrode of the MOS tube is connected with the second input end.
The device 3 to be driven can also be an IGBT tube, the grid electrode of the IGBT tube is connected with the second output end of the drive acquisition circuit, and the source electrode of the IGBT tube is connected with the second input end.
The device 3 to be driven can also be a triode, the base electrode of the triode is connected with the second output end of the drive acquisition circuit, and the emitting electrode of the triode is connected with the second input end.
The circuit 4 for rapidly responding to the fault signal comprises a NAND gate U11, a power supply VDD, a resistor R1 and a capacitor C1, wherein the chip model number of the NAND gate U11 is 74LS00. The NAND gate chip comprises a first NAND gate U11A, a second NAND gate U11C and a third NAND gate U11D.
One input end of the first nand gate U11A, i.e. the 1 st pin of the nand gate U11, is connected to the first output end of the driving acquisition circuit 2 as a low-level enabling end of the fault signal. The other input end of the first NAND gate U11A is respectively connected with one input end of the second NAND gate U11C and the output end of the third NAND gate U11D, namely, the 2 nd pin, the 10 th pin and the 11 th pin of the NAND gate U11 are connected and then serve as fault signal uploading ends to be connected with the first input end of the single chip microcomputer MCU. The other input end of the second NAND gate U11C, namely the 9 th pin of the NAND gate U11, is used as a control enabling end to be connected with the third input end of the singlechip MCU, the output end of the second NAND gate U11C, namely the 8 th pin of the NAND gate U11, is used as a low level enabling end, and the low level enabling end is connected with the second input end of the buffer 1. The output end of the first nand gate U11A is connected to one input end of the third nand gate U11D, i.e. the 3 rd pin and the 12 th pin of the nand gate U11. The other input end of the third NAND gate U11D, namely the 13 th pin of the NAND gate U11, is used as a fault signal reset end, and the fault signal reset end is connected with the second input end of the singlechip MCU. The 7 th pin of the NAND gate U11 is connected with the ground, and the 14 th pin is connected with the power supply VDD.
In order to filter burrs input by the low-level enabling end of the fault signal, the power supply VDD is connected with the ground through the resistor R1 and the capacitor C1 in sequence, and the low-level enabling end of the fault signal is connected with a connecting point of the resistor R1 and the capacitor C1. Since the larger the capacitance is, the slower the response speed is, but the better the burr filtering effect is, after a plurality of tests, the capacitance C1 is determined to be 100pF.
In the figure, the low-level enabling end of the fault signal receivesFor FAULT signals, fault_rst received by the FAULT signal reset terminal is a reset signal, contrl OE received by the control enabling terminal is a control enabling signal, and low level enabling terminal sends out +.>For enabling the signal, contrl OE is control +.>Enabled. When->Under the condition that three signals of FAULT_RST and Contrl OE are all high level, each pin randomly presents the following two states after being electrified:
state one:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 1 | 1 | 1 | 0 | 0 |
State two:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 1 | 1 | 0 | 1 | 1 |
After power-on, the singlechip MCU firstly sets the pins 1, 9 and 13 high, then the pins 13 start to reset, finally sets the pins 13 low, and finally obtains the state change of each pin as follows:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 1 | 0 | 1 | 0 | 0 |
And then the 13 feet are placed high, and each foot is changed into:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 1 | 1 | 1 | 0 | 0 |
At this time, the circuit for rapidly responding to the fault signal is in a monitoring state, onceAt low level, each foot state changes vertically and latches as:
this process starts from the beginning toThe single chip microcomputer MCU receives the fault signal uploaded by the 11 th pin after the single chip microcomputer MCU is set high for a few nanoseconds.
Even if the 1 st pin is changed to the high level again, the state remains the original state, namely, is latched as:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 0 | 1 | 1 | 0 | 1 | 1 |
If the monitoring state is to be restored, the FAULT_RST reset operation is repeated.
If the MCU is actively turned off, the MCU is enabled to be set highOnly the Contrl OE needs to be set low, the state changes as follows:
| 1 foot | 9 feet | 13 feet | 2 feet/10 feet/11 feet | 3 feet/12 feet | 8 feet |
| 1 | 0 | 1 | 0 | 1 | 1 |
Example 3
The difference from the two embodiments described above is that the capacitor C1 has a value of 1000PF.
Example 4
The difference from example 1 and example 2 is that the capacitor C1 has a value of 500PF.
The above description is given for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, but is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (6)
1. The circuit is characterized by comprising a first NAND gate U11A, a second NAND gate U11C and a third NAND gate U11D, wherein one input end of the first NAND gate U11A is used as a low-level enabling end of a fault signal, the other input end of the first NAND gate U11A is respectively connected with one input end of the second NAND gate U11C and the output end of the third NAND gate U11D, the output end of the third NAND gate U11D is used as a fault signal uploading end, the other input end of the second NAND gate U11C is used as a control enabling end, the output end of the second NAND gate U11C is used as a low-level enabling end, the output end of the first NAND gate U11A is connected with one input end of the third NAND gate U11D, and the other input end of the third NAND gate U11D is used as a fault signal resetting end;
the power supply VDD is connected with the ground through the resistor R1 and the capacitor C1 in sequence, and the low-level enabling end of the fault signal is connected with the connection point of the resistor R1 and the capacitor C1;
the first NAND gate U11A, the second NAND gate U11C and the third NAND gate U11D are integrated in the NAND gate U11, and the model of a chip where the NAND gate U11 is located is 74LS00;
the 1 st pin of the NAND gate U11 is used as a receiving end of a fault signal, the 2 nd pin, the 10 th pin and the 11 th pin of the NAND gate U11 are connected and then used as a fault signal uploading end, the 3 rd pin is connected with the 12 th pin, the 8 th pin is used as a low level enabling end, the 9 th pin is used as a control enabling end, the 7 th pin is connected with the ground, the 13 th pin is used as a fault signal resetting end, and the 14 th pin is connected with a power supply VDD;
the capacitance C1 is taken as 100pF.
2. A driving system comprising the circuit for rapidly responding to a fault signal according to claim 1, and further comprising a single-chip microcomputer MCU, a buffer (1) and a driving acquisition circuit (2), wherein the single-chip microcomputer MCU comprises a first input end, a first output end, a second output end and a third output end; the buffer (1) comprises a first input end, a second input end, a first output end and a drive acquisition circuit (2) comprising a first input end and a first output end;
the first output end of the singlechip MCU is connected with the first input end of the buffer (1), and the first output end of the buffer (1) is connected with the first input end of the drive acquisition circuit (2);
the fault signal uploading end, the fault signal resetting end and the control enabling end are respectively connected with the first input end, the second output end and the third output end of the MCU, the low-level enabling end is connected with the second input end of the buffer (1), and the first output end of the driving acquisition circuit (2) is connected with the low-level enabling end of the fault signal.
3. The driving system according to claim 2, further comprising a device (3) to be driven, wherein the driving acquisition circuit (2) further comprises a second input end and a second output end, and the driving acquisition circuit (2) is bi-directionally connected with the device (3) to be driven through the second input end and the second output end.
4. A driving system according to claim 3, wherein the device to be driven (3) is a MOS transistor, a gate of the MOS transistor is connected to the second output terminal of the driving and collecting circuit, and a source of the MOS transistor is connected to the second input terminal.
5. A driving system according to claim 3, characterized in that the device (3) to be driven is an IGBT tube, the gate of which is connected to the second output of the drive acquisition circuit, and the source of which is connected to the second input.
6. A driving system according to claim 3, characterized in that the device (3) to be driven is a triode, the base of which is connected to the second output of the drive acquisition circuit, and the emitter of which is connected to the second input.
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