CN106209066B - Chip pin multiplexing method and chip - Google Patents
Chip pin multiplexing method and chip Download PDFInfo
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- CN106209066B CN106209066B CN201610682792.4A CN201610682792A CN106209066B CN 106209066 B CN106209066 B CN 106209066B CN 201610682792 A CN201610682792 A CN 201610682792A CN 106209066 B CN106209066 B CN 106209066B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Abstract
The invention discloses a method for multiplexing chip pins and a chip, wherein any pin of the chip is grounded through an external resistor, when the chip is started, the voltage of the pin is controlled to be fixed voltage or fixed current is set to flow to the pin, and the current flowing through the pin or the voltage of the pin is collected and converted so as to latch an output signal obtained by conversion; so that the output signal has multiple paths or multiple forms under different off-chip resistances, thereby setting multiple working states of the chip based on the output signal. The invention sets the working state of the chip by using the existing driving pin through the peripheral resistor under the condition of not increasing the chip pin, so that the chip is more convenient and flexible to use, and the production and use cost is reduced.
Description
Technical Field
The invention belongs to the technical field of electronic chip design, and particularly relates to a chip pin multiplexing method and a chip.
Background
Currently, testing of integrated circuit chips is typically performed after the chips are shipped. Due to the high integration and complexity of the chip, not only the output signal of the chip but also the individual internal functional signals need to be tested, so the testability of the chip is important. In a conventional test, a test PAD is usually added inside a chip or a pin of the chip is added for detecting the correctness of an internal functional signal.
For the same type of chip, the parameters of the chip are often required to be adjusted, and different working states of the chip are set. For example, the reference voltage of one chip is 600mV, the reference voltage of another chip in the same series is 1.2V, and the performance parameters are the same in other aspects. It is generally necessary to produce two different chips for two different applications. In order to facilitate use and reduce cost, a set pin is additionally arranged on some chips, and the chips can be set to work in different states by setting the pin. Different chips are produced, and the production cost is inevitably increased; however, the chip area is increased by adding an additional mounting pin, the package cost is increased, and the system cost is also increased.
With the development of integrated circuits, not only is the testability required for an integrated circuit chip, but also a test scheme is required to save the chip area as much as possible so as to save the chip cost, thereby improving the product profit, and simultaneously, the chip debugging and secondary chip feeding for the chip fed out are required to be convenient; this is the direction in which the applicant is working.
Disclosure of Invention
Based on the above, the invention provides a method for multiplexing chip pins and a chip, which utilize the existing pins to set the working state of the chip through a peripheral resistor without increasing the chip pins, so that the chip is more convenient and flexible to use, and the production and use costs are reduced.
A method for multiplexing chip pins comprises the steps that any pin of a chip is grounded through an external resistor, when the chip is started, the voltage of the pin is controlled to be fixed voltage or fixed current is set to flow to the pin, the current flowing through the pin or the voltage of the pin is collected and converted, and then an output signal obtained through conversion is latched; so that the working state of the chip is set according to the output signal under different off-chip resistances.
Further, when the voltage of the control pin is a fixed voltage, the current flowing through the pin is collected and converted; and when the fixed current is set to flow to the pin, acquiring the voltage of the pin and converting the voltage.
Further, after the latch is completed, the fixed voltage control or the fixed current setting of the pin is cancelled, so as to avoid influencing an external device on the pin.
A pin multiplexing chip comprises a pin multiplexing circuit; for any pin of the chip, the pin multiplexing circuit is connected with the pin and an off-chip resistor, and the other end of the off-chip resistor is grounded; the pin multiplexing circuit comprises a switch, a pin control module, a signal acquisition and conversion module and a latch module; wherein:
the pin control module is connected with the pin through a switch and is used for controlling the voltage of the pin to be a fixed voltage or setting a fixed current to flow to the pin;
the signal acquisition and conversion module is used for acquiring the current flowing through the pin or the voltage of the pin and converting the current or the voltage of the pin so as to generate a plurality of paths of output signals or a plurality of types of output signals;
the latch module is used for latching the output signal;
the switch is switched on when the chip is started and is switched off after the latching module completes latching.
Furthermore, when the pin control module is used for controlling the pin voltage to be a fixed voltage, the signal acquisition and conversion module is used for acquiring and converting the current flowing through the pin; when the pin control module is used for setting the fixed current flowing direction to the pin, the signal acquisition and conversion module is used for acquiring the voltage of the pin and converting the voltage of the pin.
Furthermore, when the pin control module is used for controlling the pin voltage to be a fixed voltage, an operational amplifier is adopted, the non-inverting input end of the operational amplifier is connected with the fixed voltage, the inverting input end and the output end of the operational amplifier are connected in common and connected with one end of the switch, and the other end of the switch is connected with the pin.
Furthermore, when the pin control module is used for setting a fixed current to flow to the pin, the pin control module adopts a current source, the current output by the current source is equal to the fixed current, the input end of the current source is connected with the power voltage, the output end of the current source is connected with one end of the switch, and the other end of the switch is connected with the pin.
Furthermore, the signal acquisition conversion module adopts an A/D conversion circuit, the A/D conversion circuit has an N-bit conversion function, the input end of the A/D conversion circuit acquires current or pin voltage flowing through a pin, and the output end of the A/D conversion circuit generates 2 N The output signal of the circuit, N is a natural number larger than 0.
Furthermore, when the signal acquisition and conversion module is used for acquiring the current flowing through the pin and converting the current, the signal acquisition and conversion module consists of a fixed current source and a controlled current source, wherein the magnitude of the current output by the controlled current source is controlled by the current flowing through the pin, the input end of the controlled current source is connected with the power voltage, and the output end of the controlled current source is connected with the input end of the fixed current source and generates the output signal; the current output by the fixed current source is fixed, and the output end of the fixed current source is grounded.
Furthermore, the latch module adopts a D flip-flop or a multi-way latch.
The pin is a switch tube driving pin.
A switch circuit comprises a switch tube and a control chip thereof, wherein the control chip adopts a chip with multiplexed pins.
Based on the technical scheme, the working state of the chip is set by utilizing the conventional driving pin through the peripheral resistor under the condition that the pin of the chip is not increased, so that the chip is more convenient and flexible to use, and the production and use cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a first embodiment of a pin multiplexing chip according to the invention.
Fig. 2 is a schematic structural diagram of a pin multiplexing chip according to a second embodiment of the invention.
Fig. 3 is a schematic structural diagram of a pin multiplexing chip according to a third embodiment of the invention.
Detailed Description
In order to more specifically describe the present invention, the following detailed description is provided for the technical solution of the present invention with reference to the accompanying drawings and the specific embodiments.
Example 1
As shown in fig. 1, the chip with pin multiplexing of the present embodiment includes a pin multiplexing circuit and a control driving circuit U00; the pin multiplexing circuit and the control driving circuit U00 are connected with a driving pin GATE of the chip and an off-chip resistor R10 together, and the other end of the off-chip resistor R10 is grounded; the control driving circuit U00 is used for providing a switching control signal for the off-chip switching tube M00 through a driving pin GATE, and the driving pin GATE is also connected with a grid electrode of the switching tube M00 and an off-chip capacitor C00, wherein C00 can be an additional capacitor or a parasitic capacitor of the switching tube M00; the source of the switch tube M00 and the other end of the off-chip capacitor C00 are both grounded.
The pin multiplexing circuit in the present embodiment includes a switch K10, an operational amplifier U10, a controlled current source I11, a fixed current source I12, and a D flip-flop U11; wherein: the non-inverting input end of the operational amplifier U10 is connected with a fixed voltage VREF, the inverting input end and the output end of the operational amplifier U10 are connected with one end of the switch K10, so that the output voltage of the operational amplifier U10 is also VREF, and the other end of the switch K10 is connected with a driving pin GATE; the input end of the controlled current source I11 is connected with the power voltage VD, the control end acquires the current I10 flowing out of the pin multiplexing circuit to the driving pin GATE, the output end of the controlled current source I11 is connected with the input end of the fixed current source I12 and the input end of the D trigger U11, the output end of the fixed current source I12 is grounded, and the clock end CLK of the D trigger U11 receives a pulse signal.
When the switch K10 is turned on, the driving circuit U00 is controlled not to pull up or pull down the switching tube M00, the voltage on the driving pin GATE is VREF, and the fixed voltage VREF is lower than the threshold voltage of the switching tube M00, so that the switching tube M00 is ensured to be in the off state. In order to ensure that the grid electrode of the switching tube M00 is pulled down by the resistor when the chip is powered off, an on-chip resistor R00 can be added between the driving pin GATE and the ground, so that the switching tube M00 is ensured to be in a turn-off state, and the system is safe and reliable. Since the off-chip resistor R10 is added between the driving pin GATE and ground in this embodiment, the on-chip resistor R00 may or may not be added.
When the on-chip resistor R00 is added, the magnitude of the current i10 flowing out of the pin multiplexing circuit to the driving pin GATE is VREF/(R10 + R00). Since the magnitude of the on-chip resistor R00 is fixed for each chip, the magnitude of the current i10 is only related to the off-chip resistor R10. When no on-chip resistance R00 is added, i10= VREF/R10.
The controlled current source I11 and the fixed current source I12 are connected in series, wherein the controlled current source I11 is a current-controlled current source, the output current of the controlled current source I11 is controlled by the current I10, and the fixed current source I12 is a fixed current output. When the output current of the controlled current source I11 is greater than the fixed current source I12, the voltage V1 at the connection point of the controlled current source I11 and the fixed current source I12 is pulled up by the controlled current source I11, that is, the voltage V1 is high; when the output current of the controlled current source I11 is smaller than the fixed current source I12, the voltage V1 at the connection point of the controlled current source I11 and the fixed current source I12 is pulled down by the fixed current source I12, i.e. the voltage V1 is low. The voltage V1 is connected to the digital input D of the D flip-flop. After the voltage of the driving pin GATE is stabilized at VREF, the voltage V1 is also stabilized at a high level or a low level. When the pulse signal is input to the clock terminal CLK of the D flip-flop, the output terminal OUT of the D flip-flop latches the digital input terminal voltage when the output CLK is high. After the D trigger is latched, the switch K10 is switched off, the pin multiplexing circuit does not influence the switch tube M00, and the setting of the circuit is completed.
The output end OUT of the D trigger keeps latching high-level or low-level voltage, and two working states of the chip can be set. After the chip is arranged, the control drive circuit U00 controls the switching action of the switching tube M00.
The present embodiment provides two working state setting methods, and in addition, one controlled current source, a fixed current source, and a D flip-flop can set four working states, and so on.
Example 2
As shown in fig. 2, the chip for multiplexing pins in this embodiment includes a pin multiplexing circuit and a control driving circuit U00; the pin multiplexing circuit and the control driving circuit U00 are connected with a driving pin GATE of the chip and an off-chip resistor R10 in common, and the other end of the off-chip resistor R10 is grounded; the control driving circuit U00 is used for providing a switch control signal for the off-chip switching tube M00 through a driving pin GATE, the driving pin GATE is further connected with a grid electrode of the switching tube M00 and an off-chip capacitor C00, and a source electrode of the switching tube M00 and the other end of the off-chip capacitor C00 are grounded.
The pin multiplexing circuit in the present embodiment includes a switch K10, an operational amplifier U10, an a/D conversion circuit U20, and a latch U21; wherein: the non-inverting input end of the operational amplifier U10 is connected with a fixed voltage VREF, the inverting input end and the output end of the operational amplifier U10 are connected with one end of the switch K10, the output voltage of the operational amplifier U10 is also VREF, and the other end of the switch K10 is connected with a driving pin GATE; the input end of the a/D conversion circuit U20 is connected to the driving pin GATE for collecting the current i10 flowing from the pin multiplexing circuit to the driving pin GATE, the output end is connected to the input end of the latch U21, and the clock end CLK of the latch U21 receives the pulse signal.
When the switch K10 is started, the driving circuit U00 is controlled not to pull up or pull down the switching tube M00, the voltage on the driving pin GATE is VREF, and the fixed voltage VREF is lower than the threshold voltage of the switching tube M00, so that the switching tube M00 is ensured to be in a turn-off state; the current i10 drawn by the pin multiplexing circuit to the drive pin GATE is VREF/R10.
The sampled current i10 enters an a/D conversion circuit U20, and converts an analog current signal into a digital signal. The a/D conversion circuit U20 has its output connected to the digital input D of the latch U21. After the voltage at the GATE driving pin is stabilized at VREF, the magnitude of the current i10 is also stabilized. When the pulse signal is input to the clock terminal CLK of the latch U21, the output terminal OUT of the latch U21 latches the digital input terminal voltage when the output CLK is high. After the latch U21 finishes latching, the switch K10 is switched off, the pin multiplexing circuit does not influence the switching tube M00, and the setting of the chip is finished. Wherein, the A/D conversion circuit U20 can be an N-bit conversion circuit, and the output signal thereof has 2 N Way, then the input and output of latch U21 each have 2 N Way signal, i.e. set 2 N And (4) an operating state.
Example 3
As shown in fig. 3, the chip with pin multiplexing of the present embodiment includes a pin multiplexing circuit and a control driving circuit U00; the pin multiplexing circuit and the control driving circuit U00 are connected with a driving pin GATE of the chip and an off-chip resistor R10 together, and the other end of the off-chip resistor R10 is grounded; the control driving circuit U00 is used for providing a switch control signal for the off-chip switching tube M00 through a driving pin GATE, the driving pin GATE is further connected with a grid electrode of the switching tube M00 and the off-chip capacitor C00, and a source electrode of the switching tube M00 and the other end of the off-chip capacitor C00 are grounded.
The pin multiplexing circuit in the present embodiment includes a switch K10, a fixed current source I30, a clamping circuit U30, an a/D conversion circuit U20, and a latch U21; wherein: the input end of the fixed current source I30 is connected with the power supply voltage VD, the output end of the fixed current source I30 is connected with one end of a switch K10, and the other end of the switch K10 is connected with a driving pin GATE; the clamping circuit U30 is connected between the output end of the fixed current source I30 and the ground, the input end of the A/D conversion circuit U20 is connected with the output end of the fixed current source I30 for collecting the voltage of the driving pin GATE, the output end of the A/D conversion circuit U is connected with the input end of the latch U21, and the clock end CLK of the latch U21 receives a pulse signal.
When the switch K10 is started, the switch K00 is switched on, the driving circuit U00 is controlled not to pull up or pull down the switching tube M00, the current I30 output by the fixed current source I30 is fixed, and the voltage on the driving pin GATE is I30 × R10; the current I30 flows to the driving pin GATE from the output end of the fixed current source I30, the clamping circuit U30 is connected in parallel with the driving pin GATE through the switch K10, and the clamping voltage of the clamping circuit U30 is lower than the turn-on threshold voltage of the switching tube M00, so that the switching tube M00 is prevented from being switched on by mistake in the chip working state setting process. The off-chip resistor R10 cannot be too large, otherwise i30 × R10 is greater than the clamping voltage of the clamping circuit U30, and the clamping circuit U30 clamps the drive pin GATE voltage.
The voltage of the driving pin GATE is obtained by sampling, and enters the a/D conversion circuit U20 to convert the analog voltage signal into a digital signal. The a/D conversion circuit U20 has its output connected to the digital input D of the latch U21. After the voltage at the driving pin GATE is stabilized, a pulse signal is input to the clock terminal CLK of the latch U21, and the output terminal OUT of the latch U21 latches and outputs the digital input terminal voltage when CLK is high. After the latch U21 finishes latching, the switch K10 is switched off, the pin multiplexing circuit does not influence the switching tube M00, and the setting of the chip is finished. Wherein, the A/D conversion circuit U20 can be an N-bit conversion circuit, and the output signal thereof has 2 N Way, then the input and output of latch U21 each have 2 N Way signal, i.e. set 2 N And (4) an operating state.
The embodiments described above are presented to enable a person having ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to the above-described embodiments may be made, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications to the present invention based on the disclosure of the present invention within the protection scope of the present invention.
Claims (6)
1. A chip with multiplexed pins is characterized in that: comprises a pin multiplexing circuit; for any pin of the chip, the pin multiplexing circuit is connected with the pin and an off-chip resistor, and the other end of the off-chip resistor is grounded; the pin multiplexing circuit comprises a switch, a pin control module, a signal acquisition and conversion module and a latch module; wherein:
the pin control module is connected with the pin through a switch and is used for controlling the voltage of the pin to be a fixed voltage or setting a fixed current to flow to the pin;
the signal acquisition and conversion module is used for acquiring the current flowing through the pin or the voltage of the pin and converting the current or the voltage of the pin so as to generate a plurality of paths of output signals or a plurality of types of output signals;
the latch module is used for latching the output signal;
the switch is switched on when the chip is started and is switched off after the latching module completes latching;
when the pin control module is used for controlling the pin voltage to be fixed voltage, the signal acquisition and conversion module is used for acquiring current flowing through the pin and converting the current; when the pin control module is used for setting the fixed current flowing to the pin, the signal acquisition and conversion module is used for acquiring and converting the voltage of the pin;
when the pin control module is used for controlling the pin voltage to be a fixed voltage, an operational amplifier is adopted, the non-inverting input end of the operational amplifier is connected with the fixed voltage, the inverting input end and the output end of the operational amplifier are connected in common and connected with one end of a switch, and the other end of the switch is connected with the pin;
when the pin control module is used for setting the fixed current to flow to the pin, the pin control module adopts a current source, the current output by the current source is equal to the fixed current, the input end of the current source is connected with the power voltage, the output end of the current source is connected with one end of the switch, and the other end of the switch is connected with the pin.
2. The chip of claim 1, wherein: the signal acquisition and conversion module adopts an A/D conversion circuit,the A/D conversion circuit has N-bit conversion function, and has input terminal for collecting current or voltage flowing through the pin and output terminal for generating 2 N The output signal of the channel, N is a natural number greater than 0.
3. The chip of claim 1, wherein: when the signal acquisition and conversion module is used for acquiring the current flowing through the pin and converting the current, the signal acquisition and conversion module consists of a fixed current source and a controlled current source, the current output by the controlled current source is controlled by the current flowing through the pin, the input end of the controlled current source is connected with the power voltage, and the output end of the controlled current source is connected with the input end of the fixed current source to generate the output signal; the current output by the fixed current source is fixed, and the output end of the fixed current source is grounded.
4. The chip of claim 1, wherein: the latch module adopts a D trigger or a multi-path latch.
5. The chip of claim 1, wherein: the pin is a switch tube driving pin.
6. The utility model provides a switching circuit, includes switch tube and its control chip, its characterized in that: the control chip is the chip as claimed in any one of claims 1 to 5.
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| CN201610682792.4A CN106209066B (en) | 2016-08-17 | 2016-08-17 | Chip pin multiplexing method and chip |
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| CN107493099B (en) * | 2017-08-22 | 2021-11-26 | 钰泰半导体股份有限公司 | Method for setting chip working mode |
| CN109782660B (en) * | 2018-12-28 | 2020-04-24 | 深圳市优必选科技有限公司 | Control circuit and device compatible with voltage-type and current-type analog input |
| CN109921780B (en) * | 2019-03-07 | 2023-03-14 | 上海申矽凌微电子科技有限公司 | Multiplexing pin circuit |
| CN111289885B (en) * | 2020-03-06 | 2022-06-03 | 湖南国科微电子股份有限公司 | Debugging system and method for power-on and power-off of chip |
| CN111474407B (en) * | 2020-06-29 | 2020-11-13 | 上海海栎创微电子有限公司 | Mode selection device with voltage detection priority |
| CN115718248A (en) * | 2021-08-24 | 2023-02-28 | 深圳英集芯科技股份有限公司 | Chip testing and pin multiplexing unit, related method and related chip |
| CN116165510B (en) * | 2022-12-29 | 2023-11-24 | 无锡晟朗微电子有限公司 | Communication device for chip test |
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| CN101882864B (en) * | 2010-06-25 | 2012-08-22 | 矽力杰半导体技术(杭州)有限公司 | Electrifying startup circuit and electrifying startup method thereof |
| CN102820764A (en) * | 2012-09-11 | 2012-12-12 | 成都芯源系统有限公司 | control circuit, switching converter and control method thereof |
| CN103066985B (en) * | 2012-12-06 | 2016-02-17 | 无锡中星微电子有限公司 | There is the chip of multiplexing pins |
| CN103066872B (en) * | 2013-01-17 | 2015-06-17 | 矽力杰半导体技术(杭州)有限公司 | Integration switch power supply controller and switch power supply using the same |
| CN104767514B (en) * | 2015-03-16 | 2018-04-13 | 福州大学 | Integrated circuit pin multiple state representation method and its external circuits |
| CN205945689U (en) * | 2016-08-17 | 2017-02-08 | 杰华特微电子（杭州）有限公司 | Multiplexing chip of chip fin |
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