CN115718248A - Chip testing and pin multiplexing unit, related method and related chip - Google Patents

Abstract

The embodiment of the application discloses a chip testing and pin multiplexing unit, a related method and a related chip. The chip testing and pin multiplexing unit is applied to a chip, the chip comprises M chip functional units, M pins and a chip testing and pin multiplexing unit, and the chip functional units correspond to the pins one to one; the chip testing and pin multiplexing unit comprises a chip testing module, a pin multiplexing module, M first switch modules and M second switch modules, wherein the value of M is an integer greater than 1, and the value of N is 2 times of the value of M, so that pins corresponding to chip functional units are arranged in order to realize chip testing through multiplexing chips, and additional independent pins are not required to be additionally added for chip testing, thereby being beneficial to reducing the pins of the chips in the links of design, packaging, integration and the like, and further being beneficial to reducing the size of the chips, and reducing the cost of the chips in design, integration and packaging.

Description

A chip test and pin multiplexing unit and related method and related chip

technical field

The application relates to the field of integrated circuit testing, in particular to a chip testing and pin multiplexing unit, related methods and related chips.

Background technique

Before the chip is mass-produced, the chip needs to enter the test mode of various chip tests. In the test mode, the chip can be tested by the built-in test circuit. Then, after the test is completed, the chip enters the working mode of the normal chip function from the test mode, and performs related chip functions through the built-in chip function circuit, thereby ensuring the quality of chip production and operation.

However, at present, the test mode of the chip is usually performed by using a separate pin (PIN pin). This results in the need to add additional PIN pins for chip testing in links such as chip design, chip integration, and chip packaging, resulting in increased chip size and increased chip design, integration, and packaging costs.

Contents of the invention

This application provides a chip test and pin multiplexing unit and related methods and related chips, in order to achieve chip testing by multiplexing the pins corresponding to the existing chip functional units of the chip without additionally adding new components for chip testing. Independent pins are beneficial to reduce the pins in the design, packaging and integration of the chip, which in turn helps to reduce the size of the chip and reduce the cost of the chip in design, integration and packaging.

In the first aspect, the present application provides a chip testing and pin multiplexing unit, which is applied to a chip, and the chip includes M chip functional units, M pins and the chip testing and pin multiplexing unit, the The chip functional unit is in one-to-one correspondence with the pins; the chip test and pin multiplexing unit includes a chip test module, a pin multiplexing module, M first switch modules and M second switch modules. The value is an integer greater than 1, and the value of N is twice the value of M;

The chip testing module is connected to the M pins through the M first switch modules and the pin multiplexing module;

Each of the chip functional units is connected to one of the pins corresponding to the chip functional unit through the second switch module and the pin multiplexing module;

The pin multiplexing module is respectively connected to the M pins, the M first switch modules and the M second switch modules;

The chip testing module is configured to perform a chip test on the chip by multiplexing the pins corresponding to each of the M chip functional units;

The chip functional unit is used to execute the chip functions of the chip functional unit;

The pin multiplexing module is configured to control the M first switch modules and the M second switch modules so that the chip test module multiplexes the respective corresponding pins of the M chip functional units. pins described above.

It can be seen that the chip test and pin multiplexing unit of the present application realizes chip testing by multiplexing the pins corresponding to the existing chip functional units of the chip, without additionally adding independent pins for chip testing, thereby helping to reduce the number of chips. The pins in the links of design, packaging and integration are beneficial to reduce the size of the chip and reduce the cost of chip design, integration and packaging.

In addition, since the pin multiplexing module can control M first switch modules and M second switch modules, M pins can be repeatedly allocated to the chip test module for use, thereby ensuring that the chip can be repeatedly entered and exited Test mode, improve the efficiency of chip testing, and improve the utilization efficiency of chips.

In a second aspect, the present application provides a method for chip testing and pin multiplexing, which is applied to a chip. The chip includes M chip functional units, M pins, and a chip testing and pin multiplexing unit. The units correspond to the pins one by one, and the chip test and pin multiplexing unit includes a chip test module, a pin multiplexing module, M first switch modules and M second switch modules, and the value of M is An integer greater than 1, the value of N is twice the value of M; the method includes:

When the chip is powered on and in the standby state, a wake-up signal is received, and the wake-up signal is used to trigger the chip to enter the detection state;

When the chip enters the detection state, the M first switch modules and the M second switch modules are controlled by the signals detected by the pin multiplexing module from the M pins so that the chip testing module multiplexes the pins corresponding to each of the M chip functional units.

It can be seen that this application achieves chip testing by multiplexing the pins corresponding to the existing chip functional units of the chip, without adding additional independent pins for chip testing, thereby helping to reduce the number of links in the design, packaging and integration of the chip. pins, which in turn helps to reduce the size of the chip and reduce the cost of chip design, integration and packaging.

In addition, since the pin multiplexing module can control M first switch modules and M second switch modules, M pins can be repeatedly allocated to the chip test module for use, thereby ensuring that the chip can be repeatedly entered and exited Test mode, improve the efficiency of chip testing, and improve the utilization efficiency of chips.

In the third aspect, the present application provides a chip, including M chip functional units, M pins and the chip testing and pin multiplexing unit in the first aspect, the chip functional units correspond to the pins one by one , the value of M is an integer greater than 1.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings that are used in the embodiments of the present application. Apparently, the drawings described below are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a chip provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of another chip provided by an embodiment of the present application;

FIG. 3 to FIG. 6 are structural schematic diagrams of state control and transition of a chip provided by an embodiment of the present application;

FIG. 7 is a schematic flowchart of a method for chip testing and pin multiplexing provided by an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The terms "first", "second" and the like in the specification and claims of the present application and the above drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, software, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or optionally further includes For other steps or units inherent in these processes, methods, products or devices.

In this application, unless otherwise specified and limited, the term "connection" should be interpreted in a broad sense, for example, "connection" can be a fixed connection, an electrical connection, a detachable connection, an elastic connection, a direct connection, an indirect connection through an intermediary Connected, connected at intervals, etc., there is no specific limitation on this.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments. The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a chip provided by an embodiment of the present application. Wherein, the chip 10 may include: M chip functional units (such as chip functional unit 1201, chip functional unit 1202, etc.), M pins (such as pins 1301, 1302, etc.) and a chip testing and pin multiplexing unit 110. The chip testing and pin multiplexing unit 110 may include a chip testing module 1101, a pin multiplexing module 1102, M first switch modules (such as the first switch module 1103, the first switch module 1104, etc.) For the second switch module (such as the second switch module 1105 and the second switch module 1106), the value of M is an integer greater than 1, and the value of N is twice the value of M.

Wherein, the functional units of the chip and the pins can be in one-to-one correspondence. It can be understood that the existing chip functional units of the chip 10 respectively have corresponding pins.

For example, the chip functional unit 1201 corresponds to the pin 1301 , and the chip functional unit 1202 corresponds to the pin 1302 .

Wherein, the chip testing module 1101 can connect M pins through the M first switch modules and the pin multiplexing module 1102 .

For example, the chip testing module 1101 is connected to the pin 1301 and the pin 1302 through the first switch module 1103 , the first switch module 1104 and the pin multiplexing module 1102 .

Each of the chip functional units can be connected to a corresponding pin of the chip functional unit through a second switch module and the pin multiplexing module 1102 .

For example, the chip functional unit 1201 is connected to the pin 1301 through the second switch module 1105 and the pin multiplexing module 1102 , and the chip functional unit 1202 is connected to the pin 1302 through the second switch module 1106 and the pin multiplexing module 1102 .

Wherein, the pin multiplexing module 1102 can respectively connect M pins, M first switch modules and M second switch modules.

For example, the pin multiplexing module 1102 is respectively connected to the pin 1301 , the pin 1302 , the first switch module 1103 , the first switch module 1104 , the second switch module 1105 , and the second switch module 1106 .

Wherein, the chip testing module 1101 can be used to perform a chip test on the chip 10 by multiplexing the pins corresponding to each of the M chip functional units.

For example, the chip testing module 1101 performs a chip test on the chip 10 by multiplexing the pin 1301 and the pin 1302 .

Wherein, the chip functional unit can be used to execute the chip functions possessed by the chip functional unit. In addition, different chip functional units may perform different chip functions of the chip 10 .

Wherein, the pin multiplexing module 1102 can be used to control the M first switch modules and the M second switch modules so that the chip test module 1101 multiplexes the corresponding pins of the M chip functional units. It can be understood that the pin multiplexing module 1102 can control the M first switch modules and M second switch modules and their on-off states.

For example, the pin multiplexing module 1102 controls the on-off state of the first switch module 1103, the first switch module 1104, the second switch module 1105 and the second switch module 1106 so that the chip test module 1101 multiplexes the The corresponding pin 1301 and the corresponding pin 1302 of the chip functional unit 1202 .

It should be noted that before the chip is mass-produced, the chip needs to enter the test mode of various chip tests. In the test mode, the chip can be tested by the built-in test circuit. Then, after the test is completed, the chip enters the working mode of the normal chip function from the test mode, and performs related chip functions through the built-in chip function circuit, thereby ensuring the quality of chip production and operation.

However, at present, the test mode of the chip is usually performed by using a separate pin (PIN pin). This results in the need to add additional PIN pins for chip testing in links such as chip design, chip integration, and chip packaging, resulting in increased chip size and increased chip design, integration, and packaging costs.

For example, in Fig. 2, chip 20 has added two extra pins for chip testing, namely pin 2301 and pin 2302, and these two pins are corresponding to the pin of chip functional unit (chip functional unit 2201 corresponds to the pin 2303, and the chip function unit 2202 corresponds to the pin 2304). Although the chip 20 can reuse the pins 2301 and 2302 to enter the test mode by the chip test module 2101, but when the chip 20 completes the test and enters the working mode to use the chip functional unit, the additional two pins will in an idle waste state. Therefore, when pin resources of the chip are particularly tight, adding additional pins for chip testing will increase the size of the chip and increase the cost of chip design/integration/packaging.

Based on this, the pin multiplexing module 1102 of the embodiment of the present application controls M first switch modules and M second switch modules so that the chip test module 1101 multiplexes the corresponding pins of the M chip functional units, and then A chip test is performed on the chip 10 by the chip test module through the multiplexed M pins.

It can be seen that the chip test and pin multiplexing unit 110 of the embodiment of the present application implements chip testing by multiplexing the pins corresponding to the existing chip functional units of the chip 10, without adding additional independent pins for chip testing, thereby It is conducive to reducing the pins of the chip in the links of design, packaging, and integration, which in turn is beneficial to reducing the volume of the chip and reducing the cost of the chip in design, integration, and packaging.

In addition, since the pin multiplexing module 1102 can control M first switch modules and M second switch modules, the M pins can be repeatedly assigned to the chip test module 1101 for use by the chip test module 1101, thereby ensuring that the chip 10 can be used for multiple times. Repeatedly enter and exit the test mode to improve the efficiency of chip testing and improve the utilization efficiency of chips.

In combination with the above description, the pin multiplexing module 1102 of the embodiment of the present application will be described in detail below.

Specifically, the pin multiplexing module 1102 can be specifically used to detect the first signal through M pins; the first signal can be used to trigger the pin multiplexing module 110 to control M first switch modules and M second switch modules. The switch module can be used by allocating M pins to the chip testing module 1101 or M chip functional units.

It should be noted that the pin multiplexing module 1102 of the present application can detect external signals of the chip 10 through the M pins to determine whether to allocate the M pins to the chip testing module 1101 or to M chip function modules. .

For example, if the chip 10 needs to enter the test mode, and the pin multiplexing module 1102 detects the first signal through M pins, the pin multiplexing module 1102 controls M first switch modules and M second switch modules To allocate M pins to the chip testing module 1101 for use.

If the chip 10 needs to enter the working mode, or the chip 10 needs to enter the working mode from the test mode, and the pin multiplexing module 1102 detects the first signal through the M pins, then the pin multiplexing module 1102 controls the M pins. A switch module and M second switch modules are used to allocate M pins to M chip functional units.

Optionally, the first signal may include a pull-up voltage signal or a pull-down voltage signal.

Wherein, if the pin multiplexing module 1102 detects the pull-up voltage signal outside the chip 10 through the M pins, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to convert M pins are assigned to the chip testing module 1101; if the pin multiplexing module 1102 detects the pull-down voltage signal outside the chip 10 through M pins, then the pin multiplexing module 1102 controls M first switch modules and M A second switch module is used to allocate M pins to M chip functional units.

Similarly, when the pull-down voltage is applied to the M pins outside the chip 10, the M pins are assigned to the chip testing module 1101 for use, and there is no specific limitation on this.

Exemplarily, please refer to FIG. 3 . The chip 10 is in a standby state after being powered on. When a wake-up signal is generated, the chip 10 enters the detection state, and in the detection state, the external signals applied to the M pins are detected by the pin multiplexing module 1102 .

If the pin multiplexing module 1102 detects the pull-up voltage signal through the M pins, then control M first switch modules and M second switch modules to assign M pins to the chip test module 1101 for use, thereby It is realized that the chip 10 enters the test mode.

If the pin multiplexing module 1102 detects the pull-down voltage signal through the M pins, then control M first switch modules and M second switch modules to allocate M pins to M chip functional units for use, thereby It is realized that the chip 10 enters the working mode.

If the chip 10 needs to enter the working mode from the test mode, and the pin multiplexing module 1102 detects the pull-down voltage signal through the M pins, then control the M first switch modules and the M second switch modules so that the M The pins are assigned to the M chip functional units, so that the chip 10 can enter the working mode from the test mode.

In the working mode, the chip 10 can choose whether to enter the standby state according to the current state, so as to continuously circulate, thereby ensuring the random switching of the chip 10 between the test mode and the working mode according to actual needs, and realizing the multiplexing of M pins Purpose.

Specifically, the pin multiplexing module 1102 can be specifically used to detect whether there is a second signal within a preset time through the M pins; the second signal can be used to trigger the pin multiplexing module 1102 to control the M first The switch module and M second switch modules are used to assign M pins to the chip test module; wherein, if the second signal is detected within the preset time, the pin multiplexing module 1102 assigns the M pins to The chip testing module 1101 uses it; if the second signal is not detected within a preset time, the pin multiplexing module 1102 allocates M pins to M chip functional units for use.

It should be noted that, different from the above, this application also considers that there is no need to detect external signals to trigger the pin multiplexing module 1102 to allocate M pins to M chip functional units, but directly through the preset It is determined whether a second signal is detected within the time. If the second signal is detected within the preset time, M pins are assigned to the chip testing module 1101 for use; if the second signal is not detected within the preset time, then M pins are assigned to M chips Functional units are used, which is beneficial to improve processing efficiency.

Optionally, the second signal may include a pull-up voltage signal or a pull-down voltage signal.

Wherein, if the pull-up voltage signal is detected within the preset time, the pin multiplexing module 1102 will allocate M pins to the chip testing module 1101 by controlling M first switch modules and M second switch modules. ; If the pull-up voltage signal is not detected within the preset time, the pin multiplexing module 1102 will distribute M pins to M chip functional units by controlling M first switch modules and M second switch modules use.

Exemplarily, please refer to FIG. 4 . The chip 10 is in a standby state after being powered on. When a wake-up signal is generated, the chip 10 enters the detection state, and in the detection state, the pin multiplexing module 1102 detects whether external signals are applied to the M pins PIN within a preset time.

If the pin multiplexing module 1102 detects the second signal through the M pins within the preset time, then control M first switch modules and M second switch modules to distribute M pins to the chip test module 1101 is used, so that the chip 10 enters the test mode.

If the pin multiplexing module 1102 does not detect the pull-up voltage signal through the M pins within the preset time, then control M first switch modules and M second switch modules to assign M pins to M Each chip functional unit is used, so that the chip 10 enters the working mode.

If the chip 10 needs to enter the working mode by the test mode, then by detecting the signal to exit the test mode (the first signal can be detected by the pin multiplexing module 1102 to exit the test mode, and the signal can also be detected by the chip test module 1101 to exit the test mode, which will be described in detail below), so as to realize that the chip 10 enters the working mode from the test mode.

In the working mode, the chip 10 can choose whether to enter the standby state according to the current state, so as to continuously cycle, so as to ensure random switching between the test mode and the working mode according to actual needs, and realize the purpose of multiplexing the M pins.

In combination with the above description, the chip testing module 1101 of the embodiment of the present application will be described in detail below.

Specifically, the chip test module 1101 can be specifically used to detect the third signal through the M pins when the M pins are allocated to the chip test module 1101; the third signal can be used to trigger the chip test module 1101 to send a signal to the pin The multiplexing module 1102 sends a fourth signal; the fourth signal is used to trigger the pin multiplexing module 1102 to allocate M pins to M chip functional units by controlling M first switch modules and M second switch modules. .

It should be noted that the M pins are allocated to the chip testing module 1101, which can be understood as that the chip testing module 1101 multiplexes the corresponding pins of the M chip functional units, or the chip 10 enters the testing mode. Therefore, when the chip 10 needs to enter the working mode from the test mode, the chip test module 1101 can detect the third signal through the M pins, and the third signal triggers the chip test module 1101 to send the fourth signal to the pin multiplexing module 1102 , and finally the fourth signal triggers the pin multiplexing module 1102 to allocate M pins to M chip functional units, so that the chip 10 enters the working mode from the test mode.

Optionally, the third signal may include at least one of the following: an internal integrated circuit (Inter-Integrated Circuit, I2C) protocol signal, a serial peripheral interface (Serial Peripheral Interface, SPI) protocol signal, a joint test working group (Joint Test Action Group, JTAG) protocol signal.

It should be noted that if the third signal includes an I2C protocol signal, and the I2C protocol is usually a two-wire serial bus, then the value of M can be 2, that is, the chip test module reuses the existing two chip functions of the chip 10 The corresponding pins of the units are used to implement the chip 10 from the test mode to the working mode through the two-wire communication protocol (I2C).

If the third signal includes an SPI protocol signal, and the SPI protocol is usually a three-wire or four-wire serial bus, then the value of M can be 3 or 4, that is, the chip test module reuses the existing 3 or 4 of the chip 10. The corresponding pins of the functional units of the chip realize that the chip 10 enters the working mode from the test mode through the three-wire or four-wire communication protocol (SIP).

If the third signal includes a JTAG protocol signal, and the JTAG protocol is usually a four-wire serial bus, then the value of M can be 4, that is, the chip test module reuses the existing 4 chip functional units corresponding to each of the chip 10. pins, so as to realize that the chip 10 enters the working mode from the test mode through the four-wire communication protocol (JTAG).

Optionally, the fourth signal may be determined by a protocol interface supported by the chip testing module 1101 and the pin multiplexing module 1102, such as a serial interface, a synchronous serial interface, and an I2C protocol interface.

For example, please refer to FIG. 5 or FIG. 6 . 3 or 4 above, in FIG. 5 or 6, if the chip 10 needs to enter the working mode from the test mode, and the pin multiplexing module 1102 detects the third signal through the M pins, the chip The test module 1101 sends a fourth signal to the pin multiplexing module 1102, and the pin multiplexing module 110 controls M first switch modules and M second switch modules to distribute M pins to M chip functional units use, so that the chip 10 enters the working mode.

Specifically, the chip testing module 1101 can be specifically used to detect the fifth signal through the M pins when the M pins are assigned to the chip testing module 1101; the fifth signal can be used to determine the chip testing strategy for the chip, The chip testing strategy includes at least one of the following: reading the internal operating state of the chip, debugging and calibrating the internal circuit of the chip, and writing configuration parameters to the memory of the chip.

Wherein, the configuration parameters can be used to update and upgrade the chip 10, detect the chip, and so on.

It should be noted that, when the chip test module 1101 multiplexes the corresponding pins of the M chip functional units, or the chip 10 enters the test mode, the chip test module 1101 can detect the fifth signal through the M pins To read the internal operating status of the chip 10, debug and calibrate the internal circuit of the chip 10, write configuration parameters to the memory of the chip 10, etc.

Optionally, the fifth signal may include at least one of the following: an I2C protocol signal, an SPI protocol signal, and a JTAG protocol signal.

It should be noted that if the fifth signal includes an I2C protocol signal, and the I2C protocol is usually a two-wire serial bus, then the value of M can be 2, that is, the chip test module reuses the existing two chip functions of the chip 10 The corresponding pins of the units are used to realize the chip test on the chip 10 through the two-wire communication protocol (I2C).

If the fifth signal includes the SPI protocol signal, and the SPI protocol is usually a three-wire or four-wire serial bus, then the value of M can be 3 or 4, that is, the chip test module reuses the existing 3 or 4 of the chip 10. The corresponding pins of the functional units of the chip can realize the chip test on the chip 10 through the three-wire or four-wire communication protocol (SIP).

If the fifth signal includes a JTAG protocol signal, and the JTAG protocol is usually a four-wire serial bus, then the value of M can be 4, that is, the chip test module reuses the existing 4 chip functional units corresponding to each of the chip 10. pins, so as to implement the chip test on the chip 10 through the four-wire communication protocol (JTAG).

Consistent with the above-mentioned embodiments, the following embodiments of the present application will introduce the execution steps of the above-mentioned chip testing and pin multiplexing unit from the perspective of a method example, please refer to FIG. 7 . FIG. 7 is a schematic flow chart of a method for chip testing and pin multiplexing provided in the embodiment of the present application. The method is applied to a chip 10. The chip 10 includes M chip functional units, M pins, and chip testing and pin multiplexing. With the unit 110, the chip functional units correspond to the pins one by one, and the chip testing and pin multiplexing unit 110 may include a chip testing module 1101, a pin multiplexing module 1102, M first switch modules and M second switch modules , the value of M is an integer greater than 1, and the value of N is twice the value of M; the method includes the following steps:

S710. When the chip is powered on and in the standby state, receive a wake-up signal, and the wake-up signal is used to trigger the chip to enter the detection state.

S720. When the chip enters the detection state, control M first switch modules and M second switch modules through the signals detected by the pin multiplexing module from M pins so that the chip test module multiplexes M chips The corresponding pins of the functional units.

It should be noted that, firstly, the chip 10 needs to detect the wake-up signal in the standby state, and enter the detection state from the standby state after detecting the wake-up signal. Wherein, the wake-up signal can be determined by the communication protocol supported by the internal mode of the chip 10 , such as serial signal, synchronous serial signal and so on.

Secondly, the chip 10 performs signal detection in the detection state to determine whether to enter the detection state or the working state. Wherein, in the test mode, the chip 10 can perform a chip test through the chip test module; in the working mode, the chip 10 can perform related chip functions through M chip functional units.

Finally, the pin multiplexing module 1102 in the chip 10 controls the M first switch modules and M second switch modules so that the chip test module 1101 multiplexes the corresponding pins of the M chip functional units, so that the chip 10 After entering the test mode, the chip test module 1101 finally performs a chip test on the chip 10 through the multiplexed M pins.

It can be seen that this application achieves chip testing by multiplexing the pins corresponding to the existing chip functional units of the chip, without adding additional independent pins for chip testing, thereby helping to reduce chip design, packaging and integration. The pins on the link are beneficial to reduce the size of the chip and reduce the cost of chip design, integration and packaging.

In addition, since the pin multiplexing module can control M first switch modules and M second switch modules, M pins can be repeatedly allocated to the chip test module for use, thereby ensuring that the chip can be repeatedly entered and exited Test mode, improve the efficiency of chip testing, and improve the utilization efficiency of chips.

Specifically, the signals detected from the M pins by the pin multiplexing module in S730 are used to control M first switch modules and M second switch modules so that the chip test module multiplexes the M chip functional units The corresponding pins may include: the first signal is detected from the M pins through the pin multiplexing module, and the first signal may be used to trigger the pin multiplexing module by controlling M first switch modules and M The second switch module is used for allocating M pins to the chip testing module or M chip functional units.

It should be noted that the pin multiplexing module 1102 of the present application can detect external signals of the chip 10 through the M pins to determine whether to allocate the M pins to the chip testing module 1101 or to M chip function modules. .

For example, if the chip 10 needs to enter the test mode, and the pin multiplexing module 1102 detects the first signal through M pins, the pin multiplexing module 1102 controls M first switch modules and M second switch modules To allocate M pins to the chip testing module 1101 for use.

If the chip 10 needs to enter the working mode, or the chip 10 needs to enter the working mode from the test mode, and the pin multiplexing module 1102 detects the first signal through the M pins, then the pin multiplexing module 1102 controls the M pins. A switch module and M second switch modules are used to allocate M pins to M chip functional units.

Optionally, the first signal may include a pull-up voltage signal or a pull-down voltage signal.

Wherein, if the pin multiplexing module 1102 detects the pull-up voltage signal outside the chip 10 through the M pins, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to convert M pins are assigned to the chip testing module 1101; if the pin multiplexing module 1102 detects the pull-down voltage signal outside the chip 10 through M pins, then the pin multiplexing module 1102 controls M first switch modules and M A second switch module is used to allocate M pins to M chip functional units.

Similarly, when the pull-down voltage is applied to the M pins outside the chip 10, the M pins are assigned to the chip testing module 1101 for use, and there is no specific limitation on this.

For example, please refer to the above-mentioned FIG. 3 , which will not be repeated here.

Specifically, the signals detected from the M pins by the pin multiplexing module in S730 are used to control M first switch modules and M second switch modules so that the chip test module multiplexes the M chip functional units The corresponding pins may include: detecting whether there is a second signal from the M pins within a preset time through the pin multiplexing module, and the second signal can be used to trigger the pin multiplexing module to control the M pins A switch module and M second switch modules are used to assign M pins to the chip test module; wherein, if the second signal is detected within the preset time, the M pins are assigned to the chip test module; If the second signal is not detected within the preset time, the M pins are allocated to the M chip functional units.

It should be noted that, different from the above, this application also considers that there is no need to detect external signals to trigger the pin multiplexing module 1102 to allocate M pins to M chip functional units, but directly through the preset It is determined whether a second signal is detected within the time. If the second signal is detected within the preset time, M pins are assigned to the chip testing module 1101 for use; if the second signal is not detected within the preset time, then M pins are assigned to M chips Functional units are used, which is beneficial to improve processing efficiency.

Optionally, the second signal may include a pull-up voltage signal or a pull-down voltage signal.

Wherein, if the pull-up voltage signal is detected within the preset time, the pin multiplexing module 1102 will allocate M pins to the chip testing module 1101 by controlling M first switch modules and M second switch modules. ; If the pull-up voltage signal is not detected within the preset time, the pin multiplexing module 1102 will distribute M pins to M chip functional units by controlling M first switch modules and M second switch modules use.

For example, please refer to the above-mentioned FIG. 4 , which will not be repeated here.

Specifically, the present application may also include: when the chip test module multiplexes the corresponding pins of the M chip functional units, the chip test module detects the third signal from the M pins, and the third signal is used to trigger the chip The test module sends a fourth signal to the pin multiplexing module, and the fourth signal is used to trigger the pin multiplexing module to allocate M pins to M chips by controlling M first switch modules and M second switch modules Functional unit used.

It should be noted that the M pins are allocated to the chip testing module 1101, which can be understood as that the chip testing module 1101 multiplexes the corresponding pins of the M chip functional units, or the chip 10 enters the testing mode. Therefore, when the chip 10 needs to enter the working mode from the test mode, the chip test module 1101 can detect the third signal through the M pins, and the third signal triggers the chip test module 1101 to send the fourth signal to the pin multiplexing module 1102 , and finally the fourth signal triggers the pin multiplexing module 1102 to allocate M pins to M chip functional units, so that the chip 10 enters the working mode from the test mode.

Optionally, the third signal may include at least one of the following: an I2C protocol signal, an SPI protocol signal, and a JTAG protocol signal.

It should be noted that, in this application, the chip 10 can be implemented from the test mode to the working mode through the two-wire communication protocol (I2C), through the three-wire or four-wire communication protocol (SIP, JTAG).

Optionally, the fourth signal may be determined by a protocol interface supported by the chip testing module 1101 and the pin multiplexing module 1102, such as a serial interface, a synchronous serial interface, and an I2C protocol interface.

For example, please refer to the above-mentioned FIG. 5 or FIG. 6 , which will not be repeated here.

Specifically, the present application may also include: when the chip test module multiplexes the corresponding pins of the M chip functional units, the chip test module detects the fifth signal from the M pins, and the fifth signal is used to determine the A chip testing strategy for the chip. The chip testing strategy includes at least one of the following: reading the internal operating state of the chip, debugging and calibrating the internal circuit of the chip, and writing configuration parameters to the memory of the chip.

Wherein, the configuration parameters can be used to update and upgrade the chip 10, detect the chip, and so on.

It should be noted that, when the chip test module 1101 multiplexes the corresponding pins of the M chip functional units, or the chip 10 enters the test mode, the chip test module 1101 can detect the fifth signal through the M pins To read the internal operating status of the chip 10, debug and calibrate the internal circuit of the chip 10, write configuration parameters to the memory of the chip 10, etc.

Optionally, the fifth signal may include at least one of the following: an I2C protocol signal, an SPI protocol signal, and a JTAG protocol signal.

It should be noted that the present application can implement chip testing on the chip 10 through the two-wire communication protocol (I2C), three-wire or four-wire communication protocol (SIP, JTAG), such as reading the internal operating state of the chip, debugging and calibrating the chip. Internal circuits, programming configuration parameters to the memory of the chip, etc.

The chip testing and pin multiplexing unit and the chip testing and pin multiplexing method provided in the embodiments of the present application have been described in detail above. The principles and implementation methods involved in the embodiments of the present application are described in this paper using specific examples. Explanation, the description of the above embodiment is only used to help understand the method and core idea of the embodiment of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the embodiment of the present application, both the specific implementation method and the scope of application There may be changes. In summary, the content of this specification should not be construed as limiting the embodiment of the application.

Claims (10)

1. A chip test and pin multiplexing unit is characterized in that,

the chip testing and pin multiplexing unit is applied to a chip, wherein the chip comprises M chip functional units, M pins and the chip testing and pin multiplexing unit, and the chip functional units correspond to the pins one to one; the chip testing and pin multiplexing unit comprises a chip testing circuit, a pin multiplexing circuit, M first switch circuits and M second switch circuits, wherein the value of M is an integer greater than 1;

the chip test circuit is connected with the M pins through the M first switch circuits and the pin multiplexing circuit;

the chip functional units are respectively connected with one corresponding pin of the chip functional unit through one second switch circuit and the pin multiplexing circuit;

the pin multiplexing circuit is respectively connected with M pins, M first switch circuits and M second switch circuits;

the chip test circuit is used for multiplexing the pins corresponding to the M chip functional units to perform chip test on the chip;

the chip function unit is used for executing the chip functions of the chip function unit;

the pin multiplexing circuit is configured to control the M first switch circuits and the M second switch circuits so that the chip testing circuit multiplexes the pins corresponding to the M chip functional units.

2. The chip test and pin multiplexing unit of claim 1, wherein the pin multiplexing circuit is specifically configured to detect the first signal through M of the pins;

the first signal is used for triggering the pin multiplexing circuit to distribute M pins to the chip testing circuit or M chip functional units for use by controlling M first switch circuits and M second switch circuits.

3. The chip test and pin multiplexing unit of claim 2, wherein the first signal comprises a pull-up voltage signal or a pull-down voltage signal.

4. The chip test and pin multiplexing unit according to any one of claims 1 to 3, wherein the pin multiplexing circuit is specifically configured to detect whether a second signal is present through the M pins within a preset time;

the second signal is used for triggering the pin multiplexing circuit to distribute M pins to the chip test circuit for use by controlling M first switch circuits and M second switch circuits; wherein,

if the second signal is detected within the preset time, the pin multiplexing circuit allocates M pins to the chip test circuit for use;

and if the second signal is not detected within the preset time, the pin multiplexing circuit allocates the M pins to the M chip functional units for use.

5. The chip test and pin multiplexing unit according to any one of claims 1 to 4, wherein the chip test circuit is specifically configured to detect a third signal via the M pins when the M pins are allocated to the chip test circuit;

the third signal is used for triggering the chip test circuit to send a fourth signal to the pin multiplexing circuit;

the fourth signal is used for triggering the pin multiplexing circuit to distribute M pins to M chip functional units for use by controlling M first switch circuits and M second switch circuits.

6. The chip test and pin multiplexing unit of claim 5, wherein the third signal comprises at least one of: an inter-integrated circuit I2C protocol signal, a serial peripheral interface SPI protocol signal and a joint test work group JTAG protocol signal.

7. The chip test and pin multiplexing unit according to any one of claims 1 to 4, wherein the chip test circuit is specifically configured to detect a fifth signal via the M pins when the M pins are allocated to the chip test circuit;

the fifth signal is used to determine a chip test strategy for the chip, the chip test strategy including at least one of: reading the internal running state of the chip, debugging and calibrating the internal circuit of the chip, and programming configuration parameters to the memory of the chip.

8. A chip testing and pin multiplexing method is characterized in that the method is applied to a chip, the chip comprises M chip functional units, M pins and a chip testing and pin multiplexing unit, the chip functional units correspond to the pins one by one, the chip testing and pin multiplexing unit comprises a chip testing circuit, a pin multiplexing circuit, M first switch circuits and M second switch circuits, the value of M is an integer larger than 1, and the value of N is 2 times of the value of M; the method comprises the following steps:

receiving a wake-up signal when the chip is powered on and in a standby state, wherein the wake-up signal is used for triggering the chip to enter a detection state;

when the chip enters the detection state, the M first switch circuits and the M second switch circuits are controlled by signals detected from the M pins by the pin multiplexing circuit, so that the chip testing circuit multiplexes the pins corresponding to the M chip functional units.

9. The method of claim 8, wherein the controlling the M first switch circuits and the M second switch circuits by the signals detected from the M pins by the pin multiplexing circuit to cause the chip testing circuit to multiplex the pins corresponding to each of the M chip functional units comprises:

detecting a first signal from the M pins by the pin multiplexing circuit, wherein the first signal is used for triggering the pin multiplexing circuit to allocate the M pins to the chip testing circuit or the M chip functional units for use by controlling the M first switch circuits and the M second switch circuits; or,

detecting whether a second signal exists in the M pins within a preset time through the pin multiplexing circuit, wherein the second signal is used for triggering the pin multiplexing circuit to distribute the M pins to the chip test circuit for use by controlling the M first switch circuits and the M second switch circuits; if the second signal is detected within the preset time, distributing the M pins to the chip test circuit for use; and if the second signal is not detected within the preset time, distributing the M pins to the M chip functional units for use.

10. A chip comprising M chip functional units, M pins, and the chip testing and pin multiplexing unit according to any one of claims 1 to 7, wherein the chip functional units and the pins are in one-to-one correspondence, and a value of M is an integer greater than 1.

Images