CN205749803U - Civil Satellite Communication baseband chip - Google Patents
Civil Satellite Communication baseband chip Download PDFInfo
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- CN205749803U CN205749803U CN201620407892.1U CN201620407892U CN205749803U CN 205749803 U CN205749803 U CN 205749803U CN 201620407892 U CN201620407892 U CN 201620407892U CN 205749803 U CN205749803 U CN 205749803U
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Abstract
This utility model provides a kind of Civil Satellite Communication baseband chip, relates to IC chip field.This Civil Satellite Communication baseband chip is applied to functional mode or test pattern, include 295 pins altogether, the pin of this Civil Satellite Communication baseband chip is carried out multiplexing, number of pins can be reduced, reduce chip production cost, decrease the package area of chip, reduce technical staff's time cost during encapsulation and human cost, and beneficially satellite communication equipment Miniaturization Design.
Description
Technical field
This utility model relates to IC chip field, in particular to a kind of Civil Satellite Communication baseband chip.
Background technology
Satellite communication is to utilize the telecommunication satellite operating on terrestrial space track to forward wireless signal, it is achieved ground two point
Or a kind of communication mode of multi-point communication.On satellite communication equipment the most on the ground, Civil Satellite Communication base band is installed
Chip, to realize above-mentioned communication.
For Civil Satellite Communication baseband chip, the highest to the performance requirement of chip, and Civil Satellite Communication base
It is complicated that band algorithm realizes logic, so that the number of pins of Civil Satellite Communication baseband chip is numerous, chip package area is big,
Thus causing the packaging cost of chip higher, encapsulation difficulty is the biggest, thus causes technical staff during encapsulation, needs
Time cost that will be the biggest and human cost.
Utility model content
The purpose of this utility model is to provide a kind of Civil Satellite Communication baseband chip, to improve above-mentioned problem.
This utility model is achieved in that
A kind of Civil Satellite Communication baseband chip, this Civil Satellite Communication baseband chip is applied to functional mode or test
Pattern, includes 295 pins altogether, and in the functional mode, this Civil Satellite Communication baseband chip includes:
Radio frequency interface, for carrying out data transmission with radio frequency chip；
Peripheral Interface, for carrying out data transmission with ancillary equipment；
Mode selection interface, for selecting clock module, reset mode, start-up mode；
Described test pattern includes scan logic pattern, MBIST (memory built in self test of sram) pattern, boundary scan pattern
And macroelement test pattern,
Under scan logic pattern, this Civil Satellite Communication baseband chip includes: scan logic interface, for civilian to this
Satellite communication baseband chip carries out scan logic test；
Under MBIST (memory built in self test of sram) pattern, this Civil Satellite Communication baseband chip includes: MBIST (storage
Device built-in self-test) interface, for the memory module of this Civil Satellite Communication baseband chip is tested；
Under boundary scan pattern, this Civil Satellite Communication baseband chip includes: boundary scan interface, for I/O pin
Test；
Under macroelement test pattern, this Civil Satellite Communication baseband chip includes: macroelement test interface, for right
USB controller or PLL (phaselocked loop) or ROM carry out macroelement test.
Further, described radio frequency interface includes CSM-RF interface, BD-RF interface and GSM-RF interface.
Further, described CSM-RF interface includes that 26 pins, described BD-RF interface include 15 pins, described
GSM-RF interface includes 20 pins.
Further, described Peripheral Interface includes LCD interface, NandFlash interface, CMOS Sensor interface, SD clamping
Mouth, SIM interface, keyboard interface, jtag interface, I2S interface, RTC interface, USB interface and ddr interface.
Further, described LCD interface includes 22 pins, and described CMOS Sensor interface includes 14 pins, described
NandFlash interface includes that 22 pins, described SD card interface include that 14 pins, described SIM interface include 8 pins,
10 pins of described keyboard interface, described jtag interface includes that 10 pins, described I2S interface include 15 pins, described RTC
Interface includes 3 pins, and described USB interface includes 3 pins, and described ddr interface includes 76 pins.
Further, described mode selection interface includes: RTC interface, reseting interface and BOOT interface.
Further, described RTC interface includes 3 pins, and described reseting interface includes 2 pins, described BOOT interface
Including 8 pins.
Further, described scan logic interface includes LCD interface, NandFlash interface, CMOS Sensor interface, SD
Card interface, SIM interface, CSM-RF interface, BD-RF interface and GSM-RF interface, ARM11JTAG interface, BOOT interface, multiple
Position interface, keyboard interface, I2C interface, I2S interface, SPI interface and UART interface.
Further, described MBIST (memory built in self test of sram) interface include LCD interface, NandFlash interface,
CMOS Sensor interface, SD card interface, CSM-RF interface, GSM-RF interface, BOOT interface, reseting interface, keyboard interface and
I2S interface.
Further, described boundary scan interface includes that described boundary scan interface includes that ARM11JTAG interface, BOOT connect
Mouthful.
Hinge structure, this utility model has the advantages that the offer one that this utility model provides is civilian
Satellite communication baseband chip, is both meeting the function of satellite communication, is meeting again the measurability of this Civil Satellite Communication baseband chip
Under requirement, the pin of this chip is carried out multiplexing under functional mode and different test patterns, has simplified number of pins, reduce
Chip production cost, decreases the package area of chip, reduce technical staff's time cost during encapsulation and
Human cost, and beneficially satellite communication equipment Miniaturization Design.
For making above-mentioned purpose of the present utility model, feature and advantage to become apparent, preferred embodiment cited below particularly, and
Coordinate appended accompanying drawing, be described in detail below.
Accompanying drawing explanation
For making the purpose of this utility model embodiment, technical scheme and advantage clearer, new below in conjunction with this practicality
Accompanying drawing in type embodiment, is clearly and completely described the technical scheme in this utility model embodiment, it is clear that retouched
The embodiment stated is a part of embodiment of this utility model rather than whole embodiments.Generally described in the accompanying drawing herein and
The assembly of this utility model embodiment illustrated can be arranged with various different configurations and design.Therefore, below to attached
The detailed description of the embodiment of the present utility model provided in figure is not intended to limit claimed scope of the present utility model,
But it is merely representative of selected embodiment of the present utility model.Based on the embodiment in this utility model, ordinary skill people
The every other embodiment that member is obtained under not making creative work premise, broadly falls into the model of this utility model protection
Enclose.
Fig. 1 is that the pin multiplexing structure showing a kind of Civil Satellite Communication baseband chip provided by the utility model is shown
It is intended to.
Detailed description of the invention
Below in conjunction with accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out clearly
Chu, it is fully described by, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole realities
Execute example.Generally can be next with various different configurations with the assembly of this utility model embodiment illustrated described in accompanying drawing herein
Arrange and design.Therefore, below the detailed description of the embodiment of the present utility model provided in the accompanying drawings is not intended to limit
Claimed scope of the present utility model, but it is merely representative of selected embodiment of the present utility model.Based on this utility model
Embodiment, the every other embodiment that those skilled in the art are obtained on the premise of not making creative work, all
Belong to the scope of this utility model protection.
It should also be noted that similar label and letter represent similar terms, therefore, the most a certain Xiang Yi in following accompanying drawing
Individual accompanying drawing is defined, then need not it be defined further and explains in accompanying drawing subsequently.Meanwhile, new in this practicality
In the description of type, term " first ", " second " etc. are only used for distinguishing and describe, and it is not intended that indicate or imply relatively important
Property.
Satellite communication is to utilize the telecommunication satellite operating on terrestrial space track to forward wireless signal, it is achieved ground two point
Or a kind of communication mode of multi-point communication.On satellite communication equipment the most on the ground, Civil Satellite Communication base band is installed
Chip, to realize above-mentioned communication.For Civil Satellite Communication baseband chip, the highest to the performance requirement of chip, and
It is complicated that Civil Satellite Communication Baseband algorithms realizes logic, so that the number of pins of Civil Satellite Communication baseband chip is numerous,
Chip package area is big, thus causes the packaging cost of chip higher, and encapsulation difficulty is the biggest, thus causes technical staff to exist
During encapsulation, need the biggest time cost and human cost.
In view of this, inventor observes and research discovery through long-term, it is provided that this Civil Satellite Communication base band core a kind of
Sheet is applied to functional mode or test pattern, includes 295 pins altogether, enters the pin of this Civil Satellite Communication baseband chip
Row multiplexing, can reduce number of pins, reduces chip production cost, decreases the package area of chip, reduces technical staff
Time cost during encapsulation and human cost, and beneficially satellite communication equipment Miniaturization Design.
Below by specific embodiment and combine accompanying drawing this utility model is described in further detail.
Refering to Fig. 1, a kind of Civil Satellite Communication baseband chip that this utility model embodiment one provides, this commercial satellite leads to
Letter baseband chip model is HTD1001, and this Civil Satellite Communication baseband chip is applied to functional mode or test pattern, altogether bag
Including 295 pins, these 295 pins carry out multiplexing respectively under functional mode and test pattern, and in the functional mode, this is civilian
Satellite communication baseband chip includes:
Radio frequency interface, for carrying out data transmission with radio frequency chip；
Peripheral Interface, for carrying out data transmission with ancillary equipment；
Mode selection interface, for selecting clock module, reset mode, start-up mode；
Described test pattern includes scan logic pattern, MBIST (memory built in self test of sram) pattern, boundary scan pattern
And macroelement test pattern,
Under scan logic pattern, this Civil Satellite Communication baseband chip includes: scan logic interface, for civilian to this
Satellite communication baseband chip carries out scan logic test；
Under MBIST (memory built in self test of sram) pattern, this Civil Satellite Communication baseband chip includes: MBIST (storage
Device built-in self-test) interface, for the memory module of this Civil Satellite Communication baseband chip is tested；
Under boundary scan pattern, this Civil Satellite Communication baseband chip includes: boundary scan interface, for I/O pin
Test；
Under macroelement test pattern, this Civil Satellite Communication baseband chip includes: macroelement test interface, for right
USB controller or PLL (phaselocked loop) or ROM carry out macroelement test.
Further, referring to table 1, in the functional mode, described radio frequency interface includes CSM-RF interface, BD-RF interface
And GSM-RF interface, described CSM-RF interface includes that 20 pins, described BD-RF interface include 15 pins, described GSM-
RF interface includes 26 pins.Described Peripheral Interface includes LCD interface, NandFlash interface, CMOS Sensor interface, SD card
Interface, SIM interface, keyboard interface, jtag interface, I2S interface, RTC interface, USB interface and ddr interface.Described LCD connects
Mouth includes that 22 pins, described CMOS Sensor interface include that 14 pins, described NandFlash interface include 22 pins,
Described SD card interface includes that 14 pins, described SIM interface include 8 pins, and 10 pins of described keyboard interface are described
Jtag interface includes that 10 pins, described I2S interface include 15 pins, and described RTC interface includes 3 pins, and described USB connects
Mouth includes 3 pins, and described ddr interface includes 76 pins.Described mode selection interface includes: RTC interface is (when being used for selecting
Clock pattern), reseting interface (being used for selecting reset mode) and BOOT interface (being used for selecting start-up mode).Described RTC interface
Including 3 pins, described reseting interface includes that 2 pins, described BOOT interface include 8 pins.
| Pin is classified | Number of pins | Pin is explained |
| LCD interface | 22 | 16 bit data |
| NandFlash interface | 22 | 16 bit data |
| SD card interface | 14 | 2 groups |
| SIM interface | 8 | 2 groups |
| GSM-RF interface | 20 | Half-duplex |
| CSM-RF interface | 26 | Satellite communication radio frequency interface |
| ANTI interface | 23 | Anti-interference chip interface |
| BD-RF interface | 15 | Navigation radio frequency interface |
| UART interface | 14 | 1 group of band stream control, 5 groups of common interfaces |
| SPI interface | 6 | 4 line SPI |
| I2C interface | 6 | 3 groups |
| Keyboard interface | 10 | 5x5 |
| I2S interface | 15 | 3 groups |
| Reseting interface | 2 | 1 input, 1 output |
| ARM11JTAG interface | 5 | Standard JTAG |
| BOOT interface | 8 | Start-up mode selects, and starts information, and test enables |
| RTC and power supply control interface | 8 | 32KHz clock, LDO enables |
| USB interface | 3 | Standard USB interface |
| Ddr interface | 76 | Compatible LPDDR2, DDR3 |
| Add up to | 295 |
Table 1
Referring to Fig. 1, in the functional mode, the function selecting of each reusable pin is independent configurable, passes through
The different configurations that pin function selects, can combine multiple application scheme, be advantageously implemented satellite communication, satellite navigation, ground
Communicating integral, is advantageously implemented hand-held, portable, vehicle-mounted, boat-carrying, airborne solution, be advantageously implemented voice, short message,
The business realizing such as fax.
Referring to table 2, table 2 is itemized under the functional mode 0 (func0 pattern) of this Civil Satellite Communication baseband chip
Radio frequency interface 11, Peripheral Interface 12, common interfaces 13 pin assignments synopsis, specifically comprise LCD interface, NandFlash interface,
CMOS Sensor interface, 2 groups of SD card interfaces, 2 groups of SIM interfaces, GSM-RF interface, CSM-RF interface, BD-RF interface, 6 groups
UART interface, 2 groups of SPI interface, 3 groups of I2C interfaces, keyboard interfaces, 3 groups of I2S interfaces, reseting interface, 2 groups of ARM-JTAG interfaces,
BOOT interface, RTC interface, USB interface and ddr interface, the signal under concrete pin sequence number, pin title, func0 pattern
Title and pin describe as shown in table 2.
Table 2
Referring to table 3, table 3 is itemized in pin assignments comparison under functional mode 1 (func1 pattern), specifically includes LCD
Interface, NandFlash interface, CMOS Sensor interface, SD card interface, SIM interface, ARM11JTAG interface, BOOT interface,
Reseting interface, keyboard interface, I2C interface, I2S interface, SPI interface and UART interface, concrete pin sequence number, pin name
Signal name and pin under title, func1 pattern describe as shown in table 3, and wherein, "/" represents this pin the most not
Used.
Table 3
Referring to table 4, table 4 is itemized in pin assignments synopsis under functional mode 2 (func2 pattern), specifically comprises
Specifically comprise LCD interface, NandFlash interface, SD card interface, CSM-RF interface, ARM11JTAG interface, I2C interface, I2S connect
Mouth and UART interface.Signal name and pin under concrete pin sequence number, pin title, func2 pattern describe such as table 4
Shown in, wherein, "/" represents that this pin is not used by such a mode.
Table 4
Referring to table 5, table 5 is itemized in pin assignments synopsis under functional mode 3 (func3 pattern), specifically comprises
LCD interface, NandFlash interface, CMOS Sensor interface, CSM-RF interface, GSM-RF interface, BOOT interface, reset connect
Mouth, keyboard interface, I2C interface, I2S interface and UART interface, under concrete pin sequence number, pin title, func3 pattern
Signal name and pin describe as shown in table 5, and wherein, "/" represents that this pin is not used by such a mode.
Table 5
Referring to table 6, table 6 is itemized in pin assignments synopsis under functional mode 4 (func4 pattern), LCD interface,
NandFlash interface, CMOS Sensor interface, BD-RF interface, keyboard interface, I2C interface, I2S interface, SPI interface and
UART interface, signal name and pin under concrete pin sequence number, pin title, func4 pattern describe, as shown in table 6,
Wherein, "/" represents that this pin is not used by such a mode.
Table 6
Referring to table 7, table 7 is itemized in pin assignments synopsis under functional mode 5 (func5 pattern), LCD interface,
Reseting interface, I2C interface and I2S interface, signal name under concrete pin sequence number, pin title, func5 pattern and
Pin describes, and as shown in table 7, wherein, "/" represents that this pin is not used by such a mode.
Table 7
Referring to table 8, table 8 is itemized in pin assignments synopsis under functional mode 6 (func6 pattern), CMOS
Sensor interface, SD card interface, CSM-RF interface, BD-RF interface, keyboard interface, I2C interface and I2S interface, concrete pipe
Signal name and pin under foot sequence number, pin title, func6 pattern describe, and as shown in table 8, wherein, "/" represents this pipe
Foot is not used by such a mode.
| Sequence number | Pin title | Signal name under func6 pattern | Describe |
| 1 | LCD interface | / | / |
| 2 | NandFlash interface | / | / |
| 3 | CMOS Sensor | dbg_bus[13:0] | |
| 4 | SD card interface | dbg_bus[26:14] | |
| 5 | SIM interface | / | / |
| 6 | GSM-RF interface | / | / |
| 7 | CSM-RF interface | PWM11,12,13,14 | |
| 8 | BD-RF interface | dbg_bus[31:28] | |
| 9 | UART interface | / | / |
| 10 | SPI interface | / | / |
| 11 | I2C interface | bd_gpio[7:6] | |
| 12 | Keyboard interface | CLKOUT[3:0] | |
| 13 | I2S interface | dbg_clk_out[3:0] | |
| 14 | Reseting interface | / | / |
| 15 | ARM jtag interface | / | / |
| 16 | BOOT interface | / | / |
Table 8
Referring to table 9, table 9 is itemized in pin assignments synopsis under functional mode 7 (func7 pattern), LCD interface,
NandFlash interface, CSM-RF interface and BD-RF interface, the letter under concrete pin sequence number, pin title, func7 pattern
Number title and pin describe, and as shown in table 9, wherein, "/" represents that this pin is not used by such a mode.
| Sequence number | Pin title | Signal name under func7 pattern | Describe |
| 1 | LCD interface | dbg_bus[15:0] | |
| 2 | NandFlash interface | dbg_bus[26:16] | |
| 3 | CMOS Sensor | / | / |
| 4 | SD card interface | / | / |
| 5 | SIM interface | / | / |
| 6 | GSM-RF interface | / | / |
| 7 | CSM-RF interface | dbg_clk_out[3:0] | |
| 8 | BD-RF interface | dbg_bus[31:27] | |
| 9 | UART interface | / | / |
| 10 | SPI interface | / | / |
| 11 | I2C interface | / | / |
| 12 | Keyboard interface | / | / |
| 13 | I2S interface | / | / |
| 14 | Reseting interface | / | / |
| 15 | ARM jtag interface | / | / |
| 16 | BOOT interface | / | / |
Table 9
Referring to Fig. 1, when this Civil Satellite Communication baseband chip is in test pattern, described test pattern includes logic
Scan pattern, MBIST (memory built in self test of sram) pattern, boundary scan pattern and macroelement test pattern, according to test
Enabling the state of (TESTEN), when test enables invalid, pin (PAD) is used as functional mode (func), and pin can be used as 8
Functional mode interface (func0 pattern is to func7 pattern)；When test enables effective, pin is used as test pattern (test), then
Selecting (TEST_MODE) according to test pattern, under different test patterns, the part pin of 295 pins can be used separately as
Scan logic interface (scan), MBIST mode interface (MBIST), boundary scan interface (BSD), 2 macroelement test interfaces
(Macro 0, Macro 1).
Further, under scan logic pattern, this Civil Satellite Communication baseband chip includes: described scan logic connects
Mouthful, described scan logic interface includes that LCD interface, NandFlash interface, CMOS Sensor interface, SD card interface, SIM connect
Mouth, CSM-RF interface, BD-RF interface and GSM-RF interface, ARM11JTAG interface, BOOT interface, reseting interface, keyboard connect
Mouth, I2C interface, I2S interface, SPI interface and UART interface, the pin assignments of described scan logic interface, as shown in table 10,
Wherein, "/" represents that this pin is not used by such a mode.
Table 10
Further, under MBIST (memory built in self test of sram) pattern, this Civil Satellite Communication baseband chip includes:
MBIST (memory built in self test of sram) interface, this MBIST (memory built in self test of sram) interface include LCD interface,
NandFlash interface, CMOS Sensor interface, SD card interface, CSM-RF interface, GSM-RF interface, BOOT interface, reset connect
Mouth, keyboard interface and I2S interface, the pin assignments of described MBIST (memory built in self test of sram) interface is as shown in table 11, its
In, "/" represents that this pin is not used by such a mode.
Table 11
Further, under boundary scan pattern, this Civil Satellite Communication baseband chip includes: boundary scan interface, institute
State boundary scan interface and include ARM11JTAG interface, BOOT interface, the pin assignments such as table of described boundary scan interface (BSD)
Shown in 12, wherein, "/" represents that this pin is not used by such a mode.
Table 12
Further, macroelement test pattern includes that macroelement tests 0 pattern and macroelement tests 1 pattern, this macroelement
Test interface is the test of macroelement in chip, under macroelement tests 0 pattern, and this Civil Satellite Communication baseband chip bag
Including: macroelement test interface 0 (Macro 0), macroelement test interface 0 (Macro 0) includes that LCD interface, NandFlash connect
Mouth, CMOS Sensor interface, SD card interface, CSM-RF interface, BD-RF interface, GSM-RF interface, BOOT interface and UART
Interface, table 13 lists the pin assignments of macroelement test interface 0 (Macro 0), and wherein, "/" represents that this pin is in this pattern
Under be not used by.
Table 13
Further, under macroelement tests 0 pattern, this Civil Satellite Communication baseband chip includes: macroelement test connects
Mouth 1 (Macro 1), macroelement test interface 1 (Macro 1) includes that LCD interface, NandFlash interface, CMOS Sensor connect
Mouth, SD card interface, BOOT interface, keyboard interface, I2C interface, SPI interface and UART interface, table 14 lists macroelement and surveys
Trying the pin assignments of mouth 1 (Macro 1), wherein, "/" represents that this pin is not used by such a mode.
Table 14
The offer one Civil Satellite Communication baseband chip that this utility model provides, is both meeting the function of satellite communication,
Meet again under the measurability of this Civil Satellite Communication baseband chip requires, to the pin of this chip in functional mode and different surveys
Carry out multiplexing under die trial formula, simplified number of pins, reduce chip production cost, decrease the package area of chip, reduce
Technical staff's time cost during encapsulation and human cost, and beneficially satellite communication equipment miniaturization sets
Meter.
In description of the present utility model, in addition it is also necessary to explanation, unless otherwise clearly defined and limited, term " sets
Put ", should be interpreted broadly " installation ", " being connected ", " connection ", connect for example, it may be fixing, it is also possible to be to removably connect,
Or be integrally connected；Can be to be mechanically connected, it is also possible to be electrical connection；Can be to be joined directly together, it is also possible to pass through intermediary
It is indirectly connected to, can be the connection of two element internals.For the ordinary skill in the art, can manage with concrete condition
Solve above-mentioned term concrete meaning in this utility model.
It should also be noted that similar label and letter represent similar terms, therefore, the most a certain Xiang Yi in following accompanying drawing
Individual accompanying drawing is defined, then need not it be defined further and explains in accompanying drawing subsequently.
In description of the present utility model, " " center ", " on ", D score, "left", "right", " perpendicular it should be noted that term
Directly ", " level ", " interior ", the orientation of the instruction such as " outward " or position relationship be based on orientation shown in the drawings or position relationship, or
It is the orientation or position relationship usually put during the use of this utility model product, is for only for ease of description this utility model and letter
Change describe rather than instruction or the hint device of indication or element must have specific orientation, with specific azimuth configuration and
Operation, therefore it is not intended that to restriction of the present utility model.Additionally, term " first ", " second ", " the 3rd " etc. are only used for district
Divide and describe, and it is not intended that indicate or hint relative importance.
The foregoing is only preferred embodiment of the present utility model, be not limited to this utility model, for this
For the technical staff in field, this utility model can have various modifications and variations.All in spirit of the present utility model and principle
Within, any modification, equivalent substitution and improvement etc. made, within should be included in protection domain of the present utility model.
The foregoing is only preferred embodiment of the present utility model, be not limited to this utility model, for this
For the technical staff in field, this utility model can have various modifications and variations.All in spirit of the present utility model and principle
Within, any modification, equivalent substitution and improvement etc. made, within should be included in protection domain of the present utility model.It should be noted that
Arrive: similar label and letter represent similar terms in following accompanying drawing, therefore, are determined in the most a certain Xiang Yi accompanying drawing
Justice, then need not define it further and explain in accompanying drawing subsequently.
The above, detailed description of the invention the most of the present utility model, but protection domain of the present utility model does not limit to
In this, any those familiar with the art, in the technical scope that this utility model discloses, can readily occur in change
Or replace, all should contain within protection domain of the present utility model.Therefore, protection domain of the present utility model should be described with power
The protection domain that profit requires is as the criterion.
Claims (10)
1. a Civil Satellite Communication baseband chip, this Civil Satellite Communication baseband chip is applied to functional mode or test mould
Formula, it is characterised in that including 295 pins altogether, in the functional mode, this Civil Satellite Communication baseband chip includes:
Radio frequency interface, for carrying out data transmission with radio frequency chip；
Peripheral Interface, for carrying out data transmission with ancillary equipment；
Mode selection interface, for selecting clock module, reset mode, start-up mode；
Described test pattern includes scan logic pattern, MBIST pattern, boundary scan pattern and macroelement test pattern,
Under scan logic pattern, this Civil Satellite Communication baseband chip includes: scan logic interface, for this commercial satellite
Communications baseband chip carries out scan logic test；
Under MBIST pattern, this Civil Satellite Communication baseband chip includes: MBIST interface, for this Civil Satellite Communication base
The memory module of microarray strip is tested；
Under boundary scan pattern, this Civil Satellite Communication baseband chip includes: boundary scan interface, for carrying out I/O pin
Test；
Under macroelement test pattern, this Civil Satellite Communication baseband chip includes: macroelement test interface, for controlling USB
Device processed or phaselocked loop or ROM carry out macroelement test.
Civil Satellite Communication baseband chip the most according to claim 1, it is characterised in that described radio frequency interface includes CSM-
RF interface, BD-RF interface and GSM-RF interface.
Civil Satellite Communication baseband chip the most according to claim 2, it is characterised in that described CSM-RF interface includes
26 pins, described BD-RF interface includes that 15 pins, described GSM-RF interface include 20 pins.
Civil Satellite Communication baseband chip the most according to claim 1, it is characterised in that described Peripheral Interface includes LCD
Interface, NandFlash interface, CMOS Sensor interface, SD card interface, SIM interface, keyboard interface, jtag interface, I2S connect
Mouth, RTC interface, USB interface and ddr interface.
Civil Satellite Communication baseband chip the most according to claim 4, it is characterised in that described LCD interface includes 22
Pin, described CMOS Sensor interface includes that 14 pins, described NandFlash interface include 22 pins, described SD clamping
Mouth includes that 14 pins, described SIM interface include 8 pins, and 10 pins of described keyboard interface, described jtag interface includes
10 pins, described I2S interface includes 15 pins, and described RTC interface includes 3 pins, and described USB interface includes 3 pipes
Foot, described ddr interface includes 76 pins.
Civil Satellite Communication baseband chip the most according to claim 1, it is characterised in that described mode selection interface bag
Include: RTC interface, reseting interface and BOOT interface.
Civil Satellite Communication baseband chip the most according to claim 6, it is characterised in that described RTC interface includes 3 pipes
Foot, described reseting interface includes that 2 pins, described BOOT interface include 8 pins.
Civil Satellite Communication baseband chip the most according to claim 1, it is characterised in that described scan logic interface includes
LCD interface, NandFlash interface, CMOS Sensor interface, SD card interface, SIM interface, CSM-RF interface, BD-RF interface
And GSM-RF interface, ARM11JTAG interface, BOOT interface, reseting interface, keyboard interface, I2C interface, I2S interface, SPI connect
Mouth and UART interface.
Civil Satellite Communication baseband chip the most according to claim 1, it is characterised in that described MBIST (memory built
Self-test) interface includes LCD interface, NandFlash interface, CMOS Sensor interface, SD card interface, CSM-RF interface, GSM-
RF interface, BOOT interface, reseting interface, keyboard interface and I2S interface.
Civil Satellite Communication baseband chip the most according to claim 1, it is characterised in that described boundary scan interface bag
Include ARM11 jtag interface, BOOT interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620407892.1U CN205749803U (en) | 2016-05-06 | 2016-05-06 | Civil Satellite Communication baseband chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620407892.1U CN205749803U (en) | 2016-05-06 | 2016-05-06 | Civil Satellite Communication baseband chip |
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| Publication Number | Publication Date |
|---|---|
| CN205749803U true CN205749803U (en) | 2016-11-30 |
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| CN201620407892.1U Active CN205749803U (en) | 2016-05-06 | 2016-05-06 | Civil Satellite Communication baseband chip |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109286597A (en) * | 2017-07-20 | 2019-01-29 | 北京中科晶上科技股份有限公司 | A kind of baseband chip |
| CN109739803A (en) * | 2018-12-03 | 2019-05-10 | 中国科学院国家空间科学中心 | A kind of configurable general asic chip integrated on a small scale |
| CN113419164A (en) * | 2021-08-24 | 2021-09-21 | 深圳英集芯科技股份有限公司 | Chip test and pin multiplexing unit and chip test and pin multiplexing method |
| CN114567369A (en) * | 2022-02-21 | 2022-05-31 | 北京国电高科科技有限公司 | Half-duplex data forwarding method and system for satellite Internet of things |
| CN115085800A (en) * | 2022-07-27 | 2022-09-20 | 平安银行股份有限公司 | Ground satellite equipment, satellite transit monitoring method and storage medium |
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2016
- 2016-05-06 CN CN201620407892.1U patent/CN205749803U/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109286597A (en) * | 2017-07-20 | 2019-01-29 | 北京中科晶上科技股份有限公司 | A kind of baseband chip |
| CN109739803A (en) * | 2018-12-03 | 2019-05-10 | 中国科学院国家空间科学中心 | A kind of configurable general asic chip integrated on a small scale |
| CN109739803B (en) * | 2018-12-03 | 2023-05-12 | 中国科学院国家空间科学中心 | Configurable universal small-scale integrated ASIC chip |
| CN113419164A (en) * | 2021-08-24 | 2021-09-21 | 深圳英集芯科技股份有限公司 | Chip test and pin multiplexing unit and chip test and pin multiplexing method |
| CN114567369A (en) * | 2022-02-21 | 2022-05-31 | 北京国电高科科技有限公司 | Half-duplex data forwarding method and system for satellite Internet of things |
| CN114567369B (en) * | 2022-02-21 | 2022-11-22 | 北京国电高科科技有限公司 | Half-duplex data forwarding method and system for satellite Internet of things |
| CN115085800A (en) * | 2022-07-27 | 2022-09-20 | 平安银行股份有限公司 | Ground satellite equipment, satellite transit monitoring method and storage medium |
| CN115085800B (en) * | 2022-07-27 | 2022-11-29 | 平安银行股份有限公司 | Ground satellite equipment, satellite transit monitoring method and storage medium |
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Inventor after: Liu Jiehua Inventor after: Ma Wenbo Inventor after: Jing Jun Inventor after: Jiang Ke Inventor before: Liu Jiehua Inventor before: Ma Wenbo Inventor before: Jing Jun |
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Effective date of registration: 20200728 Address after: 610000 Sichuan city of Chengdu province Tianfu Zheng Xing Shun Shing Street No. 172 Patentee after: Huali Zhixin (Chengdu) integrated circuit Co., Ltd Address before: 100080, No. 18, building No. 8, hospital B, West Wang Xi Road, Haidian District, Beijing Patentee before: HWA CREATE Corp.,Ltd. |