CN205749909U - satellite communication navigation chip - Google Patents
satellite communication navigation chip Download PDFInfo
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- CN205749909U CN205749909U CN201620407872.4U CN201620407872U CN205749909U CN 205749909 U CN205749909 U CN 205749909U CN 201620407872 U CN201620407872 U CN 201620407872U CN 205749909 U CN205749909 U CN 205749909U
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Abstract
This utility model provides a kind of satellite communication navigation chip, relates to IC chip field.This satellite communication navigation chip application is in functional mode or test pattern, include 204 pins altogether, the pin of this satellite communication navigation chip is carried out multiplexing, number of pins can be reduced, reduce chip production cost, decrease the package area of chip, reduce technical staff's time cost during encapsulation and human cost, and beneficially satellite communication equipment Miniaturization Design.
Description
Technical field
This utility model relates to IC chip field, in particular to a kind of satellite communication navigation chip.
Background technology
Satellite communication is to utilize the telecommunication satellite operating on terrestrial space track to forward wireless signal, it is achieved ground two point
Or a kind of communication mode of multi-point communication.On satellite communication equipment the most on the ground, satellite communication navigation core is installed
Sheet, to realize above-mentioned communication.
Along with developing rapidly of airmanship, the function of aeronautical satellite communication and navigation chip and collection are the most increasingly
Greatly.At present aeronautical satellite communication and navigation integrated chip is for numerous functions of navigation, and has general interface for extending.
Along with the growth of the market demand, the function of aeronautical satellite communication and navigation integrated chip gets more and more, as integrated multiple tracking cell,
There is multiple PRM interface, support various communication interfaces, multiple external connection interface section etc..Along with the increase of functional integration, core
The number of pin of sheet is consequently increased.
The aeronautical satellite communication and navigation chip of general integrated level of the prior art needs the number of pin up to 400 drawn
Multiple, so that the number of pins of dual-use satellite communication navigation chip is numerous, chip package area is big, thus causes core
The packaging cost of sheet is higher, and encapsulation difficulty is the biggest, thus cause technical staff during encapsulation, when needing the biggest
Between cost and human cost.
Utility model content
The purpose of this utility model there are provided a kind of satellite communication navigation chip, to improve above-mentioned problem.
This utility model is achieved in that
A kind of satellite communication navigation chip, this satellite communication navigation chip application is in functional mode or test pattern, altogether
Including 204 pins, in the functional mode, this satellite communication navigation chip includes:
Radio frequency interface, for carrying out data transmission with a radio frequency chip；
Peripheral Interface, for carrying out data transmission with ancillary equipment；
Mode selection interface, for selecting clock module, reset mode, start-up mode；
Described test pattern includes scan logic pattern, MBIST (memory built in self test of sram) pattern, boundary scan pattern
And macroelement test pattern,
Under scan logic pattern, this satellite communication navigation chip includes: scan logic interface, for this satellite communication
Navigation chip carries out scan logic test；
Under MBIST pattern, this satellite communication navigation chip includes: MBIST interface, for this satellite communication navigation core
The memory module of sheet is tested；
Under boundary scan pattern, this satellite communication navigation chip includes: boundary scan interface, for carrying out I/O pin
Test；
Under macroelement test pattern, this satellite communication navigation chip includes: macroelement test interface, for controlling USB
Device processed or PLL (phaselocked loop) or ROM carry out macroelement test.
Further, described radio frequency interface includes ANTI_RF interface, USER_RF interface and RDSS_RF interface.
Further, described ANTI_RF interface includes that 13 pins, described USER_RF interface include 20 pins, described
RDSS_RF interface includes 15 pins.
Further, described Peripheral Interface includes that SD card interface, SIM interface, jtag interface, PRM interface and RTC connect
Mouthful.
Further, described SD card interface includes that 7 pins, described SIM interface include 8 pins, and described JTAG connects
Mouth includes 5 pins, 68 pins of described PRM interface, and described RTC interface includes 3 pins.
Further, described mode selection interface includes that UART interface, SPI interface, I2C interface, RST interface, BOOT connect
Mouth, GPIO interface, PAD_PROG interface, CLK interface, PPS interface and TEST interface.
Further, described UART interface includes 18 pins, and described SPI interface includes 16 pins, described I2C interface
Including 4 pins, described RST interface includes that 1 pin, described BOOT interface include 5 pins, described GPIO interface 16 pipe
Foot, described PAD_PROG interface includes that 1 pin, described CLK interface include that 1 pin, described PPS interface include 2 pins,
Described TEST interface includes 1 pin.
Further, described scan logic interface includes ANTI_RF interface, USER_RF interface, RDSS_RF interface, SD card
Interface, SIM interface, jtag interface, PRM interface, UART interface, SPI interface, I2C interface, RST interface, BOOT interface,
GPIO interface, PAD_PROG interface, CLK interface and PPS interface.
Further, described MBIST interface includes that ANTI_RF interface, USER_RF interface, RDSS_RF interface, PRM connect
Mouth, SPI interface, CLK interface and TEST interface.
Further, described boundary scan interface includes jtag interface.
Hinge structure, this utility model has the advantages that the offer one satellite that this utility model provides
Communication and navigation chip, is both meeting the navigation feature of satellite communication, is meeting again the measurability requirement of this satellite communication navigation chip
Under, the pin of this chip is carried out multiplexing under functional mode and different test patterns, has simplified number of pins, reduced core
Sheet production cost, decreases the package area of chip, reduces technical staff's time cost during encapsulation and manpower
Cost, and beneficially satellite communication equipment Miniaturization Design.
For making above-mentioned purpose of the present utility model, feature and advantage to become apparent, preferred embodiment cited below particularly, and
Coordinate appended accompanying drawing, be described in detail below.
Accompanying drawing explanation
For making the purpose of this utility model embodiment, technical scheme and advantage clearer, new below in conjunction with this practicality
Accompanying drawing in type embodiment, is clearly and completely described the technical scheme in this utility model embodiment, it is clear that retouched
The embodiment stated is a part of embodiment of this utility model rather than whole embodiments.Generally described in the accompanying drawing herein and
The assembly of this utility model embodiment illustrated can be arranged with various different configurations and design.Therefore, below to attached
The detailed description of the embodiment of the present utility model provided in figure is not intended to limit claimed scope of the present utility model,
But it is merely representative of selected embodiment of the present utility model.Based on the embodiment in this utility model, ordinary skill people
The every other embodiment that member is obtained under not making creative work premise, broadly falls into the model of this utility model protection
Enclose.
Fig. 1 shows the pin multiplexing structural representation of a kind of satellite communication navigation chip provided by the utility model.
Detailed description of the invention
Below in conjunction with accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out clearly
Chu, it is fully described by, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole realities
Execute example.Generally can be next with various different configurations with the assembly of this utility model embodiment illustrated described in accompanying drawing herein
Arrange and design.Therefore, below the detailed description of the embodiment of the present utility model provided in the accompanying drawings is not intended to limit
Claimed scope of the present utility model, but it is merely representative of selected embodiment of the present utility model.Based on this utility model
Embodiment, the every other embodiment that those skilled in the art are obtained on the premise of not making creative work, all
Belong to the scope of this utility model protection.
It should also be noted that similar label and letter represent similar terms, therefore, the most a certain Xiang Yi in following accompanying drawing
Individual accompanying drawing is defined, then need not it be defined further and explains in accompanying drawing subsequently.Meanwhile, new in this practicality
In the description of type, term " first ", " second " etc. are only used for distinguishing and describe, and it is not intended that indicate or imply relatively important
Property.
In view of this, inventor observes and research discovery through long-term, it is provided that this satellite communication navigation chip a kind of, should
Satellite communication navigation chip application, in functional mode or test pattern, includes 204 pins altogether, to this satellite communication navigation core
The pin of sheet carries out multiplexing, can reduce number of pins, reduces chip production cost, decreases the package area of chip, reduces
Technical staff's time cost during encapsulation and human cost, and beneficially satellite communication equipment miniaturization sets
Meter.
Below by specific embodiment and combine accompanying drawing this utility model is described in further detail.
Refering to Fig. 1, a kind of satellite communication navigation chip that this utility model embodiment one provides, be applied to functional mode or
Person's test pattern, includes 204 pins altogether, and in the functional mode, this satellite communication navigation chip includes:
Radio frequency interface, for carrying out data transmission with a radio frequency chip；
Peripheral Interface, for carrying out data transmission with ancillary equipment；
Mode selection interface, for selecting clock module, reset mode, start-up mode；
Described test pattern includes scan logic pattern, memory built in self test of sram (MBIST, Memory Build-in
Self Test) pattern, boundary scan pattern and macroelement test pattern；
Under scan logic pattern, this satellite communication navigation chip includes: scan logic interface, for this satellite communication
Navigation chip carries out scan logic test；
Under MBIST pattern, this satellite communication navigation chip includes: MBIST interface, for this satellite communication navigation core
The memory module of sheet is tested；
Under boundary scan pattern, this satellite communication navigation chip includes: boundary scan interface, for carrying out I/O pin
Test；
Under macroelement test pattern, this satellite communication navigation chip includes: macroelement test interface, for controlling USB
Device processed or PLL (phaselocked loop) or ROM carry out macroelement test.
Further, referring to table 1, in the functional mode, described radio frequency interface includes that ANTI_RF interface, USER_RF connect
Mouth and RDSS_RF interface.Described ANTI_RF interface includes that 13 pins, described USER_RF interface include 20 pins, institute
State RDSS_RF interface and include 15 pins.Described Peripheral Interface includes SD card interface, SIM interface, jtag interface, PRM interface
And RTC interface.Described SD card interface includes that 7 pins, described SIM interface include 8 pins, and described jtag interface includes
5 pins, 68 pins of described PRM interface, described RTC interface includes 3 pins.Described mode selection interface includes that UART connects
Mouth, SPI interface, I2C interface, RST interface, BOOT interface, GPIO interface, PAD_PROG interface, CLK interface, PPS interface and
TEST interface.Described UART interface includes 18 pins, and described SPI interface includes that 16 pins, described I2C interface include 4
Pin, described RST interface includes that 1 pin, described BOOT interface include 5 pins, and 16 pins of described GPIO interface are described
PAD_PROG interface includes that 1 pin, described CLK interface include that 1 pin, described PPS interface include 2 pins, described
TEST interface includes 1 pin.
| Pin is classified | Number of pins | Pin is explained |
| ANTI_RF interface | 13 | 12 bit data, 1 bit clock |
| USER_RF interface | 20 | 4 groups of x5 (4 bit data, 1 bit clock) |
| RDSS_RF interface | 15 | 12 bit data |
| SPI interface | 16 | 3 groups different |
| PRM interface | 68 | 2 groups of x34 |
| UART interface | 18 | 9 groups of x2 (2 bit data) |
| SIM interface | 8 | 2 groups of x4 |
| SD card interface | 7 | 1 group |
| I2C interface | 4 | 2 groups |
| GPIO interface | 16 | 16 |
| Jtag interface | 5 | 1 group |
| PAD_PROG interface | 1 | 1 |
| BOOT interface | 5 | Start-up mode selects, and starts information, and test enables |
| CLK interface | 1 | Output RF_CLK |
| PPS interface | 2 | 1 input, 1 output |
| RST interface | 1 | 1 |
| TEST interface | 1 | 1 |
| RTC interface | 3 | 32KHz clock, RTC resets |
| Add up to | 204 |
Table 1
Referring to Fig. 1, in the functional mode, the function selecting of each reusable pin is independent configurable, passes through
The different configurations that pin function selects, can combine multiple application scheme, be advantageously implemented satellite communication, satellite navigation, ground
Communicating integral, is advantageously implemented hand-held, portable, vehicle-mounted, boat-carrying, airborne solution, be advantageously implemented voice, short message,
The business realizing such as fax.This satellite communication navigation chip selects disparate modules in the functional mode by func_sel signal
Signal source, this signal bit wide is the selection that 3 bits can realize 8 functional modes, and using CPU to configure this signal at most can be real
The multiplexed port of existing 8 modules, including the multiplexing of general purpose I/O.This satellite communication navigation chip provides func_oen signal, in merit
Energy pattern is got off to realize the input and output of each module port and is controlled.When CPU configuration func_sel is a certain stuck-module,
It is input or output that func_oen signal can control the port of this module, when func_oen is that high point represents input at ordinary times,
Otherwise represent output.This satellite communication navigation chip is integrated with 5 road tracking modules, the wherein 4 each needs of road tracking module 4
Data pins and 1 clock pins are mutual with external radio frequency chip；Another road tracking module needs 12 anti-interference data pins
Mutual with external radio frequency chip with 1 clock pins.This satellite communication navigation chip is also integrated with RDSS function, needs 12 ways
Mutual with external radio frequency chip according to input, 1 circuit-switched data data output and 1 road clock.This satellite communication navigation chip also has two
Group PRM interface, each PRM members of a family comprise 32 circuit-switched data and 1 clock and 1 reset is mutual with outside PRM chip.This satellite
Communication and navigation chip also comprises interfaces such as organizing UART, SPI, SCI, SDIO, I2C, GPIO more can be mutual with external equipment.
Referring to table 2, table 2 is itemized in radio frequency under the functional mode 0 (func0 pattern) of this satellite communication navigation chip
Interface, Peripheral Interface, mode selection interface pin assignments synopsis.Under concrete pin sequence number, pin title, func0 pattern
Signal name and pin describe as shown in table 2.
Table 2
Referring to table 3, table 3 is itemized in pin assignments comparison, concrete pin under functional mode 1 (func1 pattern)
Signal name and pin under sequence number, pin title, func1 pattern describe as shown in table 3, and wherein, "/" represents that this pin exists
It is not used by under this pattern.
Table 3
Referring to table 4, table 4 is itemized in pin assignments synopsis under functional mode 2 (func2 pattern).Concrete pipe
Signal name and pin under foot sequence number, pin title, func2 pattern describe as shown in table 4, and wherein, "/" represents this pin
It is not used by such a mode.
Table 4
Referring to table 5, table 5 is itemized in pin assignments synopsis under functional mode 3 (func3 pattern), concrete pipe
Signal name and pin under foot sequence number, pin title, func3 pattern describe as shown in table 5, and wherein, "/" represents this pin
It is not used by such a mode.
Table 5
Referring to table 6, table 6 is itemized in pin assignments synopsis under functional mode 4 (func4 pattern), concrete pipe
Signal name and pin under foot sequence number, pin title, func4 pattern describe, and as shown in table 6, wherein, "/" represents this pipe
Foot is not used by such a mode.
Table 6
Referring to table 7, table 7 is itemized in pin assignments synopsis under functional mode 5 (func5 pattern), concrete pipe
Signal name and pin under foot sequence number, pin title, func5 pattern describe, and as shown in table 7, wherein, "/" represents this pipe
Foot is not used by such a mode.
Table 7
Referring to table 8, table 8 is itemized in pin assignments synopsis under functional mode 6 (func6 pattern), concrete pipe
Signal name and pin under foot sequence number, pin title, func6 pattern describe, and as shown in table 8, wherein, "/" represents this pipe
Foot is not used by such a mode.
Table 8
Referring to table 9, table 9 is itemized in pin assignments synopsis under functional mode 7 (func7 pattern), concrete pipe
Signal name and pin under foot sequence number, pin title, func7 pattern describe, and as shown in table 9, wherein, "/" represents this pipe
Foot is not used by such a mode.
Table 9
Referring to Fig. 1, when this satellite communication navigation chip is in test pattern, described test pattern includes scan logic
Pattern, MBIST pattern, boundary scan pattern and macroelement test pattern, enable the state of (TESTEN), work as survey according to test
When examination enables invalid, pin (PAD) is used as functional mode (func), and pin can be used as 8 functional mode interface (func0 patterns
To func7 pattern)；When test enables effective, pin is used as test pattern (test), selects (TEST_ further according to test pattern
MODE), under different test patterns, the part pin of 303 pins can be used separately as scan logic interface (scan),
MBIST mode interface (MBIST), boundary scan interface (BSD), macroelement test interface.
Further, under scan logic pattern, this satellite communication navigation chip includes: described scan logic interface, institute
Stating the pin assignments of scan logic interface, as shown in table 10, wherein, "/" represents that this pin is not used by such a mode.
Table 10
Further, under MBIST pattern, this satellite communication navigation chip includes: MBIST interface, described MBIST interface
Pin assignments as shown in table 11, wherein, "/" represents that this pin is not used by such a mode.
Table 11
Further, under boundary scan pattern, this satellite communication navigation chip includes: boundary scan interface, described limit
Boundary's scan interface includes ARM11JTAG interface, and the pin assignments of described boundary scan interface (BSD) is as shown in table 12, wherein,
"/" represents that this pin is not used by such a mode.
Table 12
Further, macroelement test pattern includes that macroelement tests 0 pattern, under macroelement tests 0 pattern, and this satellite
Communication and navigation chip includes: macroelement test interface 0 (Macro 0), and this macroelement test interface is macroelement in chip
Test, table 13 lists the pin assignments of macroelement test interface 0, and wherein, "/" represents that this pin is not made
With.
Table 13
The offer one satellite communication navigation chip that this utility model provides, is both meeting the navigation feature of satellite communication,
Meet again under the measurability of this satellite communication navigation chip requires, to the pin of this chip at functional mode and different test moulds
Carry out multiplexing under formula, simplified number of pins, reduce chip production cost, decrease the package area of chip, reduce skill
Art personnel time cost during encapsulation and human cost, and beneficially satellite communication equipment Miniaturization Design.
In description of the present utility model, in addition it is also necessary to explanation, unless otherwise clearly defined and limited, term " sets
Put ", should be interpreted broadly " installation ", " being connected ", " connection ", connect for example, it may be fixing, it is also possible to be to removably connect,
Or be integrally connected；Can be to be mechanically connected, it is also possible to be electrical connection；Can be to be joined directly together, it is also possible to pass through intermediary
It is indirectly connected to, can be the connection of two element internals.For the ordinary skill in the art, can manage with concrete condition
Solve above-mentioned term concrete meaning in this utility model.
It should also be noted that similar label and letter represent similar terms, therefore, the most a certain Xiang Yi in following accompanying drawing
Individual accompanying drawing is defined, then need not it be defined further and explains in accompanying drawing subsequently.
In description of the present utility model, " " center ", " on ", D score, "left", "right", " perpendicular it should be noted that term
Directly ", " level ", " interior ", the orientation of the instruction such as " outward " or position relationship be based on orientation shown in the drawings or position relationship, or
It is the orientation or position relationship usually put during the use of this utility model product, is for only for ease of description this utility model and letter
Change describe rather than instruction or the hint device of indication or element must have specific orientation, with specific azimuth configuration and
Operation, therefore it is not intended that to restriction of the present utility model.Additionally, term " first ", " second ", " the 3rd " etc. are only used for district
Divide and describe, and it is not intended that indicate or hint relative importance.
The foregoing is only preferred embodiment of the present utility model, be not limited to this utility model, for this
For the technical staff in field, this utility model can have various modifications and variations.All in spirit of the present utility model and principle
Within, any modification, equivalent substitution and improvement etc. made, within should be included in protection domain of the present utility model.
The foregoing is only preferred embodiment of the present utility model, be not limited to this utility model, for this
For the technical staff in field, this utility model can have various modifications and variations.All in spirit of the present utility model and principle
Within, any modification, equivalent substitution and improvement etc. made, within should be included in protection domain of the present utility model.It should be noted that
Arrive: similar label and letter represent similar terms in following accompanying drawing, therefore, are determined in the most a certain Xiang Yi accompanying drawing
Justice, then need not define it further and explain in accompanying drawing subsequently.
The above, detailed description of the invention the most of the present utility model, but protection domain of the present utility model does not limit to
In this, any those familiar with the art, in the technical scope that this utility model discloses, can readily occur in change
Or replace, all should contain within protection domain of the present utility model.Therefore, protection domain of the present utility model should be described with power
The protection domain that profit requires is as the criterion.
Claims (10)
1. a satellite communication navigation chip, this satellite communication navigation chip application is in functional mode or test pattern, and it is special
Levying and be, include 204 pins altogether, in the functional mode, this satellite communication navigation chip includes:
Radio frequency interface, for carrying out data transmission with a radio frequency chip；
Peripheral Interface, for carrying out data transmission with ancillary equipment；
Mode selection interface, for selecting clock module, reset mode, start-up mode；
Described test pattern includes scan logic pattern, MBIST pattern, boundary scan pattern and macroelement test pattern,
Under scan logic pattern, this satellite communication navigation chip includes: scan logic interface, for this satellite communication navigation
Chip carries out scan logic test；
Under MBIST pattern, this satellite communication navigation chip includes: MBIST interface, for this satellite communication navigation chip
Memory module is tested；
Under boundary scan pattern, this satellite communication navigation chip includes: boundary scan interface, for surveying I/O pin
Examination；
Under macroelement test pattern, this satellite communication navigation chip includes: macroelement test interface, for USB controller
Or phaselocked loop or ROM carry out macroelement test.
Satellite communication navigation chip the most according to claim 1, it is characterised in that described radio frequency interface includes ANTI_RF
Interface, USER_RF interface and RDSS_RF interface.
Satellite communication navigation chip the most according to claim 2, it is characterised in that described ANTI_RF interface includes 13
Pin, described USER_RF interface includes that 20 pins, described RDSS_RF interface include 15 pins.
Satellite communication navigation chip the most according to claim 1, it is characterised in that described Peripheral Interface includes SD clamping
Mouth, SIM interface, jtag interface, PRM interface and RTC interface.
Satellite communication navigation chip the most according to claim 4, it is characterised in that described SD card interface includes 7 pins,
Described SIM interface includes 8 pins, and described jtag interface includes 5 pins, 68 pins of described PRM interface, described RTC
Interface includes 3 pins.
Satellite communication navigation chip the most according to claim 1, it is characterised in that described mode selection interface includes UART
Interface, SPI interface, I2C interface, RST interface, BOOT interface, GPIO interface, PAD_PROG interface, CLK interface, PPS interface with
And TEST interface.
Satellite communication navigation chip the most according to claim 6, it is characterised in that described UART interface includes 18 pipes
Foot, described SPI interface includes that 16 pins, described I2C interface include that 4 pins, described RST interface include 1 pin, described
BOOT interface includes 5 pins, 16 pins of described GPIO interface, and described PAD_PROG interface includes 1 pin, described CLK
Interface includes that 1 pin, described PPS interface include that 2 pins, described TEST interface include 1 pin.
Satellite communication navigation chip the most according to claim 1, it is characterised in that described scan logic interface includes
ANTI_RF interface, USER_RF interface, RDSS_RF interface, SD card interface, SIM interface, jtag interface, PRM interface, UART
Interface, SPI interface, I2C interface, RST interface, BOOT interface, GPIO interface, PAD_PROG interface, CLK interface and PPS connect
Mouthful.
Satellite communication navigation chip the most according to claim 1, it is characterised in that described MBIST interface includes ANTI_RF
Interface, USER_RF interface, RDSS_RF interface, PRM interface, SPI interface, CLK interface and TEST interface.
Satellite communication navigation chip the most according to claim 1, it is characterised in that described boundary scan interface includes
Jtag interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620407872.4U CN205749909U (en) | 2016-05-06 | 2016-05-06 | satellite communication navigation chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620407872.4U CN205749909U (en) | 2016-05-06 | 2016-05-06 | satellite communication navigation chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205749909U true CN205749909U (en) | 2016-11-30 |
Family
ID=57370896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620407872.4U Active CN205749909U (en) | 2016-05-06 | 2016-05-06 | satellite communication navigation chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205749909U (en) |
-
2016
- 2016-05-06 CN CN201620407872.4U patent/CN205749909U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: HWA CREATE TECHNOLOGY CORPORATION LTD. Assignor: Beijing Hwa Create Co., Ltd. Contract record no.: 2018510000013 Denomination of utility model: Satellite communication chip that navigates Granted publication date: 20161130 License type: Exclusive License Record date: 20180301 |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| CB03 | Change of inventor or designer information |
Inventor after: Liu Jiehua Inventor after: Jiang Ke Inventor after: Ma Wenbo Inventor after: Jing Jun Inventor before: Liu Jiehua Inventor before: Ma Wenbo Inventor before: Jing Jun |
|
| CB03 | Change of inventor or designer information | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200728 Address after: 610000 Sichuan city of Chengdu province Tianfu Zheng Xing Shun Shing Street No. 172 Patentee after: Huali Zhixin (Chengdu) integrated circuit Co., Ltd Address before: 100080, No. 18, building No. 8, hospital B, West Wang Xi Road, Haidian District, Beijing Patentee before: HWA CREATE Corp.,Ltd. |
|
| TR01 | Transfer of patent right |