CN205749804U - Satellite antijam communication baseband chip - Google Patents
Satellite antijam communication baseband chip Download PDFInfo
- Publication number
- CN205749804U CN205749804U CN201620408507.5U CN201620408507U CN205749804U CN 205749804 U CN205749804 U CN 205749804U CN 201620408507 U CN201620408507 U CN 201620408507U CN 205749804 U CN205749804 U CN 205749804U
- Authority
- CN
- China
- Prior art keywords
- pin
- satellite
- test
- baseband chip
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
This utility model provides a kind of satellite antijam communication baseband chip, relates to IC chip field.This satellite antijam communication baseband chip is applied to functional mode or test pattern, include 23 pins altogether, the pin of this satellite antijam communication baseband chip is carried out multiplexing, number of pins can be reduced, reduce chip production cost, decrease the package area of chip, reduce technical staff's time cost during encapsulation and human cost, and beneficially satellite communication equipment Miniaturization Design.
Description
Technical field
This utility model relates to IC chip field, in particular to a kind of satellite antijam communication base band core
Sheet.
Background technology
Satellite communication is to utilize the telecommunication satellite operating on terrestrial space track to forward wireless signal, it is achieved ground two point
Or a kind of communication mode of multi-point communication.On satellite communication equipment the most on the ground, satellite antijam communication base is installed
Microarray strip, to realize above-mentioned communication.Satellite antijam communication baseband chip communication during, satellite antijam communication base
The up-link of microarray strip and downlink all can suffer from interference, therefore derived that to have the satellite of interference free performance anti-dry
Disturb communications baseband chip, outer signals can be avoided to disturb during satellite antijam communication baseband chip communication, it is achieved
The most real-time communication.
It is for the satellite antijam communication baseband chip with interference free performance, the highest to the performance requirement of chip,
And it is complicated that Anti-interference algorithm realizes logic, so that the number of pins of satellite antijam communication baseband chip is numerous, chip
Package area is big, thus causes the packaging cost of chip higher, and encapsulation difficulty is the biggest, thus causes technical staff encapsulating
During, need the biggest time cost and human cost, and the resource of satellite antijam communication baseband chip is disappeared
Consumption is big, power consumption is high.
Utility model content
The purpose of this utility model is to provide a kind of satellite antijam communication baseband chip, to improve above-mentioned problem.
This utility model is achieved in that
A kind of satellite antijam communication baseband chip, this satellite antijam communication baseband chip be applied to functional mode or
Test pattern, includes 23 pins altogether, and in the functional mode, this satellite antijam communication baseband chip includes:
Radio frequency interface, for carrying out data transmission with a radio frequency chip；
Control interface, control data and state observation data for transfer process；
Mode selection interface, for selecting clock module, reset mode, interrupt mode；
Described test pattern includes scan logic pattern, MBIST (memory built in self test of sram) pattern, input testing mode
And output test pattern,
Under scan logic pattern, this satellite antijam communication baseband chip includes: scan logic interface, for defending this
Star antijam communication baseband chip carries out scan logic test；
Under MBIST (memory built in self test of sram) pattern, this satellite antijam communication baseband chip includes: MBIST (deposits
Reservoir built-in self-test) interface, for the memory module of this satellite antijam communication baseband chip is tested；
Under input testing mode, this satellite antijam communication baseband chip includes: IO input interface, for I/O pin
Test during output signal；
Under output test pattern, this satellite antijam communication baseband chip includes: IO output interface, for I/O pin
Test during output signal.
Further, described radio frequency interface includes that 11 pins, described control interface include 7 pins, and described pattern is selected
Select interface and include 5 pins.
Further, described radio frequency interface includes 4 data out pin, 4 data in pin, and 1 sends enable
Pin, 1 receives enable pin, and 1 data is transmitted with road clock pins.
Further, described control interface includes 1 SPI chip selection signal pin, 1 SPI clock signal pin, 4 SPI
Data pins, 1 effective pin of SPI data.
Further, described mode selection interface includes 1 clock signal pin, 1 reset signal pin, 1 reception
Interrupt signal pin, 1 sends interrupt signal pin, and 1 test enables signal pin.
Further, described scan logic interface includes 22 pins, described MBIST (memory built in self test of sram) interface
Including 19 pins, described IO input interface includes that 23 pins, described IO output interface include 23 pins.
Further, described scan logic interface includes 7 scanning input pins, 7 scanning output pins, 1 scanning
Enable pin, 1 comp enable pin, 1 occ pattern pin, 1 scan clock pin, 1 scan reset pin, 2 surveys
Die trial formula base pin selection, 1 test enable pin.
Further, described MBIST (memory built in self test of sram) interface includes that 1 memory built in self test of sram enables pipe
Foot, 1 memory built in self test of sram failure signal pin, 1 memory built in self test of sram completes signal pin, and 1 displacement makes
Energy pin, 1 misr clock pins, 7 misr output pins, 1 PLL (phaselocked loop) output signal pin, 1 PLL is (phase-locked
Ring) locking signal pin, 1 memory built in self test of sram clock pins, 1 memory built in self test of sram reseting pin, 2 surveys
Die trial formula base pin selection, 1 test enable pin.
Further, described IO input interface includes 17 input signal pins, 1 and output pin, 1 or outlet tube
Foot, 2 test pattern base pin selections, 1 test enable pin.
Further, described IO output interface includes 19 clock division output pins, 1 clock input pin, 2 surveys
Die trial formula base pin selection, 1 test enable pin.
Hinge structure, this utility model has the advantages that the offer one satellite that this utility model provides
Antijam communication baseband chip, is both meeting the function of satellite communication, and meet again this satellite antijam communication baseband chip can
Under the property surveyed requires, the pin of this chip is carried out multiplexing under functional mode and different test patterns, has simplified number of pins,
Reduce chip production cost, decrease the package area of chip, reduce technical staff and become the time during encapsulation
Basis and human cost, and beneficially satellite communication equipment Miniaturization Design.
For making above-mentioned purpose of the present utility model, feature and advantage to become apparent, preferred embodiment cited below particularly, and
Coordinate appended accompanying drawing, be described in detail below.
Accompanying drawing explanation
For making the purpose of this utility model embodiment, technical scheme and advantage clearer, new below in conjunction with this practicality
Accompanying drawing in type embodiment, is clearly and completely described the technical scheme in this utility model embodiment, it is clear that retouched
The embodiment stated is a part of embodiment of this utility model rather than whole embodiments.Generally described in the accompanying drawing herein and
The assembly of this utility model embodiment illustrated can be arranged with various different configurations and design.Therefore, below to attached
The detailed description of the embodiment of the present utility model provided in figure is not intended to limit claimed scope of the present utility model,
But it is merely representative of selected embodiment of the present utility model.Based on the embodiment in this utility model, ordinary skill people
The every other embodiment that member is obtained under not making creative work premise, broadly falls into the model of this utility model protection
Enclose.
Fig. 1 is the pin multiplexing structure showing a kind of satellite antijam communication baseband chip provided by the utility model
Schematic diagram.
Detailed description of the invention
Below in conjunction with accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out clearly
Chu, it is fully described by, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole realities
Execute example.Generally can be next with various different configurations with the assembly of this utility model embodiment illustrated described in accompanying drawing herein
Arrange and design.Therefore, below the detailed description of the embodiment of the present utility model provided in the accompanying drawings is not intended to limit
Claimed scope of the present utility model, but it is merely representative of selected embodiment of the present utility model.Based on this utility model
Embodiment, the every other embodiment that those skilled in the art are obtained on the premise of not making creative work, all
Belong to the scope of this utility model protection.
It should also be noted that similar label and letter represent similar terms, therefore, the most a certain Xiang Yi in following accompanying drawing
Individual accompanying drawing is defined, then need not it be defined further and explains in accompanying drawing subsequently.Meanwhile, new in this practicality
In the description of type, term " first ", " second " etc. are only used for distinguishing and describe, and it is not intended that indicate or imply relatively important
Property.
Satellite communication is to utilize the telecommunication satellite operating on terrestrial space track to forward wireless signal, it is achieved ground two point
Or a kind of communication mode of multi-point communication.On satellite communication equipment the most on the ground, satellite antijam communication base is installed
Microarray strip, to realize above-mentioned communication.For the satellite antijam communication baseband chip with interference free performance, to chip
Performance requirement the highest, and Anti-interference algorithm to realize logic complicated, so that the pipe of satellite antijam communication baseband chip
Foot Numerous, chip package area is big, thus causes the packaging cost of chip higher, and encapsulation difficulty is the biggest, thus leads
Cause technical staff, during encapsulation, needs the biggest time cost and human cost, and makes satellite antijam communication
The resource consumption of baseband chip is big, power consumption is high.
In view of this, inventor observes and research discovery through long-term, it is provided that this satellite antijam communication base band a kind of
Chip application, in functional mode or test pattern, includes 23 pins altogether, the pipe to this satellite antijam communication baseband chip
Foot carries out multiplexing, can reduce number of pins, reduces chip production cost, decreases the package area of chip, reduces technology
Personnel's time cost during encapsulation and human cost, and beneficially satellite communication equipment Miniaturization Design.
Below by specific embodiment and combine accompanying drawing this utility model is described in further detail.
Refering to Fig. 1, a kind of satellite antijam communication baseband chip that this utility model embodiment one provides, this satellite is anti-dry
Disturbing communications baseband chip application in functional mode or test pattern, include 23 pins altogether, these 23 pins are respectively in function
Carrying out multiplexing under pattern and test pattern, in the functional mode, this satellite antijam communication baseband chip includes:
Radio frequency interface, for carrying out data transmission with a radio frequency chip；
Control interface, control data and state observation data for transfer process；
Mode selection interface, for selecting clock module, reset mode, interrupt mode；
Described test pattern includes scan logic pattern, memory built in self test of sram (Memory Build-in Self
Test, be called for short MBIST) pattern, input testing mode and output test pattern,
Under scan logic pattern, this satellite antijam communication baseband chip includes: scan logic interface, for defending this
Star antijam communication baseband chip carries out scan logic test；
Under MBIST pattern, this satellite antijam communication baseband chip includes: MBIST interface, for resisting this satellite
The memory module of interference communications baseband chip is tested；
Under input testing mode, this satellite antijam communication baseband chip includes: IO input interface, for I/O pin
Test during input signal；
Under output test pattern, this satellite antijam communication baseband chip includes: IO output interface, for I/O pin
Test during output signal.
Referring to table 1, in the functional mode, described radio frequency interface includes that 11 pins, described control interface include 7 pipes
Foot, described mode selection interface includes 5 pins.
Table 1
Further, referring to table 2, described radio frequency interface specifically includes 4 data out pin, 4 data input pipes
Foot, 1 sends enable pin, and 1 receives enable pin, and 1 data are transmitted with road clock pins, can be used for carrying out up simultaneously
Link, the communication data transfer of downlink；Described control interface includes 1 SPI chip selection signal pin, 1 SPI clock signal pipe
Foot, 4 SPI data pins, 1 effective pin of SPI data, can be used under wide scope clock frequency main control chip to interference resistant base band
Chip carries out configuring and state observation；Described mode selection interface includes 1 clock signal pin, 1 reset signal pin, 1
Individual reception interrupt signal pin, 1 sends interrupt signal pin, and 1 test enables signal pin, can be used for selecting chip operation
Required clock, reset and interrupt working manner, concrete pin sequence number, pin title and pin describe as shown in table 2.
Table 2
Fig. 1 shows chip pin multiplexing structural representation, enables the state of (TESTEN) according to test, when test enables
Time invalid, pad (PAD) is used as functional mode (func)；When test enables effective, pin is used as test pattern (test), then
Selecting (TEST_MODE) according to test pattern, pin can be used as scan pattern interface (scan), MBIST mode interface
(MBIST), IO input test interface (IO input), IO output test interface (IO output).
Under scan logic pattern, this satellite antijam communication baseband chip includes: described scan logic interface, described in patrol
Collect scan interface and include that 22 pins, described scan logic interface specifically include 7 scanning input pins, 7 scanning outlet tubes
Foot, 1 scanning enable pin, 1 comp enable pin, 1 occ pattern pin, 1 scan clock pin, 1 scan reset
Pin, 2 test pattern base pin selections, 1 test enable pin.The pin assignments of described scan logic interface, such as table 3 institute
Showing, wherein, "/" represents that this pin is not used by such a mode.
Table 3
Under MBIST pattern, described MBIST interface includes that 19 pins, described MBIST interface specifically include 1 storage
Device built-in self-test enable pin, 1 memory built in self test of sram failure signal pin, 1 memory built in self test of sram completes
Signal pin, 1 displacement enable pin, 1 misr clock pins, 7 misr output pins, 1 PLL (phaselocked loop) output letter
Number pin, 1 PLL (phaselocked loop) locking signal pin, 1 memory built in self test of sram clock pins, 1 memory built from
Test reset pin, 2 test pattern base pin selections, 1 test enable pin.The pin assignments of described MBIST interface such as table 4
Shown in, wherein, "/" represents that this pin is not used by such a mode.
Table 4
Under input testing mode, this satellite antijam communication baseband chip includes: IO input interface, and described IO input connects
Mouth includes that 23 pins, described IO input interface specifically include 17 input signal pins, 1 and output pin, 1 or output
Pin, 2 test pattern base pin selections, 1 test enable pin.The pin assignments of described IO input interface is as shown in table 5.
Table 5
Under output test pattern, this satellite antijam communication baseband chip includes that IO output interface, described IO output connect
Mouth includes that 23 pins, described IO output interface specifically include 19 clock division output pins, 1 clock input pin, 2
Test pattern base pin selection, 1 test enable pin, table 6 lists the pin assignments of IO output interface.
| Sequence number | Pin title | Signal name under output test pattern | Describe |
| 1 | ANTI_TXDATA0 | CLK_DIV_OUT | Clock division exports |
| 2 | ANTI_TXDATA1 | CLK_DIV_OUT | Clock division exports |
| 3 | ANTI_TXDATA2 | CLK_DIV_OUT | Clock division exports |
| 4 | ANTI_TXDATA3 | CLK_DIV_OUT | Clock division exports |
| 5 | ANTI_RXDATA0 | CLK_DIV_OUT | Clock division exports |
| 6 | ANTI_RXDATA1 | CLK_DIV_OUT | Clock division exports |
| 7 | ANTI_RXDATA2 | CLK_DIV_OUT | Clock division exports |
| 8 | ANTI_RXDATA3 | CLK_DIV_OUT | Clock division exports |
| 9 | ANTI_TXEN | CLK_DIV_OUT | Clock division exports |
| 10 | ANTI_RXEN | CLK_DIV_OUT | Clock division exports |
| 11 | ANTI_DATACLK | CLK_DIV_OUT | Clock division exports |
| 12 | ANTI_SPI_CS | CLK_DIV_OUT | Clock division exports |
| 13 | ANTI_SPI_SCLK | CLK_DIV_OUT | Clock division exports |
| 14 | ANTI_SPI_D0 | CLK_DIV_OUT | Clock division exports |
| 15 | ANTI_SPI_D1 | CLK_DIV_OUT | Clock division exports |
| 16 | ANTI_SPI_D2 | CLK_DIV_OUT | Clock division exports |
| 17 | ANTI_SPI_D3 | CLK_DIV_OUT | Clock division exports |
| 18 | ANTI_SPI_DATAVALID | CLK_DIV_OUT | Clock division exports |
| 19 | ANTI_CLK | CLK_IN | Clock inputs |
| 20 | ANTI_RESET | CLK_DIV_OUT | Clock division exports |
| 21 | ANTI_INT0 | TEST_MODE0 | Test pattern selects 0 |
| 22 | ANTI_INT1 | TEST_MODE1 | Test pattern selects 1 |
| 23 | ANTI_TESTEN | TESTEN | Test enables |
Table 6
The offer one satellite antijam communication baseband chip that this utility model provides, in the merit both meeting satellite communication
Can, meet again under the measurability of this satellite antijam communication baseband chip requires, to the pin of this chip at functional mode and not
Carry out multiplexing under same test pattern, simplified number of pins, reduced chip production cost, decreased the encapsulating face of chip
Long-pending, reduce technical staff's time cost during encapsulation and human cost, and beneficially satellite communication equipment is little
Typeization designs.
In description of the present utility model, in addition it is also necessary to explanation, unless otherwise clearly defined and limited, term " sets
Put ", should be interpreted broadly " installation ", " being connected ", " connection ", connect for example, it may be fixing, it is also possible to be to removably connect,
Or be integrally connected；Can be to be mechanically connected, it is also possible to be electrical connection；Can be to be joined directly together, it is also possible to pass through intermediary
It is indirectly connected to, can be the connection of two element internals.For the ordinary skill in the art, can manage with concrete condition
Solve above-mentioned term concrete meaning in this utility model.
It should also be noted that similar label and letter represent similar terms, therefore, the most a certain Xiang Yi in following accompanying drawing
Individual accompanying drawing is defined, then need not it be defined further and explains in accompanying drawing subsequently.
In description of the present utility model, " " center ", " on ", D score, "left", "right", " perpendicular it should be noted that term
Directly ", " level ", " interior ", the orientation of the instruction such as " outward " or position relationship be based on orientation shown in the drawings or position relationship, or
It is the orientation or position relationship usually put during the use of this utility model product, is for only for ease of description this utility model and letter
Change describe rather than instruction or the hint device of indication or element must have specific orientation, with specific azimuth configuration and
Operation, therefore it is not intended that to restriction of the present utility model.Additionally, term " first ", " second ", " the 3rd " etc. are only used for district
Divide and describe, and it is not intended that indicate or hint relative importance.
The foregoing is only preferred embodiment of the present utility model, be not limited to this utility model, for this
For the technical staff in field, this utility model can have various modifications and variations.All in spirit of the present utility model and principle
Within, any modification, equivalent substitution and improvement etc. made, within should be included in protection domain of the present utility model.
The foregoing is only preferred embodiment of the present utility model, be not limited to this utility model, for this
For the technical staff in field, this utility model can have various modifications and variations.All in spirit of the present utility model and principle
Within, any modification, equivalent substitution and improvement etc. made, within should be included in protection domain of the present utility model.It should be noted that
Arrive: similar label and letter represent similar terms in following accompanying drawing, therefore, are determined in the most a certain Xiang Yi accompanying drawing
Justice, then need not define it further and explain in accompanying drawing subsequently.
The above, detailed description of the invention the most of the present utility model, but protection domain of the present utility model does not limit to
In this, any those familiar with the art, in the technical scope that this utility model discloses, can readily occur in change
Or replace, all should contain within protection domain of the present utility model.Therefore, protection domain of the present utility model should be described with power
The protection domain that profit requires is as the criterion.
Claims (10)
1. a satellite antijam communication baseband chip, this satellite antijam communication baseband chip is applied to functional mode or survey
Die trial formula, it is characterised in that including 23 pins altogether, in the functional mode, this satellite antijam communication baseband chip includes:
Radio frequency interface, for carrying out data transmission with a radio frequency chip；
Control interface, control data and state observation data for transfer process；
Mode selection interface, for selecting clock module, reset mode, interrupt mode；
Described test pattern include scan logic pattern, MBIST (memory built in self test of sram) pattern, input testing mode and
Output test pattern,
Under scan logic pattern, this satellite antijam communication baseband chip includes: scan logic interface, for resisting this satellite
Interference communications baseband chip carries out scan logic test；
Under MBIST (memory built in self test of sram) pattern, this satellite antijam communication baseband chip includes: MBIST (memorizer
Built-in self-test) interface, for the memory module of this satellite antijam communication baseband chip is tested；
Under input testing mode, this satellite antijam communication baseband chip includes: IO input interface, for exporting I/O pin
Test during signal；
Under output test pattern, this satellite antijam communication baseband chip includes: IO output interface, for exporting I/O pin
Test during signal.
Satellite antijam communication baseband chip the most according to claim 1, it is characterised in that described radio frequency interface includes 11
Individual pin, described control interface includes 7 pins, and described mode selection interface includes 5 pins.
Satellite antijam communication baseband chip the most according to claim 2, it is characterised in that described radio frequency interface includes 4
Individual data out pin, 4 data in pin, 1 sends enable pin, and 1 receives enable pin, the transmission of 1 data with
Road clock pins.
Satellite antijam communication baseband chip the most according to claim 2, it is characterised in that described control interface includes 1
Individual SPI chip selection signal pin, 1 SPI clock signal pin, 4 SPI data pins, 1 effective pin of SPI data.
Satellite antijam communication baseband chip the most according to claim 2, it is characterised in that described mode selection interface bag
Including 1 clock signal pin, 1 reset signal pin, 1 receives interrupt signal pin, and 1 sends interrupt signal pin, 1
Test enables signal pin.
Satellite antijam communication baseband chip the most according to claim 1, it is characterised in that described scan logic interface bag
Including 22 pins, described MBIST (memory built in self test of sram) interface includes that 19 pins, described IO input interface include 23
Pin, described IO output interface includes 23 pins.
Satellite antijam communication baseband chip the most according to claim 6, it is characterised in that described scan logic interface bag
Include 7 scanning input pins, 7 scanning output pins, 1 scanning enable pin, 1 comp enable pin, 1 occ pattern
Pin, 1 scan clock pin, 1 scan reset pin, 2 test pattern base pin selections, 1 test enable pin.
Satellite antijam communication baseband chip the most according to claim 6, it is characterised in that described MBIST is (in memorizer
Build self-test) interface includes 1 memory built in self test of sram enable pin, 1 memory built in self test of sram failure signal pin,
1 memory built in self test of sram completes signal pin, 1 displacement enable pin, 1 misr clock pins, 7 misr outlet tubes
Foot, 1 PLL (phaselocked loop) output signal pin, 1 PLL (phaselocked loop) locking signal pin, 1 memory built in self test of sram
Clock pins, 1 memory built in self test of sram reseting pin, 2 test pattern base pin selections, 1 test enable pin.
Satellite antijam communication baseband chip the most according to claim 6, it is characterised in that described IO input interface includes
17 input signal pins, 1 and output pin, 1 or output pin, 2 test pattern base pin selections, 1 test enables
Pin.
Satellite antijam communication baseband chip the most according to claim 6, it is characterised in that described IO output interface bag
Include 19 clock division output pins, 1 clock input pin, 2 test pattern base pin selections, 1 test enable pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620408507.5U CN205749804U (en) | 2016-05-06 | 2016-05-06 | Satellite antijam communication baseband chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620408507.5U CN205749804U (en) | 2016-05-06 | 2016-05-06 | Satellite antijam communication baseband chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205749804U true CN205749804U (en) | 2016-11-30 |
Family
ID=57369580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620408507.5U Active CN205749804U (en) | 2016-05-06 | 2016-05-06 | Satellite antijam communication baseband chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205749804U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109739803A (en) * | 2018-12-03 | 2019-05-10 | 中国科学院国家空间科学中心 | A kind of configurable general asic chip integrated on a small scale |
-
2016
- 2016-05-06 CN CN201620408507.5U patent/CN205749804U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109739803A (en) * | 2018-12-03 | 2019-05-10 | 中国科学院国家空间科学中心 | A kind of configurable general asic chip integrated on a small scale |
| CN109739803B (en) * | 2018-12-03 | 2023-05-12 | 中国科学院国家空间科学中心 | Configurable universal small-scale integrated ASIC chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN205749803U (en) | Civil Satellite Communication baseband chip | |
| Vieira et al. | Survey on wireless sensor network devices | |
| Deb et al. | Wireless NoC as interconnection backbone for multicore chips: Promises and challenges | |
| CN101958733B (en) | Radio transmission system and electronic installation | |
| CN108605055A (en) | Programmable distributed data processing in serial link | |
| CN102624439B (en) | Integrated detection equipment for pico-satellite | |
| CN205749804U (en) | Satellite antijam communication baseband chip | |
| CN109444819A (en) | Radar system and its control method | |
| CN103399214B (en) | Spaceborne phased array receiving antenna test macro | |
| CN105807293B (en) | Veneer multiple antennas based on SOC determines appearance receiver | |
| CN101238679A (en) | Signal spectrum steering method, apparatus, and system | |
| CN104169828B (en) | High bandwidth communication device and system | |
| CN205229465U (en) | Baseband chip and multimode GNSS receiver of multimode GNSS receiver | |
| CN110113275A (en) | A kind of intelligence multichannel wideband interferer signal generation device | |
| Deb et al. | Wireless network-on-chip: a new era in multi-core chip design | |
| CN101887130B (en) | Programmable navigational satellite spread spectrum sequence generator | |
| CN107015063A (en) | Wide band multi-channel Correlation receiver and method of reseptance | |
| US7774665B2 (en) | Apparatus for testing a phrase-locked loop in a boundary scan enabled device | |
| CN208046596U (en) | A kind of transmission channel signal processing system for multi-channel digital TR components | |
| CN205749909U (en) | satellite communication navigation chip | |
| Li et al. | Near-field beamforming for STAR-RIS networks | |
| CN205829624U (en) | Dual-use communications baseband chip | |
| CN201282455Y (en) | Digital fiber-optical discharging-directly machine system | |
| CN207457341U (en) | Three-phase and four-line RF intelligent electric meters | |
| CN103297002B (en) | A kind of method and apparatus of AF panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Liu Jiehua Inventor after: Ma Wenbo Inventor after: Jing Jun Inventor after: Jiang Ke Inventor before: Liu Jiehua Inventor before: Ma Wenbo Inventor before: Jing Jun |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200722 Address after: 610000 Sichuan city of Chengdu province Tianfu Zheng Xing Shun Shing Street No. 172 Patentee after: Huali Zhixin (Chengdu) integrated circuit Co., Ltd Address before: 100080, No. 18, building No. 8, hospital B, West Wang Xi Road, Haidian District, Beijing Patentee before: HWA CREATE Corp.,Ltd. |