CN218524823U

CN218524823U - FT test system of power supply chip

Info

Publication number: CN218524823U
Application number: CN202220740720.1U
Authority: CN
Inventors: 邓宁杰; 肖文勇; 何利蓉
Original assignee: Hangzhou Xiongmai Integrated Circuit Technology Co Ltd
Current assignee: Zhejiang Xinmai Microelectronics Co ltd
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2023-02-24
Anticipated expiration: 2032-03-31

Abstract

The invention relates to an FT test system of a power supply chip, wherein an ARM processor and the power supply chip are integrated on a test board, a test machine is connected with the test board through a feedback GPIO port, the ARM processor pulls down or pulls up a level voltage signal of the feedback GPIO port according to test data to generate a high level voltage signal or a low level voltage signal, and the high level voltage signal or the low level voltage signal is transmitted to a signal port of the test machine, so that the test machine only needs to have a high level and low level judgment function, the requirements on the quality and the function of the test machine are reduced, the difficulty of programming on the test machine is further reduced, the selection requirement on the test machine is low, and the cost is saved.

Description

FT test system of power supply chip

Technical Field

The application relates to the technical field of chip testing, in particular to an FT testing system of a power supply chip.

Background

The FT Test, a Functional Test, is a Test for performing a power-on Test on an electrical component to Test whether the electrical component can normally operate. Different from ICT test, flying probe, AOI test, X-Ray test and other test methods, FT test can obtain the test result of whether the electrical element can be normally used or not very intuitively, so that the method is widely used for testing the power supply chip.

The existing FT test method of the power supply chip is to directly place the power supply chip on a test machine, connect the test machine and the power supply chip through the existing circuit of the test machine, then control the test machine to send an electric signal to the power supply chip, and finally judge whether the function of the power supply chip is normal or not through a feedback signal returned by the power supply chip.

However, when the FT test method is used, a power chip test program needs to be written in a tester in advance, and the programming process is complex and difficult, which leads to a greatly increased complexity of the test process and is very inconvenient to debug.

SUMMERY OF THE UTILITY MODEL

Therefore, it is necessary to provide an FT test system for a power supply chip, which aims at the problems of the conventional FT test method for the power supply chip that the programming flow of the tester is complicated and the difficulty is high, which leads to greatly increased complexity of the test flow and inconvenient debugging.

The application provides a power chip's FT test system includes:

the tester comprises a signal port and a power port;

the test board comprises a power supply interface, and the power supply interface of the test board is connected with the power supply port of the tester through a power supply line;

the ARM processor is integrated on the test board; the ARM processor comprises a plurality of test GPIO ports and is used for transmitting test data; the ARM processor also comprises a feedback GPIO port, and the feedback GPIO port is connected with a signal port of the tester through a signal wire;

and the power supply chip is integrated on the test board and comprises a plurality of functional modules, and each functional module is connected with one test GPIO port of the ARM processor through a pin of the functional module.

Further, the ARM processor further comprises:

the DAC circuit module is connected with each GPIO testing port and used for converting digital signals into analog signals;

the ADC circuit module is connected with each GPIO test port and is used for converting the analog signals into digital signals;

and the timer circuit module is connected with each GPIO test port and used for providing a timing function.

Further, the ARM processor further comprises a first I2C communication module, and the power supply chip further comprises a second I2C communication module; the first I2C communication module and the second I2C communication module are in communication connection through a clock line and a data line.

Further, the power supply chip further includes:

the IRCUT circuit module is used for switching the camera filter;

and the loudspeaker circuit module is used for playing sound.

Further, the power supply chip further includes:

the power-on reset circuit module is used for power-on reset;

the AES circuit module is used for executing an AES encryption algorithm;

the DC-DC circuit module is used for converting one path of externally introduced voltage signals into a plurality of paths of voltage signals with different voltage values;

furthermore, the DC-DC circuit module is configured to convert an externally-introduced 5V voltage signal into a 1V voltage signal, a 1.8V voltage signal, and a 3.3V voltage signal.

Further, the power supply chip further includes:

a battery module connected with the second I2C communication module;

further, the power supply chip further includes:

and the stepping motor driving circuit module is connected with the second I2C communication module.

Further, the ARM processor further includes:

the first test GPIO port is connected with a pin of the IRCUT circuit module;

the second test GPIO port is connected with a pin of the loudspeaker circuit module;

the third test GPIO port is connected with a pin of the power-on reset circuit module;

the fourth test GPIO port is connected with a pin of the AES circuit module;

the fifth test GPIO port is connected with a pin of the DC-DC circuit module;

the sixth test GPIO port is connected with the pin of the battery module;

the seventh test GPIO port is connected with the pin of the stepping motor driving circuit module;

further, the length of a connecting wire between each test GPIO port and a pin of a functional module connected with the test GPIO port is less than 2000mil.

The application provides a FT test system of power chip, through with ARM treater and power chip integration on a test board, the test machine is connected through a feedback GPIO mouth with the test board, the ARM treater draws the level voltage signal of low or high feedback GPIO mouth according to test data to produce high level voltage signal or low level voltage signal, and with high level voltage signal or low level voltage signal transmission to the signal port of test machine, consequently only need the test machine have the high low level judge function can, reduced to the requirement on test machine quality and function, and then reduced the degree of difficulty of programming on the test machine, and the selection requirement to the test machine is low, has saved the cost.

Drawings

Fig. 1 is a schematic structural diagram of an FT test system of a power chip according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of an FT test system of a power chip according to another embodiment of the present application.

Fig. 3 is a schematic structural diagram of an FT test system of a power chip according to another embodiment of the present application.

Reference numerals:

10-a testing machine; 110-a signal port; 120-power port; 20-test board; 210-a power interface;

30-ARM processor; 310-test GPIO port; 320-feedback GPIO port; 330-DAC circuit module 340-ADC circuit module; 350-a timer circuit module; 360-a first I2C communication module;

381-a first test GPIO port; 382-a second test GPIO port; 383-a third test GPIO port;

384-fourth test GPIO port; 385-a fifth test GPIO port; 386-a sixth test GPIO port;

387-a seventh test GPIO port; 40-a power supply chip; 400-a functional module;

410-a second I2C communication module; 420-IRCUT circuit block; 430-speaker circuit module;

431-an operational amplifier; 431 a-the output of the operational amplifier;

431 b-the positive power supply terminal of the operational amplifier; 431 c-the negative power supply terminal of the operational amplifier;

431 d-inverting input of operational amplifier; 431 e-the non-inverting input of the operational amplifier;

431 f-the output of the operational amplifier; 432-a third resistance; 433-a fourth resistor; 434-fifth resistance;

435-sixth resistor; 436-seventh resistance; 437-inductance; 438-speaker power amplifier circuit;

439-power supply; 440-power on reset circuit module; 450-AES circuit module;

460-DC-DC circuit module; 470-a battery module; 480-a stepping motor driving circuit module;

50-a power line; 60-signal lines; 710-a first resistance; 720-a second resistance;

730-a capacitance; 730-an eighth resistance; 740-ninth resistor.

Detailed Description

For the purpose of making the technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The application provides a power supply chip's FT test system. It should be noted that the FT test system for power supply chips provided by the present application is applicable to the test of any kind and model of power supply chip, and the test of power supply chips mounted on any equipment or device.

As shown in FIG. 1, in one embodiment of the present application, an FT test system for power chips includes a tester 10, a test board 20, an ARM processor 30, and a power chip 40.

The tester 10 includes a signal port 110 and a power port 120. The test board 20 includes a power interface 210. The power interface 210 of the test board 20 is connected to the power port 120 of the tester 10 via a power line 5050.

The ARM processor 30 is integrated on the test board 20. The ARM processor 30 includes a plurality of test GPIO ports 310. The test GPIO port 310 is used to transmit test data. The ARM processor 30 also includes a feedback GPIO port 320. The feedback GPIO port 320 is connected to the signal port 110 of the test machine 10 via a signal line 60. The ARM processor 30 pulls down or pulls up the level voltage signal of the feedback GPIO port 320 according to the test data, thereby generating a high level voltage signal or a low level voltage signal, and transmitting the high level voltage signal or the low level voltage signal to the signal port 110 of the test machine 10.

The power source chip 40 is integrated on the test board 20. The power supply chip 40 includes a plurality of functional modules 400. Each functional module 400 is connected with one test GPIO port 310 of the ARM processor 30 through pins of the functional module 400.

Specifically, the ARM processor 30 may be an STM32F103 single chip microcomputer, and is good in stability. Each functional module 400 is connected with a test GPIO port 310 of the ARM processor 30 through pins of the functional module 400. For the sake of simplicity of the contents shown in the figures, the pins of the functional module 400 are not shown in the figures.

The testing machine 10 is provided with an MCU, the signal port 110 and the power supply port 120 are ports on the MCU, and the signal port 110 is connected to the feedback GPIO port 320 through a signal line 60. The signal line 60 is used to transmit signals. The power port 120 on the MCU of the tester 10 is connected to the power interface 210 on the ARM processor 30 via a power cord 50. The power cord 50 is used to deliver electrical energy. It can be seen that only 1 signal line 60 and 1 power line 50 are required for connection between the test board 20 and the tester 10, and the connection method is simple.

The operating principle of the FT test system of the power supply chip 40 provided in this embodiment is:

ARM processor 30 enables each functional module 400 of power chip 40 by controlling registers within power chip 40. In this process, ARM processor 30 collects test data of voltage, cycle, etc. of each functional module 400. ARM processor 30 includes a plurality of test GPIO ports 310. Each test GPIO port 310 is used to transmit test data for one type (or class) of test.

The ARM processor 30 further pulls down or pulls up the level voltage signal of the feedback GPIO port 320 according to the test data, thereby generating a high level voltage signal or a low level voltage signal, and transmitting the high level voltage signal or the low level voltage signal to the signal port 110 of the testing machine 10. The MCU of the testing machine 10 determines the test result by detecting the voltage value of the high level voltage signal or the low level voltage signal at the signal port 110.

Alternatively, the voltage value of the low-level voltage signal is 0, and the voltage value of the high-level voltage signal is 3.3V. For example, if the test machine 10 detects that the voltage of the signal port 110 is 0V, it represents that the test is abnormal, and the power chip 40 fails. If the test detects that the voltage of the signal port 110 is 3.3V, it represents that the test is normal, and the power chip 40 is qualified.

Optionally, the voltage value of the low-level voltage signal is in a value range of 0V or more and 0.5V or less, and the voltage value of the high-level voltage signal is in a value range of 3V or more and 3.3V or less. Because the actual circuit has certain voltage fluctuation, a certain numerical range is adopted instead of a fixed value to judge whether the test is normal, and the actual condition is better met.

The test board 20 is a PCB board. Optionally, test board 20 is a double-sided PCB board. The double-sided PCB board comprises a Top Layer (Top Layer) and a Bottom Layer (Bottom Layer), wherein copper is coated on two sides, an insulating Layer is arranged in the middle of the Top Layer and the Bottom Layer, both sides can be wired, and the Top Layer and the Bottom Layer are generally communicated through a through hole or a bonding pad. The double-sided PCB can be used for a more complex circuit, is an ideal PCB, and can reduce the manufacturing cost of the PCB.

In this embodiment, the present application provides an FT testing system of a power chip 40, wherein an ARM processor 30 and the power chip 40 are integrated on a testing board 20, the testing board 20 is connected to the testing board 20 through a feedback GPIO port 320, and the ARM processor 30 pulls down or pulls up a level voltage signal of the feedback GPIO port 320 according to testing data, so as to generate a high level voltage signal or a low level voltage signal, and transmit the high level voltage signal or the low level voltage signal to a signal port 110 of the testing machine 10, so that the testing machine 10 only needs to have a function of determining a high level and a low level, thereby reducing requirements on quality and functions of the testing machine 10, further reducing difficulty in programming on the testing machine 10, and having low requirements on selection of the testing machine 10, and saving cost.

In addition, the test board 20 in the FT test system of the power chip 40 provided in this embodiment is small in size, and if the number of functional modules 400 to be tested needs to be increased or decreased, only the circuit connection mode needs to be modified on the test board 20, which is very convenient for debugging.

As shown in fig. 2, in an embodiment of the present application, the ARM processor 30 further includes a DAC circuit module 330, an ADC circuit module 340, and a timer circuit module 350. The DAC circuit is connected to each GPIO testing port 310, and is configured to convert a digital signal into an analog signal. The ADC circuit is connected to each GPIO port 310 for converting analog signals into digital signals. The timer circuit is connected with each testing GPIO port 310 and is used for providing a timing function.

Specifically, the DAC circuit module 330, the ADC circuit module 340 and the timer circuit module 350 respectively provide the ARM processor 30 with digital-to-analog, analog-to-digital and timer functions, so that these functions can be applied to the test flow of the power chip 40 to cooperate with the completion of the test operation.

Optionally, the ARM processor 30 further comprises an interrupt module for responding to an event occurring in the system.

As shown in FIG. 2, in one embodiment of the present application, the ARM processor 30 further includes a first I2C communication module 360. The power chip 40 also includes a second I2C communication module 410. The first I2C communication module 360 is communicatively coupled to the second I2C communication module 410 via a clock line and a data line.

Specifically, the ARM processor 30 and the power chip 40 communicate in an I2C communication manner, so that the ARM processor 30 can collect test data of each functional module 400 in the power chip 40, and the subsequent ARM processor 30 can feed back a test result to the testing machine 10 in a manner of pulling up or pulling down the test GPIO port 310.

As shown in fig. 2, in an embodiment of the present application, the power chip 40 includes an IRCUT circuit module 420 and a speaker circuit module 430. The IRCUT circuit module 420 is used to switch the camera filter. The speaker circuit module 430 is used to play sound.

Specifically, the IRCUT circuit module 420 and the speaker circuit module 430 are both one of the functional modules 400.

The power chip 40 in this embodiment is applied to an electronic device or an electronic apparatus having a camera and a speaker, such as a camera, a mobile phone, a tablet computer, a notebook computer, and the like.

The IRCUT circuit module 420 is used to switch a camera filter in an electronic device. Therefore, the FT test system of the power supply chip 40 provided by the present application can be used to test whether the switching function of the camera filter is normal.

The speaker circuit module 430 is used for playing sound through a speaker. Therefore, the FT test system of the power supply chip 40 provided by the present application can be used to test whether the speaker can normally play sound.

As shown in fig. 2, in an embodiment of the present application, the power chip 40 further includes a power-on reset circuit module 440, an AES circuit module 450, and a DC-DC circuit module 460. The power-on reset circuit module 440 is used for power-on reset. The AES circuit block 450 is used to perform an AES encryption algorithm. The DC-DC circuit module 460 is configured to convert one path of externally introduced voltage signal into multiple paths of voltage signals with different voltage values.

Specifically, the power-on reset circuit module 440, the AES circuit module 450, and the DC-DC circuit module 460 are all one of the functional modules 400. The power-on reset circuit module 440 is used for power-on reset operation. The power-on reset operation refers to an operation in which the electronic device mounted with the power supply chip 40 initializes all the functional modules 400 at each power-on. Therefore, the FT test system of the power supply chip 40 provided by the present application can be used to test whether the speaker can normally perform the power-on reset operation.

The AES circuit block 450 is configured to perform an AES encryption algorithm. The AES Encryption algorithm, advanced Encryption Standard (AES), is a symmetric Encryption algorithm used in many operations of an electronic device equipped with the power chip 40. For example, the AES encryption algorithm may be used to log into a user account of the electronic device. Therefore, the FT test system of the power supply chip 40 provided by the present application can be used to test whether the AES encryption algorithm can operate normally.

The DC-DC circuit module 460 is configured to convert one path of externally introduced voltage signal into multiple paths of voltage signals with different voltage values. For example, the DC-DC circuit module 460 may convert an externally introduced 5V DC voltage into a 1V DC voltage. The FT test system of the power supply chip 40 provided in the present application can be used to test whether the DC-DC circuit can normally convert the voltage.

In an embodiment of the present application, the DC-DC circuit module 460 is configured to convert an externally-introduced 5V voltage signal into a 1V voltage signal, a 1.8V voltage signal, and a 3.3V voltage signal.

Specifically, the DC-DC circuit module 460 can convert an externally-introduced 5V voltage signal into three voltage signals with different voltage values, so as to adapt to the voltage requirements of different loads connected to the power chip 40.

As shown in fig. 2, in an embodiment of the present application, the power chip 40 further includes a battery module 470 and a stepping motor driving circuit module 480. The battery module 470 is used to provide electric energy. The step motor driving circuit module 480 is used for driving a step motor.

Specifically, the battery module 470 and the stepping motor driving circuit module 480 are one of the functional modules 400. The battery module 470 may be a lithium battery module. The battery module 470 may temporarily supply power to the electronic device mounted with the power chip 40 when the electronic device suddenly loses power supply. Therefore, the FT test system of the power supply chip 40 provided by the present application can be used to test whether the power supply function of the battery module 470 is normal.

The power supply chip 40 in the present embodiment is applied to an apparatus or device having a stepping motor. The stepping motor driving circuit is used for driving a stepping motor. Therefore, the FT test system of the power supply chip 40 provided by the present application can be used to test whether the stepper motor driving circuit can normally drive the motor shaft of the stepper motor to rotate.

As shown in fig. 2, in an embodiment of the present application, the ARM processor 30 further includes a first test GPIO port 381, a second test GPIO port 382, a third test GPIO port 383, a fourth test GPIO port 384, a fifth test GPIO port 385, a sixth test GPIO port 386, and a seventh test GPIO port 387.

The first test GPIO port 381 is connected to a pin of the IRCUT circuit module 420. The second test GPIO port 382 is connected to a pin of the speaker circuit module 430. The third test GPIO port 383 is connected to a pin of the power-on reset circuit module 440. The fourth test GPIO port 384 is connected to a pin of the AES circuit module 450. The fifth test GPIO port 385 is connected to a pin of the DC-DC circuit module 460. The sixth test GPIO port 386 is connected to a pin of the battery module 470. And the seventh test GPIO port 387 is connected with a pin of the stepping motor driving circuit module 480.

Specifically, the DAC circuit block 330, the ADC circuit block 340 and the timer circuit block 350 are connected to each GPIO port 310.

Optionally, as shown in fig. 3, a first resistor 710 and a second resistor 720 are further included between the IRCUT circuit module 420 and the first test GPIO port 381. One end of the first resistor 710 is grounded, and the other end of the first resistor 710 is connected in series with the second resistor 720. One end of the second resistor 720 is connected in series with the first resistor 710, and the other end of the second resistor 720 is connected to the IRCUT circuit. The resistance value of the first resistor 710 may be 10 kilo-ohms. The resistance value of the second resistor 720 may be 10 kilo-ohms.

As shown in fig. 3, the speaker circuit module 430 includes an operational amplifier 431, a third resistor 432, a fourth resistor 433, a fifth resistor 434, a sixth resistor 435, a seventh resistor 436, an inductor 437 and a speaker power amplifier circuit 438. The output 431a of the operational amplifier 431 is connected to the second test GPIO port 382. The positive power supply terminal 431b of the operational amplifier 431 is connected to a power supply source 439. The negative power supply terminal 431c of the operational amplifier 431 is grounded. A third resistor 432 is connected between the non-inverting input terminal 431e of the operational amplifier 431 and the speaker power amplifier circuit 438. The fourth resistor 433 and the inductor 437 are connected in series to form a first branch (not labeled in the drawing of the first branch). One end of the first branch is connected to the connection link between the third resistor 432 and the speaker power amplifier circuit 438. The other end of the first branch is connected to a speaker power amplifier circuit 438. One end of the fifth resistor 434 is connected to the inverting input terminal 431d of the operational amplifier 431. The other end of the fifth resistor 434 is connected to the connection link between the fourth resistor 433 and the inductor 437. Another second branch (not numbered in the second branch) is led out from the connection link between the inverting input terminal 431d of the operational amplifier 431 and the fifth resistor 434, and a sixth resistor 435 is disposed on the second branch. One end of the sixth resistor 435 is connected to the connection link between the inverting input terminal 431d of the operational amplifier 431 and the fifth resistor 434, and the other end of the sixth resistor 435 is grounded. A seventh resistor 436 is further connected between the output end 431a of the operational amplifier 431 and the non-inverting input end 431e of the operational amplifier 431.

As shown in fig. 3, a capacitor 730 is further disposed between the battery module 470 and the sixth test GPIO port 386. The positive plate of the capacitor 730 is connected to the connection link between the battery module 470 and the sixth test GPIO port 386. The negative plate of the capacitor 730 is grounded.

An eighth resistor 730 and a ninth resistor 740 are further arranged between the stepping motor driving circuit module 480 and the seventh test GPIO port 387. One end of the eighth resistor 730 is grounded, and the other end of the eighth resistor 730 is connected to the ninth resistor 740. The ninth resistor 740 has one end connected to the eighth resistor 730 and the other end connected to the step motor driving circuit module 480. The seventh test GPIO port 387 is connected to the connection link between the eighth resistor 730 and the ninth resistor 740.

Specifically, the work flow of the FT test system of the power chip 40 provided in this embodiment is as follows:

s1, testing the power-on reset time of the power chip 40, the voltage of the IRCUT circuit module 420, the period and voltage of the speaker power amplifier circuit 438 in the speaker circuit module 430, the period and voltage of the stepping motor driving circuit module 480, and the like through the functions provided by the DAC circuit module 330, the ADC circuit module 340, the timer circuit module 350, and the like of the ARM processor 30.

And S2, detecting the voltages of the DC-DC circuit module 460 and the battery module 470 of the power chip 40 by using the ADC function of the ARM processor 30, and converting the 5V direct-current voltage of the externally introduced DC-DC circuit module 460 into three voltages of 1V, 1.8V and 3.3V.

And S3, judging whether the read AES ciphertext is consistent with a theoretical value or not by configuring a register in the AES circuit module 450 in the power chip 40.

And S4, storing the test results of all the functional modules 400 in a return value 0 or-1 mode in a specially defined structural body mode.

S5, the ARM processor 30 pulls up or pulls down the feedback GPIO port 320 connected with the test machine 10 through judging the return value (0 or-1) in the structural body, the test machine 10 judges the test result after detecting the voltage of the feedback GPIO port 320, the GPIO voltage is high (namely 3-3.3V) to represent that the test is normal, the GPIO voltage is low (namely 0V-0.5V) to represent that the test is abnormal, and finally qualified chips are selected.

In one embodiment of the present application, the length of the connection wire between each test GPIO port 310 and the pin of the functional module 400 connected thereto is less than 2000 mils.

Specifically, the length of the connection wire is the running length. mil is mil, 1mil =1/1000inch (= 0.0254mm (millimeter).

In combination with the previous embodiment, the length of the connection wire between the first test GPIO port 381 and the pin of the IRCUT circuit module 420 is less than 2000mil. The length of the connecting wire between the second test GPIO port 382 and the pin of the speaker circuit module 430 is less than 2000mil. And the length of a connecting wire between the third test GPIO port 383 and the pin of the power-on reset circuit module 440 is less than 2000mil. The length of a connecting wire between the fourth test GPIO port 384 and the pin of the AES circuit module 450 is less than 2000mil. The length of the connecting wire between the fifth test GPIO port 385 and the pin of the DC-DC circuit module 460 is less than 2000mil. The length of the connection wire between the sixth test GPIO port 386 and the pin of the battery module 470 is less than 2000 mils. And the length of a connecting wire between the seventh test GPIO port 387 and the pin of the stepping motor driving circuit module 480 is less than 2000mil.

The technical features of the embodiments described above may be arbitrarily combined, the order of execution of the method steps is not limited, and for simplicity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the combinations of the technical features should be considered as the scope of the present description.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An FT test system of a power supply chip, comprising:

the tester comprises a signal port and a power supply port;

2. The FT test system of a power chip of claim 1, wherein the ARM processor further comprises:

3. The FT test system of a power chip of claim 2, wherein the ARM processor further comprises a first I2C communication module, the power chip further comprising a second I2C communication module; the first I2C communication module and the second I2C communication module are in communication connection through a clock line and a data line.

4. The FT test system of a power supply chip according to claim 3, wherein the power supply chip includes:

the IRCUT circuit module is used for switching the camera filter;

and the loudspeaker circuit module is used for playing sound.

5. The FT test system of a power supply chip according to claim 4, wherein the power supply chip further comprises:

the power-on reset circuit module is used for power-on reset;

the AES circuit module is used for executing an AES encryption algorithm;

and the DC-DC circuit module is used for converting one path of externally introduced voltage signals into a plurality of paths of voltage signals with different voltage values.

6. The FT test system for power supply chips of claim 5, wherein the DC-DC circuit module is configured to convert an externally-introduced 5V voltage signal into a 1V voltage signal, a 1.8V voltage signal and a 3.3V voltage signal.

7. The FT test system of a power supply chip of claim 6, further comprising:

and the battery module is used for providing electric energy.

8. The FT test system of a power supply chip of claim 7, wherein the power supply chip further comprises:

and the stepping motor driving circuit module is used for driving the stepping motor.

9. The FT test system of a power chip of claim 8, wherein the ARM processor further comprises:

the first test GPIO port is connected with a pin of the IRCUT circuit module;

the fourth test GPIO port is connected with a pin of the AES circuit module; the fifth test GPIO port is connected with a pin of the DC-DC circuit module;

the sixth test GPIO port is connected with the pin of the battery module;

and the seventh test GPIO port is connected with the pin of the stepping motor driving circuit module.

10. The FT test system of a power supply chip of claim 9, wherein a length of a connection wire between each test GPIO port and a pin of a functional module connected thereto is less than 2000 mils.